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Change subject: Revert "drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory region"
......................................................................
Patch Set 1:
(1 comment)
File src/drivers/intel/fsp2_0/hob_verify.c:
https://review.coreboot.org/c/coreboot/+/56163/comment/56049923_153a8e90
PS1, Line 52:
> this doesn't need to be checked any more and i'm not even 100% certain if the second part of the con […]
tl;dr there is nothing to check if we do not ask the FSP to increase bootloader TOLUM size.
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Change subject: sb/intel/common: Hide IFD options if !HAVE_IFD_BIN
......................................................................
Patch Set 4:
(1 comment)
File src/southbridge/intel/common/firmware/Kconfig:
https://review.coreboot.org/c/coreboot/+/56107/comment/26c2b512_408841ee
PS2, Line 106:
: config MAINBOARD_USES_IFD_GBE_REGION
: def_bool n
> Went with PS1 approach, which is simpler and works.
About `MAINBOARD_USES_IFD_GBE_REGION`: mainboards are expected to select it, so that prompts for the GbE region are only shown when necessary. It thus shouldn't be guarded by `HAVE_IFD_BIN`.
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Change subject: supermicro/x11-lga1151-series: Remove SkipExtGfxScan = 1
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
> FSP does this:
> ...
That's proves me right, doesn't it? i.e. for IVD, it only matters that
`PrimaryDisplay != (IGD, Auto)`.
> TL;DR IVD does not only depend on SkipExtGfxScan, but also on InternalGfx, PrimaryDisplay
I think you are reading it wrong. `PrimaryDisplay` is what matters most
for IVD: `IVD = PrimaryDisplay != IGD`. The other options just provide some
constraints for `PrimaryDisplay`, e.g. if not `SkipExtGfxScan` and something
is found, `Auto` is not turned into `IGD`; if not `InternalGfx`, `IGD` is not
an option for `PrimaryDisplay`.
I assume (no time to check right now), that the difference between `PCH_PCIe`
and `PEG` for `PrimaryDisplay` is only about bridge settings that coreboot
overwrites anyway. If that is the case, all that matters here is to set
`PrimaryDisplay != (Auto, IGD)`. If the options are too confusing, please
just test it.
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Change subject: sb/intel/common: Hide IFD options if !HAVE_IFD_BIN
......................................................................
Patch Set 4:
(1 comment)
File src/southbridge/intel/common/firmware/Kconfig:
https://review.coreboot.org/c/coreboot/+/56107/comment/189dc211_2211282e
PS2, Line 31: depends on HAVE_IFD_BIN
> Probably. I could even include IFD_BIN_PATH in the guard. […]
Went with PS1 approach
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Change subject: sb/intel/common: Hide IFD options if !HAVE_IFD_BIN
......................................................................
Patch Set 3:
(1 comment)
File src/southbridge/intel/common/firmware/Kconfig:
https://review.coreboot.org/c/coreboot/+/56107/comment/196d5cb1_052fde7f
PS2, Line 106:
: config MAINBOARD_USES_IFD_GBE_REGION
: def_bool n
> Looks like mainboards have been selecting this unconditionally. […]
Went with PS1 approach, which is simpler and works.
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56173 )
Change subject: soc/intel/common/irq: Account for single-function devices
......................................................................
Patch Set 1:
(3 comments)
Patchset:
PS1:
> > not required […]
Correct, just PCI_INT_A
File src/soc/intel/common/block/irq/irq.c:
https://review.coreboot.org/c/coreboot/+/56173/comment/ada6f267_6bb42e0e
PS1, Line 257: IRQ_NONE
> Should this be `!= IRQ_NONE` or `== IRQ_PIRQ`? What happens if there are multiple functions but only […]
this is wrong anyway
https://review.coreboot.org/c/coreboot/+/56173/comment/527cef35_02ed10b6
PS1, Line 266: /* Single-function devices must use PIRQ_A */
> BTW, is the requirement that the single-function device must use PIRQ_A? Or is it that it must use I […]
haha, looks like I misread my own notes (double checked in the BWG, it is INTA, not PIRQ_A). Which basically means this was unnecessary, `find_free_pin()` will always start with PCI_INT_A, so you would have to construct a slot so as to violate this constraint (fixed pins B,C,D only, no PIRQs, no DIRECT either).
tl;dr this change can be dropped.
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Hello build bot (Jenkins), Nico Huber, Paul Menzel, Tim Wawrzynczak, Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56107
to look at the new patch set (#4).
Change subject: sb/intel/common: Hide IFD options if !HAVE_IFD_BIN
......................................................................
sb/intel/common: Hide IFD options if !HAVE_IFD_BIN
When `HAVE_IFD_BIN` is not enabled, do not show IFD-related options.
Change-Id: I8736f32b4c695efbd68adf551e1376726c718b56
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/southbridge/intel/common/firmware/Kconfig
1 file changed, 3 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/56107/4
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56005 )
Change subject: soc/intel/common/block/acpi: Add LPM requirements support to PEPD _DSM
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/common/block/acpi/pep.c:
https://review.coreboot.org/c/coreboot/+/56005/comment/21b138da_435ae62f
PS2, Line 142: static void pep_s0ix_collect_lpm_requirements(void *unused)
> Can we have separate functions: one to read out register value to a buffer and returns status and ot […]
Sure, I like that, done.
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