coreboot-gerrit July 2021

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Change in coreboot[master]: security/intel/txt: add missing cpu/x86/msr.h include
by Felix Held (Code Review) 09 Jul '21

09 Jul '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56186 ) Change subject: security/intel/txt: add missing cpu/x86/msr.h include ...................................................................... security/intel/txt: add missing cpu/x86/msr.h include msr_t and a few other things used in here are defined in cpu/x86/msr.h, so include it directly in this file. Change-Id: I7a3299381ff54b7665620861dec60642f27bac8d Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/security/intel/txt/common.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/56186/1 diff --git a/src/security/intel/txt/common.c b/src/security/intel/txt/common.c index 437c55e..239e152 100644 --- a/src/security/intel/txt/common.c +++ b/src/security/intel/txt/common.c @@ -6,6 +6,7 @@ #include <cpu/x86/cr.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> +#include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <lib.h> #include <smp/node.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/56186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a3299381ff54b7665620861dec60642f27bac8d Gerrit-Change-Number: 56186 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/*/mca: use mca_get_bank_count()
by Felix Held (Code Review) 09 Jul '21

09 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56185 ) Change subject: soc/amd/*/mca: use mca_get_bank_count() ...................................................................... soc/amd/*/mca: use mca_get_bank_count() Use the common mca_get_bank_count function instead of open-coding the functionality to get the MCA bank number. Also re-type the num_banks variable from signed in to unsigned int, since the number of MCA bank is always positive. Change-Id: I126767cf9ad468cab6d6537dd73e9b2dc377b5c4 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/mca.c M src/soc/amd/stoneyridge/mca.c 2 files changed, 4 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/56185/1 diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index 2576f6e..9e2b5e2 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -152,12 +152,10 @@ void check_mca(void) { int i; - msr_t cap; struct mca_bank mci; - int num_banks; + unsigned int num_banks; - cap = rdmsr(IA32_MCG_CAP); - num_banks = cap.lo & MCA_BANKS_MASK; + num_banks = mca_get_bank_count(); for (i = 0 ; i < num_banks ; i++) { mci.sts = rdmsr(MCAX_STATUS_MSR(i)); diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index b1f955f..910ccac 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -151,12 +151,10 @@ void check_mca(void) { int i; - msr_t cap; struct mca_bank mci; - int num_banks; + unsigned int num_banks; - cap = rdmsr(IA32_MCG_CAP); - num_banks = cap.lo & MCA_BANKS_MASK; + num_banks = mca_get_bank_count(); if (is_warm_reset()) { for (i = 0 ; i < num_banks ; i++) { -- To view, visit https://review.coreboot.org/c/coreboot/+/56185 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I126767cf9ad468cab6d6537dd73e9b2dc377b5c4 Gerrit-Change-Number: 56185 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/amd/*/model_*_init: use mca_get_bank_count()
by Felix Held (Code Review) 09 Jul '21

09 Jul '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56184 ) Change subject: cpu/amd/*/model_*_init: use mca_get_bank_count() ...................................................................... cpu/amd/*/model_*_init: use mca_get_bank_count() Use the common mca_get_bank_count function instead of open-coding the functionality to get the MCA bank number. Also re-type the num_banks variable from signed in to unsigned int, since the number of MCA bank is always positive. Change-Id: I70ad423aab484cf4ec8f51b43624cd434647aad4 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/cpu/amd/agesa/family14/model_14_init.c M src/cpu/amd/agesa/family15tn/model_15_init.c M src/cpu/amd/agesa/family16kb/model_16_init.c M src/cpu/amd/pi/00730F01/model_16_init.c 4 files changed, 8 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/56184/1 diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 942539c..1bcbc34 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -17,7 +17,7 @@ { u8 i; msr_t msr; - int num_banks; + unsigned int num_banks; int msrno; #if CONFIG(LOGICAL_CPUS) u32 siblings; @@ -59,8 +59,7 @@ x86_enable_cache(); /* zero the machine check error status registers */ - msr = rdmsr(IA32_MCG_CAP); - num_banks = msr.lo & MCA_BANKS_MASK; + num_banks = mca_get_bank_count(); msr.lo = 0; msr.hi = 0; for (i = 0; i < num_banks; i++) diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index 83efb44..c7fcb36 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -20,7 +20,7 @@ u8 i; msr_t msr; - int num_banks; + unsigned int num_banks; int msrno; unsigned int cpu_idx; #if CONFIG(LOGICAL_CPUS) @@ -58,8 +58,7 @@ x86_enable_cache(); /* zero the machine check error status registers */ - msr = rdmsr(IA32_MCG_CAP); - num_banks = msr.lo & MCA_BANKS_MASK; + num_banks = mca_get_bank_count(); msr.lo = 0; msr.hi = 0; for (i = 0; i < num_banks; i++) diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c index c1c7577..28c3e78 100644 --- a/src/cpu/amd/agesa/family16kb/model_16_init.c +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -19,7 +19,7 @@ u8 i; msr_t msr; - int num_banks; + unsigned int num_banks; int msrno; #if CONFIG(LOGICAL_CPUS) u32 siblings; @@ -56,8 +56,7 @@ x86_enable_cache(); /* zero the machine check error status registers */ - msr = rdmsr(IA32_MCG_CAP); - num_banks = msr.lo & MCA_BANKS_MASK; + num_banks = mca_get_bank_count(); msr.lo = 0; msr.hi = 0; for (i = 0; i < num_banks; i++) diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index 358f83b..7266a2c 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -22,7 +22,7 @@ u8 i; msr_t msr; - int num_banks; + unsigned int num_banks; u32 siblings; /* @@ -41,8 +41,7 @@ x86_mtrr_check(); /* zero the machine check error status registers */ - msr = rdmsr(IA32_MCG_CAP); - num_banks = msr.lo & MCA_BANKS_MASK; + num_banks = mca_get_bank_count(); msr.lo = 0; msr.hi = 0; for (i = 0; i < num_banks; i++) -- To view, visit https://review.coreboot.org/c/coreboot/+/56184 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70ad423aab484cf4ec8f51b43624cd434647aad4 Gerrit-Change-Number: 56184 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: include/cpu/x86/msr: add mca_get_bank_count function
by Felix Held (Code Review) 09 Jul '21

09 Jul '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56183 ) Change subject: include/cpu/x86/msr: add mca_get_bank_count function ...................................................................... include/cpu/x86/msr: add mca_get_bank_count function In multiple locations within the coreboot tree the IA32_MCG_CAP MSR gets read and masked with MCA_BANKS_MASK to get the number of available MCA banks on the CPU, so add this to the common code to avoid duplication of code. Change-Id: Id118a900edbe1f67aabcd109d2654c167b6345ea Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/include/cpu/x86/msr.h 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/56183/1 diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index bc367d7..54d9059 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -155,6 +155,13 @@ #endif /* CONFIG_SOC_SETS_MSRS */ +/* get MCA bank count from MSR */ +static inline unsigned int mca_get_bank_count(void) +{ + msr_t msr = rdmsr(IA32_MCG_CAP); + return msr.lo & MCA_BANKS_MASK; +} + /* Helpers for interpreting MC[i]_STATUS */ static inline int mca_valid(msr_t msr) -- To view, visit https://review.coreboot.org/c/coreboot/+/56183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id118a900edbe1f67aabcd109d2654c167b6345ea Gerrit-Change-Number: 56183 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/haswell: Move MRC glue code into a subfolder
by Paul Menzel (Code Review) 09 Jul '21

09 Jul '21

Attention is currently required from: Nico Huber, Matt DeVillier, Angel Pons, Arthur Heymans, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55523 ) Change subject: nb/intel/haswell: Move MRC glue code into a subfolder ...................................................................... Patch Set 7: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/55523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3e26ec1c2d5ccce928083d7ce41445908df8cf3 Gerrit-Change-Number: 55523 Gerrit-PatchSet: 7 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 09 Jul 2021 21:09:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: supermicro/x11-lga1151-series: Remove SkipExtGfxScan = 1
by Nico Huber (Code Review) 09 Jul '21

09 Jul '21

Attention is currently required from: Angel Pons, Michael Niewöhner. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56071 ) Change subject: supermicro/x11-lga1151-series: Remove SkipExtGfxScan = 1 ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > Does just `PrimaryDisplay = Display_PEG` work with both an external GPU and the BMC VGA? Ah, got it. FSP only takes the `PrimaryDisplay` UPD into account if the "ExtGfxScan" is performed. Otherwise an internal `PrimaryDisplay` variable that is initialized to `IGD` takes precedence. (I've been asking Intel to document the interdependencies of UPDs for years, they'll never learn.) Too bad. What we could do is to try to optimize the case that IGD is disabled, i.e. a global `if (!is_dev_enabled(IGD)) SkipExtGfxScan = 1;`. Probably not worth any hassle, though. I agree to the `SkipExtGfxScan` change now. But it would be nice to move the `SkipExtGfxScan = 0` setting to the override tree that also enables the IGD. (Actually, I'd prefer the IGD to be always enabled or have a Kconfig for it. It's not board specific, hence doesn't belong in the devicetree.) -- To view, visit https://review.coreboot.org/c/coreboot/+/56071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41249112c65927b61ca5f791f8eb8c3f3d204fce Gerrit-Change-Number: 56071 Gerrit-PatchSet: 3 Gerrit-Owner: Jan Tatje <jan(a)jnt.io> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Fri, 09 Jul 2021 20:44:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jan Tatje <jan(a)jnt.io> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: include/cpu/x86/msr: fix MCG_CTL_P definition
by Raul Rangel (Code Review) 09 Jul '21

09 Jul '21

Attention is currently required from: Angel Pons, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56179 ) Change subject: include/cpu/x86/msr: fix MCG_CTL_P definition ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56179 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39a59083daa5c2db11a8074d5c4881bf55688f43 Gerrit-Change-Number: 56179 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 09 Jul 2021 20:43:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso,stoneyridge/mca: remove unneeded line break
by Raul Rangel (Code Review) 09 Jul '21

09 Jul '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56180 ) Change subject: soc/amd/picasso,stoneyridge/mca: remove unneeded line break ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib74ff1d585f8ef54960e6a1eafd5a280907f8675 Gerrit-Change-Number: 56180 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 09 Jul 2021 20:42:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso,stoneyridge/mca: remove unneeded line break
by Felix Held (Code Review) 09 Jul '21

09 Jul '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56180 ) Change subject: soc/amd/picasso,stoneyridge/mca: remove unneeded line break ...................................................................... soc/amd/picasso,stoneyridge/mca: remove unneeded line break Change-Id: Ib74ff1d585f8ef54960e6a1eafd5a280907f8675 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/mca.c M src/soc/amd/stoneyridge/mca.c 2 files changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/56180/1 diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index 2576f6e..12d4ccc 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -184,8 +184,7 @@ i, mci.cmask.hi, mci.cmask.lo); mci.bank = i; - if (CONFIG(ACPI_BERT) - && mca_valid(mci.sts)) + if (CONFIG(ACPI_BERT) && mca_valid(mci.sts)) build_bert_mca_error(&mci); } } diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index b1f955f..346cd6d 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -186,8 +186,7 @@ i, mci.cmask.hi, mci.cmask.lo); mci.bank = i; - if (CONFIG(ACPI_BERT) - && mca_valid(mci.sts)) + if (CONFIG(ACPI_BERT) && mca_valid(mci.sts)) build_bert_mca_error(&mci); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/56180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib74ff1d585f8ef54960e6a1eafd5a280907f8675 Gerrit-Change-Number: 56180 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: include/cpu/x86/msr: fix MCG_CTL_P definition
by Felix Held (Code Review) 09 Jul '21

09 Jul '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56179 ) Change subject: include/cpu/x86/msr: fix MCG_CTL_P definition ...................................................................... include/cpu/x86/msr: fix MCG_CTL_P definition MCG_CTL_P is bit 8 of the IA32_MCG_CAP MSR and not bit 3. Bits 0-7 of that MSR contain the number of MCA banks being present on the CPU. Change-Id: I39a59083daa5c2db11a8074d5c4881bf55688f43 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/include/cpu/x86/msr.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/56179/1 diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index bc367d7..f4a28e7 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -36,7 +36,7 @@ #define SMBASE_RO_MSR 0x98 #define IA32_SMM_MONITOR_VALID (1 << 0) #define IA32_MCG_CAP 0x179 -#define MCG_CTL_P (1 << 3) +#define MCG_CTL_P (1 << 8) #define MCA_BANKS_MASK 0xff #define IA32_PERF_STATUS 0x198 #define IA32_PERF_CTL 0x199 -- To view, visit https://review.coreboot.org/c/coreboot/+/56179 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39a59083daa5c2db11a8074d5c4881bf55688f43 Gerrit-Change-Number: 56179 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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coreboot-gerrit July 2021