coreboot-gerrit July 2021

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Change in coreboot[master]: vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2237_00
by Tim Wawrzynczak (Code Review) 10 Jul '21

10 Jul '21

Attention is currently required from: V Sowmya, Subrata Banik, Sridhar Siricilla, Ronak Kanabar, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55896 ) Change subject: vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2237_00 ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/55896/comment/26454a77_20c4c2ca PS3, Line 19: Cq-Depend:chrome-internal:3970327 Cq-Depend:chrome-internal:3925290 -- To view, visit https://review.coreboot.org/c/coreboot/+/55896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie291204a3fa0b9451c418c84bd40a17ef08a436c Gerrit-Change-Number: 55896 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 09 Jul 2021 22:22:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: ACPI CPPC support for AMD
by Julian Schroeder (Code Review) 09 Jul '21

09 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Julian Schroeder, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56188 to look at the new patch set (#2). Change subject: soc/amd/cezanne: ACPI CPPC support for AMD ...................................................................... soc/amd/cezanne: ACPI CPPC support for AMD This leverages the existing CPPC support and adds a cppc init for AMD/Cezanne. Signed-off-by: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Change-Id: I94172f40c7fa4b7b89237fd382448e598da00fbb --- M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/cezanne/acpi.c A src/soc/amd/cezanne/cppc.c A src/soc/amd/cezanne/cppc.h A src/soc/amd/cezanne/cppc_init.c 5 files changed, 225 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/56188/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94172f40c7fa4b7b89237fd382448e598da00fbb Gerrit-Change-Number: 56188 Gerrit-PatchSet: 2 Gerrit-Owner: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Add (and fix) devices in IRQ table
by Furquan Shaikh (Code Review) 09 Jul '21

09 Jul '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56175 ) Change subject: soc/intel/alderlake: Add (and fix) devices in IRQ table ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/56175/comment/b9fe3f61_c3a8d468 PS2, Line 51: FIXED_INT_PIRQ > EDS and both say INT_LINE is RW for IGD and IPU (and indeed, they appear programmable from lspci's reporting), but empirically, S0ix fails if they are not set to 16 (their pin is RO set to PCI_INT_A). Could it be some bad assumption in FSP? > The CPU_6 slot is just more PCIe RPs, so are programmed the same as the the PCH side (according to their `function number % 4`) That makes sense. I was curious mostly about the non-PCIE RP devices as to how the decision was made: IGD, IPU -> Fixed int and pirq UART0, UART1, Tracehub -> Fixed int -- To view, visit https://review.coreboot.org/c/coreboot/+/56175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7612ee008842ba2b8dcd36deb201f4f26130660 Gerrit-Change-Number: 56175 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 09 Jul 2021 21:34:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: ACPI CPPC support for AMD
by build bot (Jenkins) (Code Review) 09 Jul '21

09 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56188 ) Change subject: soc/amd/cezanne: ACPI CPPC support for AMD ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/cezanne/cppc_init.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123758): https://review.coreboot.org/c/coreboot/+/56188/comment/58eae095_9b78edee PS1, Line 18: .access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS, //4 trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/56188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94172f40c7fa4b7b89237fd382448e598da00fbb Gerrit-Change-Number: 56188 Gerrit-PatchSet: 1 Gerrit-Owner: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 09 Jul 2021 21:30:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: ACPI CPPC support for AMD
by Julian Schroeder (Code Review) 09 Jul '21

09 Jul '21

Julian Schroeder has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56188 ) Change subject: soc/amd/cezanne: ACPI CPPC support for AMD ...................................................................... soc/amd/cezanne: ACPI CPPC support for AMD This leverages the existing CPPC support and adds a cppc init for AMD/Cezanne. Signed-off-by: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Change-Id: I94172f40c7fa4b7b89237fd382448e598da00fbb --- M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/cezanne/acpi.c A src/soc/amd/cezanne/cppc.c A src/soc/amd/cezanne/cppc.h A src/soc/amd/cezanne/cppc_init.c 5 files changed, 223 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/56188/1 diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index fa38cc3..022f7cc 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -32,6 +32,9 @@ ramstage-y += i2c.c ramstage-y += acpi.c +ramstage-y += cppc_init.c +ramstage-y += cppc.c + ramstage-y += agesa_acpi.c ramstage-y += chip.c ramstage-y += cpu.c diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index 6e2ae9c..a130e1d 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -19,6 +19,7 @@ #include <soc/msr.h> #include <types.h> #include "chip.h" +#include "cppc.h" unsigned long acpi_fill_madt(unsigned long current) { @@ -358,6 +359,8 @@ acpigen_write_CSD_package(cpu / threads_per_core, threads_per_core, CSD_HW_ALL, 0); + generate_cppc_entries(cpu); + acpigen_pop_len(); } diff --git a/src/soc/amd/cezanne/cppc.c b/src/soc/amd/cezanne/cppc.c new file mode 100644 index 0000000..df2b6df --- /dev/null +++ b/src/soc/amd/cezanne/cppc.c @@ -0,0 +1,17 @@ +#include <acpi/acpi_pm.h> +#include <acpi/acpigen.h> +#include <arch/cpu.h> +#include "cppc.h" + +void generate_cppc_entries(int core_id) +{ + /* Generate GCPC package in first logical core */ + if (core_id == 0) { + struct cppc_config cppc_config; + cpu_init_cppc_config(&cppc_config, CPPC_VERSION_3); + acpigen_write_CPPC_package(&cppc_config); + } + + /* Write _CPC entry for each logical core */ + acpigen_write_CPPC_method(); +} diff --git a/src/soc/amd/cezanne/cppc.h b/src/soc/amd/cezanne/cppc.h new file mode 100644 index 0000000..43e6fda --- /dev/null +++ b/src/soc/amd/cezanne/cppc.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _CPU_AMD_COMMON_H +#define _CPU_AMD_COMMON_H + +#include <types.h> + +struct cppc_config; +void cpu_init_cppc_config(struct cppc_config *config, u32 version); +void generate_cppc_entries(int core_id); + +#endif diff --git a/src/soc/amd/cezanne/cppc_init.c b/src/soc/amd/cezanne/cppc_init.c new file mode 100644 index 0000000..53aa12f --- /dev/null +++ b/src/soc/amd/cezanne/cppc_init.c @@ -0,0 +1,188 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpigen.h> +#include <cpu/x86/msr.h> +#include "cppc.h" + +/* + * version 2 is expected to be the typical use case. + * For now this function 'punts' on version 3 and just + * populates the additional fields with 'unsupported'. + */ +void cpu_init_cppc_config(struct cppc_config *config, u32 version) +{ + acpi_addr_t msr = { + .space_id = ACPI_ADDRESS_SPACE_FIXED, + .bit_width = 8, + .bit_offset = 0, + .access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS, //4 + .addrl = 0, + .addrh = 0, + }; + static const acpi_addr_t unsupported = { + .space_id = ACPI_ADDRESS_SPACE_MEMORY, + .bit_width = 0, + .bit_offset = 0, + .access_size = ACPI_ACCESS_SIZE_UNDEFINED, + .addrl = 0, + .addrh = 0, + }; + + config->version = version; + + msr.addrl = 0xc00102b0; + msr.bit_offset = 24; + + /* + * Highest Performance: + * ResourceTemplate(){Register(FFixedHW, 0x08, 0x00, 0x771, 0x04,)}, + */ + config->regs[CPPC_HIGHEST_PERF] = msr; + + /* + * Lowest Nonlinear Performance -> Most Efficient Performance: + * ResourceTemplate(){Register(FFixedHW, 0x08, 0x10, 0x771, 0x04,)}, + */ + msr.bit_offset = 8; + config->regs[CPPC_LOWEST_NONL_PERF] = msr; + + /* + * Lowest Performance: + * ResourceTemplate(){Register(FFixedHW, 0x08, 0x18, 0x771, 0x04,)}, + */ + msr.bit_offset = 0; + config->regs[CPPC_LOWEST_PERF] = msr; + + /* + * Guaranteed Performance Register: + * ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0x771, 0x04,)}, + */ + config->regs[CPPC_GUARANTEED_PERF] = unsupported; + + + /* + * Nominal Performance -> Maximum Non-Turbo Ratio: + * ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0xce, 0x04,)}, + */ + msr.addrl = 0xc00102b0; + msr.bit_offset = 16; + config->regs[CPPC_NOMINAL_PERF] = msr; + + + /* + * Desired Performance Register: + * ResourceTemplate(){Register(FFixedHW, 0x08, 0x10, 0x774, 0x04,)}, + */ + msr.addrl = 0xc00102b3; + msr.bit_offset = 16; + config->regs[CPPC_DESIRED_PERF] = msr; + + /* + * Minimum Performance Register: + * ResourceTemplate(){Register(FFixedHW, 0x08, 0x00, 0x774, 0x04,)}, + */ + msr.bit_offset = 8; + config->regs[CPPC_MIN_PERF] = msr; + + /* + * Maximum Performance Register: + * ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0x774, 0x04,)}, + */ + msr.bit_offset = 0; + config->regs[CPPC_MAX_PERF] = msr; + + /* + * Performance Reduction Tolerance Register: + * ResourceTemplate(){Register(SystemMemory, 0x00, 0x00, 0x0,,)}, + */ + config->regs[CPPC_PERF_REDUCE_TOLERANCE] = unsupported; + + /* + * Time Window Register: + * ResourceTemplate(){Register(SystemMemory, 0x00, 0x00, 0x0,,)}, + */ + config->regs[CPPC_TIME_WINDOW] = unsupported; + + /* + * Counter Wraparound Time: + * ResourceTemplate(){Register(SystemMemory, 0x00, 0x00, 0x0,,)}, + */ + config->regs[CPPC_COUNTER_WRAP] = unsupported; + + /* + * Reference Performance Counter Register: + * ResourceTemplate(){Register(FFixedHW, 0x40, 0x00, 0x0E7, 0x04,)}, + */ + msr.addrl = 0xe7; + msr.bit_width = 64; + msr.bit_offset = 0; + config->regs[CPPC_REF_PERF_COUNTER] = msr; + + + /* + * Delivered Performance Counter Register: + * ResourceTemplate(){Register(FFixedHW, 0x40, 0x00, 0x0E8, 0x04,)}, + */ + msr.addrl = 0xe8; + config->regs[CPPC_DELIVERED_PERF_COUNTER] = msr; + + + /* + * Performance Limited Register: + * ResourceTemplate(){Register(FFixedHW, 0x01, 0x02, 0x777, 0x04,)}, + */ + msr.bit_width = 1; + msr.addrl = 0xc00102b4; + msr.bit_offset = 1; + config->regs[CPPC_PERF_LIMITED] = msr; + + + /* + * CPPC Enable Register: + * ResourceTemplate(){Register(FFixedHW, 0x01, 0x00, 0x770, 0x04,)}, + */ + msr.addrl = 0xc00102b1; + msr.bit_offset = 0; + config->regs[CPPC_ENABLE] = msr; + + if (version >= 2) { + /* Autonomous Selection Enable is populated below */ + + /* + * Autonomous Activity Window Register + * ResourceTemplate(){Register(FFixedHW, 0x0a, 0x20, 0x774, 0x04,)}, + */ + config->regs[CPPC_AUTO_ACTIVITY_WINDOW] = unsupported; + + /* + * Autonomous Energy Performance Preference Register + * ResourceTemplate(){Register(FFixedHW, 0x08, 0x18, 0x774, 0x04,)}, + */ + msr.addrl = 0xc00102b1; + msr.bit_width = 8; + msr.bit_offset = 24; + config->regs[CPPC_PERF_PREF] = msr; + + /* Reference Performance */ + config->regs[CPPC_REF_PERF] = unsupported; + + if (version >= 3) { + /* Lowest Frequency */ + config->regs[CPPC_LOWEST_FREQ] = unsupported; + /* Nominal Frequency */ + config->regs[CPPC_NOMINAL_FREQ] = unsupported; + } + + /* + * Autonomous Selection Enable = 1 + * This field is actually the first addition in version 2 but + * it's so unlike the others I'm populating it last. + */ + msr.space_id = ACPI_ADDRESS_SPACE_MEMORY; + msr.bit_width = 32; + msr.bit_offset = 0; + msr.access_size = ACPI_ACCESS_SIZE_UNDEFINED; + msr.addrl = 1; + config->regs[CPPC_AUTO_SELECT] = unsupported; + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/56188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94172f40c7fa4b7b89237fd382448e598da00fbb Gerrit-Change-Number: 56188 Gerrit-PatchSet: 1 Gerrit-Owner: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: supermicro/x11-lga1151-series: Remove SkipExtGfxScan = 1
by Jan Tatje (Code Review) 09 Jul '21

09 Jul '21

Attention is currently required from: Nico Huber, Angel Pons, Michael Niewöhner. Jan Tatje has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56071 ) Change subject: supermicro/x11-lga1151-series: Remove SkipExtGfxScan = 1 ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > Ah, got it. FSP only takes the `PrimaryDisplay` UPD into account if the […] When I set `SkipExtGfxScan = 0` my PCIe SAS controller card doesn't show up. I did not have that card in earlier, so I did not notice until now. At first I thought it was just coincidence, but I tried multiple times turning `SkipExtGfxScan` on and off, so `SkipExtGfxScan = 0` seems to somehow break PCIe. -- To view, visit https://review.coreboot.org/c/coreboot/+/56071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41249112c65927b61ca5f791f8eb8c3f3d204fce Gerrit-Change-Number: 56071 Gerrit-PatchSet: 3 Gerrit-Owner: Jan Tatje <jan(a)jnt.io> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Fri, 09 Jul 2021 21:28:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Jan Tatje <jan(a)jnt.io> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/irq: Account for single-function devices
by Furquan Shaikh (Code Review) 09 Jul '21

09 Jul '21

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56173 ) Change subject: soc/intel/common/irq: Account for single-function devices ...................................................................... Patch Set 1: (2 comments) Patchset: PS1: > Correct, just PCI_INT_A Ack. File src/soc/intel/common/block/irq/irq.c: https://review.coreboot.org/c/coreboot/+/56173/comment/fc28af5c_17658664 PS1, Line 266: /* Single-function devices must use PIRQ_A */ > haha, looks like I misread my own notes (double checked in the BWG, it is INTA, not PIRQ_A). […] Makes sense. Yeah, INTA requirement should already be satisfied. -- To view, visit https://review.coreboot.org/c/coreboot/+/56173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3b0347c8a2c14413094adf1f9fca380525fb1c8 Gerrit-Change-Number: 56173 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Fri, 09 Jul 2021 21:25:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/*/Makefile.inc: Do some cosmetics
by Felix Held (Code Review) 09 Jul '21

09 Jul '21

Attention is currently required from: Jason Glenesk, Martin Roth, Marshall Dawson, Arthur Heymans. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56117 ) Change subject: soc/amd/*/Makefile.inc: Do some cosmetics ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > > I'm not sure this makes things more understandable, but I don't have any outright objection to it. […] i'm ok with either way. having the full $(obj)/coreboot.pre makes it a bit more obvious what it'll do though without knowing all makefile magic too well. haven't looked how it's done elsewhere in the tree though, so i really don't have much of an opinion on this one -- To view, visit https://review.coreboot.org/c/coreboot/+/56117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea2322ca1abd43900f3631b7965f07fed4235ca0 Gerrit-Change-Number: 56117 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 09 Jul 2021 21:22:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/acpi: Change GPIO controller interrupt to shared
by Felix Held (Code Review) 09 Jul '21

09 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56177 ) Change subject: soc/amd/cezanne/acpi: Change GPIO controller interrupt to shared ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56177 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I48c6d548a2a8d67599f25e37eeafc90764d9e2d2 Gerrit-Change-Number: 56177 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Fri, 09 Jul 2021 21:17:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: security/intel/txt: use mca_get_bank_count()
by Felix Held (Code Review) 09 Jul '21

09 Jul '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56187 ) Change subject: security/intel/txt: use mca_get_bank_count() ...................................................................... security/intel/txt: use mca_get_bank_count() Use the common mca_get_bank_count function instead of open-coding the functionality to get the MCA bank number. Change-Id: I28244c975ee34d36d0b44df092d4a62a01c3c79c Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/security/intel/txt/common.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/56187/1 diff --git a/src/security/intel/txt/common.c b/src/security/intel/txt/common.c index 239e152..011e8cc 100644 --- a/src/security/intel/txt/common.c +++ b/src/security/intel/txt/common.c @@ -481,8 +481,7 @@ * Make sure there are no uncorrectable MCE errors. * Intel 64 and IA-32 Architectures Software Developer Manuals Vol 2D */ - msr = rdmsr(IA32_MCG_CAP); - size_t max_mc_msr = msr.lo & MCA_BANKS_MASK; + size_t max_mc_msr = mca_get_bank_count(); for (size_t i = 0; i < max_mc_msr; i++) { msr = rdmsr(IA32_MC0_STATUS + 4 * i); if (!(msr.hi & MCA_STATUS_HI_UC)) -- To view, visit https://review.coreboot.org/c/coreboot/+/56187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28244c975ee34d36d0b44df092d4a62a01c3c79c Gerrit-Change-Number: 56187 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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coreboot-gerrit July 2021