Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56564 )
Change subject: mb/siemens/mc_ehl1: Enable In Band ECC
......................................................................
mb/siemens/mc_ehl1: Enable In Band ECC
Enable IBECC for mc_ehl1 to provide a memory failure protection.
Change-Id: If8f81d6bacb77dc38e231c1cedf22831de8a38a9
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56564
Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
1 file changed, 6 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Mario Scheithauer: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
index 34a4ce5..1eece7a 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
@@ -20,6 +20,12 @@
register "SmbusEnable" = "1"
register "Heci2Enable" = "1"
+ # Enable IBECC for the complete memory
+ register "ibecc" = "{
+ .enable = 1,
+ .mode = IBECC_ALL
+ }"
+
# USB related UPDs
register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # USB3/2 Type A port 1
register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # USB3/2 Type A Port 2
--
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Gerrit-Change-Id: If8f81d6bacb77dc38e231c1cedf22831de8a38a9
Gerrit-Change-Number: 56564
Gerrit-PatchSet: 4
Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
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Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56563 )
Change subject: mb/siemens/mc_ehl1: Disable System Agent dynamic frequency support
......................................................................
mb/siemens/mc_ehl1: Disable System Agent dynamic frequency support
In favor of better realtime performance disable dynamic frequency
support in the System Agent for mc_ehl1.
Change-Id: I0e62bcf2e5efa97d89bf7192f1536747a02ad992
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56563
Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Mario Scheithauer: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
index 2f8df04..34a4ce5 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
@@ -16,7 +16,7 @@
register "HeciEnabled" = "1"
# FSP configuration
- register "SaGv" = "SaGv_Enabled"
+ register "SaGv" = "SaGv_Disabled"
register "SmbusEnable" = "1"
register "Heci2Enable" = "1"
--
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Gerrit-Change-Id: I0e62bcf2e5efa97d89bf7192f1536747a02ad992
Gerrit-Change-Number: 56563
Gerrit-PatchSet: 4
Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
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Gerrit-MessageType: merged
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56541 )
Change subject: mb/siemens/mc_ehl: Enable LPC TPM
......................................................................
mb/siemens/mc_ehl: Enable LPC TPM
All the boards based on the mc_ehl baseboard have a TPM which is
connected to SPI but mapped into the address space of the x86 so that
it acts like a LPC attached TPM. Enable the TPM driver so that it will
be used. In addition add the needed entry in devicetree.
Change-Id: I301d0ed4a108bac45d95eced120e7ba280945d9c
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56541
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/mainboard/siemens/mc_ehl/Kconfig
M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
2 files changed, 7 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Mario Scheithauer: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_ehl/Kconfig b/src/mainboard/siemens/mc_ehl/Kconfig
index 5c36c8f..926e668 100644
--- a/src/mainboard/siemens/mc_ehl/Kconfig
+++ b/src/mainboard/siemens/mc_ehl/Kconfig
@@ -6,6 +6,8 @@
select HAVE_SPD_IN_CBFS
select HAVE_ACPI_TABLES
select DRIVERS_I2C_RX6110SA
+ select MAINBOARD_HAS_TPM2
+ select MAINBOARD_HAS_LPC_TPM
source "src/mainboard/siemens/mc_ehl/variants/*/Kconfig"
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
index 03d10aa..2f8df04 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
@@ -214,7 +214,11 @@
device pci 1e.6 on end # HPET
device pci 1e.7 on end # IOAPIC
- device pci 1f.0 on end # eSPI Interface
+ device pci 1f.0 on # eSPI Interface
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
+ end
device pci 1f.1 on end # P2SB
device pci 1f.2 hidden end # Power Management Controller
device pci 1f.3 off end # Intel cAVS/HDA
--
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Gerrit-Change-Number: 56541
Gerrit-PatchSet: 4
Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com>
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Gerrit-MessageType: merged
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56523 )
Change subject: mb/siemens/mc_ehl: Add external RTC RX6110SA
......................................................................
mb/siemens/mc_ehl: Add external RTC RX6110SA
All the mainboards based on mc_ehl use the external RTC RX6110SA.
Enable the driver in Kconfig for all boards based on mc_ehl. In
addition, as mc_ehl1 has the RTC attached to the SMBus, add the
devicetree entry on behalf of the SMBus device 00:1f.4 for this variant.
Change-Id: Ie1f45d0e6f9063c00253fe58a6268d40de91cf63
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56523
Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/siemens/mc_ehl/Kconfig
M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
2 files changed, 17 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Mario Scheithauer: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_ehl/Kconfig b/src/mainboard/siemens/mc_ehl/Kconfig
index fb8dc03..5c36c8f 100644
--- a/src/mainboard/siemens/mc_ehl/Kconfig
+++ b/src/mainboard/siemens/mc_ehl/Kconfig
@@ -5,7 +5,7 @@
select DRIVERS_I2C_GENERIC
select HAVE_SPD_IN_CBFS
select HAVE_ACPI_TABLES
-
+ select DRIVERS_I2C_RX6110SA
source "src/mainboard/siemens/mc_ehl/variants/*/Kconfig"
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
index 950f501..03d10aa 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
@@ -218,7 +218,22 @@
device pci 1f.1 on end # P2SB
device pci 1f.2 hidden end # Power Management Controller
device pci 1f.3 off end # Intel cAVS/HDA
- device pci 1f.4 on end # SMBus
+ device pci 1f.4 on # SMBus
+ # Enable external RTC chip
+ chip drivers/i2c/rx6110sa
+ register "bus_speed" = "I2C_SPEED_STANDARD"
+ register "pmon_sampling" = "PMON_SAMPL_256_MS"
+ register "bks_on" = "0"
+ register "bks_off" = "1"
+ register "iocut_en" = "1"
+ register "set_user_date" = "1"
+ register "user_year" = "04"
+ register "user_month" = "07"
+ register "user_day" = "01"
+ register "user_weekday" = "4"
+ device i2c 0x32 on end # RTC RX6110 SA
+ end
+ end
device pci 1f.5 on end # PCH SPI (flash & TPM)
device pci 1f.7 off end # PCH Intel Trace Hub
end
--
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Gerrit-Change-Number: 56523
Gerrit-PatchSet: 5
Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
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Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56523 )
Change subject: mb/siemens/mc_ehl: Add external RTC RX6110SA
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56523/comment/136fa1a9_36295c7e
PS1, Line 12:
> Not sure if that is helpful here. […]
Ack
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Gerrit-Change-Number: 56523
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Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56571 )
Change subject: arch/x86/thread: Add #error when compiling for x86_64
......................................................................
arch/x86/thread: Add #error when compiling for x86_64
The x86 thread code is all x86_32 specific. It needs to be updated to
work with 64 bit. For now just throw an error when compiling.
BUG=b:179699789
TEST=none
Suggested-by: Furquan Shaikh <furquan(a)google.com>
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I96187ad84bdec40c6883748afa41e217bc389b79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56571
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Julius Werner <jwerner(a)chromium.org>
---
M src/arch/x86/thread.c
M src/arch/x86/thread_switch.S
2 files changed, 8 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Julius Werner: Looks good to me, approved
diff --git a/src/arch/x86/thread.c b/src/arch/x86/thread.c
index a9fda66..fa60961 100644
--- a/src/arch/x86/thread.c
+++ b/src/arch/x86/thread.c
@@ -2,6 +2,10 @@
#include <thread.h>
+#if ENV_X86_64
+#error COOP_MULTITASKING does not currently support x86_64
+#endif
+
/* The stack frame looks like the following after a pushad instruction. */
struct pushad_regs {
uint32_t edi; /* Offset 0x00 */
diff --git a/src/arch/x86/thread_switch.S b/src/arch/x86/thread_switch.S
index 049f0927..3c6a34d 100644
--- a/src/arch/x86/thread_switch.S
+++ b/src/arch/x86/thread_switch.S
@@ -1,5 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#if ENV_X86_64
+#error COOP_MULTITASKING does not currently support x86_64
+#endif
+
.code32
.text
--
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Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org>
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Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56626 )
Change subject: mb/google/dedede/var/storo: Set the xHCI LFPS period sampling off time to 0ms
......................................................................
mb/google/dedede/var/storo: Set the xHCI LFPS period sampling off time to 0ms
LTE module L850-GL may encounter U3 wakeup race condition with the host.
Setting xHCI LFPS periodic sampling off time to 0ms so that the host would not
miss the device-initiated U3 wakeup thus avoid the race condition.
BUG=b:193898133
BRANCH=dedede
TEST=flash the image to the device. Run following command to check the bits[7:4] is 0x0:
iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com>
Change-Id: Ic84dc83b749cf3c6029a06730096b64ef8cb8cd9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56626
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com>
---
M src/mainboard/google/dedede/variants/storo/overridetree.cb
1 file changed, 2 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Karthik Ramasubramanian: Looks good to me, approved
diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb
index e824652..aedb285 100644
--- a/src/mainboard/google/dedede/variants/storo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb
@@ -79,6 +79,8 @@
register "tcc_offset" = "10" # TCC of 95C
+ register "xhci_lfps_sampling_offtime_ms" = "0"
+
device domain 0 on
device pci 04.0 on
chip drivers/intel/dptf
--
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