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Change subject: soc/intel/jasperlake: select CPU_SUPPORTS_CORE_RECOVERY for Jasper Lake
......................................................................
soc/intel/jasperlake: select CPU_SUPPORTS_CORE_RECOVERY for Jasper Lake
Jasper Lake supports core recovery mechanism. This patch enables the
required support for core recovery,
BUG=None
BRANCH=None
TEST=check number of cores in `lscpu` output and it matches with
actual number on SoC.
Change-Id: I639ad518d135000c802389c670f3348ba281022e
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com>
---
M src/soc/intel/jasperlake/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/56696/1
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index fa26a54..87d0228 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -13,6 +13,7 @@
select CACHE_MRC_SETTINGS
select CPU_INTEL_COMMON
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
+ select CPU_SUPPORTS_CORE_RECOVERY
select CPU_SUPPORTS_PM_TIMER_EMULATION
select COS_MAPPED_TO_MSB
select FSP_COMPRESS_FSP_S_LZ4
--
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Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56695 )
Change subject: soc/intel/common/block/cpu: Add core recovery feature support
......................................................................
soc/intel/common/block/cpu: Add core recovery feature support
Core recovery is a new mechanism that allows the CPU core configuration.
The new mechanism doesn't guarantee the bootstrap processor (BSP) LAPIC
ID always starts from 0.
Currently coreboot assumes that BSP always has LAPIC ID 0. Hence, the
non-presence CPU core with LAPIC ID 0 will be added into the CPU topology
along with the other valid CPU cores during coreboot initialization.
Finally, at Linux kernel, the non-presence core will fail at initialization
and be set as an offline CPU.
BUG=None
BRANCH=None
TEST=check the number of cores in `lscpu` is matching as per the maximum
core available in SoC.
Change-Id: Ied00d2c3d960c8714c0d18a6b65dfd371915b2ff
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com>
---
M src/soc/intel/common/block/cpu/Kconfig
M src/soc/intel/common/block/cpu/mp_init.c
2 files changed, 33 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/56695/1
diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig
index 16844d9..fb443f6 100644
--- a/src/soc/intel/common/block/cpu/Kconfig
+++ b/src/soc/intel/common/block/cpu/Kconfig
@@ -113,3 +113,20 @@
help
Select this on platforms that do not support Bootguard related MSRs
0x139, MSR_BC_PBEC and 0x13A, MSR_BOOT_GUARD_SACM_INFO.
+
+config CPU_SUPPORTS_CORE_RECOVERY
+ bool
+ default n
+ help
+ Core recovery is a new mechanism that allows the CPU core configuration.
+ The new mechanism doesn't guarantee the bootstrap processor (BSP) LAPIC
+ ID always starts from 0.
+
+ Currently coreboot assumes that BSP always has LAPIC ID 0. Hence, the
+ non-presence CPU core with LAPIC ID 0 will be added into the CPU topology
+ along with the other valid CPU cores during coreboot initialization.
+ Finally, at Linux kernel, the non-presence core will fail at initialization
+ and be set as an offline CPU.
+
+ SoC Kconfig to select this option when the platform supports Core recovery so
+ that it can override the non-existed LAPIC ID 0 with valid BSP LAPIC ID.
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index c31a6f7..77df4e4 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -150,6 +150,22 @@
x86_mtrr_check();
}
+static void do_core_recovery(void *unused)
+{
+ if(!CONFIG(CPU_SUPPORTS_CORE_RECOVERY))
+ return;
+
+ struct device *dev = dev_find_path(NULL, DEVICE_PATH_APIC);
+ assert(dev != NULL);
+
+ uint32_t bsp_apic_id = lapicid();
+
+ if(dev->path.apic.apic_id != bsp_apic_id)
+ dev->path.apic.apic_id = bsp_apic_id;
+}
+
+/* Enable core recovery */
+BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, do_core_recovery, NULL);
/* Do CPU MP Init before FSP Silicon Init */
BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, coreboot_init_cpus, NULL);
BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_EXIT, post_cpus_init, NULL);
--
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Change subject: mb/google/kukui: Add new config 'pico' in coreboot
......................................................................
Patch Set 2: Code-Review+2
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Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56450 )
Change subject: soc/amd/picasso: Move IVRS generation code to common
......................................................................
Patch Set 2:
(3 comments)
Patchset:
PS1:
> I'd introduce the Kconfig option SOC_AMD_COMMON_BLOCK_ACPI_IVRS here and only select that in picasso […]
done
File src/include/acpi/acpi.h:
https://review.coreboot.org/c/coreboot/+/56450/comment/f9615aa4_cd0d779e
PS1, Line 1202: acpi_populate_ivrs
> acpi_fill_ivrs would be more consistent with the existing functions here
Done
File src/soc/amd/common/block/acpi/ivrs.c:
https://review.coreboot.org/c/coreboot/+/56450/comment/01fbcb6f_c578273f
PS1, Line 356: /* BDF <bus>:00.2 */
: ivrs->ivhd.device_id = 0x02 | (nb_dev->bus->secondary << 8);
: ivrs->ivhd.capability_offset = pci_find_capability(iommu_dev, IOMMU_CAP_ID);
: ivrs->ivhd.iommu_base_low = pci_read_config32(iommu_dev, 0x44) & 0xffffc000;
: ivrs->ivhd.iommu_base_high = pci_read_config32(iommu_dev, 0x48);
> It could be in a follow-on, but something like this could potentially change across generations of A […]
Agree
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Matt Papageorge, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56450
to look at the new patch set (#2).
Change subject: soc/amd/picasso: Move IVRS generation code to common
......................................................................
soc/amd/picasso: Move IVRS generation code to common
Move IVRS acpi table generation code to common, so that it can be shared
by other programs.
BUG=b:190515051
TEST=Build picasso coreboot image. Compare IVRS tables before/after
change.
Change-Id: Icd5fec3a9d66e8301e267312020e726d9bc1aa70
Signed-off-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com>
---
M src/soc/amd/common/block/acpi/Makefile.inc
A src/soc/amd/common/block/acpi/ivrs.c
M src/soc/amd/common/block/include/amdblocks/acpi.h
M src/soc/amd/picasso/Kconfig
M src/soc/amd/picasso/agesa_acpi.c
5 files changed, 472 insertions(+), 450 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/56450/2
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Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51130 )
Change subject: util/inteltool: Add support for GLK
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
Without a case in gpio.c, it just ends up at the default "is not (yet)" supported.
With that added it, with N5000 and N5030, it seems to segfault at:
```
0x09b0: 0x0002276544000402 PNL1
```
I'll try and backtrace it when I get a chance.
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56684 )
Change subject: soc/amd/cezanne/early_fch: Perform early SPI initialization
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
duplicate of CB:52907 that still has some open TODOs
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Change subject: tests: Add lib/cbfs-verification-test test case
......................................................................
Patch Set 2:
(5 comments)
File tests/lib/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/56601/comment/bb687adb_457cfbbc
PS2, Line 198: CONFIG_CBFS_VERIFICATION=1 \
> It would be great if you could build this test twice, once with CONFIG_CBFS_VERIFICATION=1 and once […]
Makes sense
File tests/lib/cbfs-verification-test.c:
https://review.coreboot.org/c/coreboot/+/56601/comment/a739f798_8af8ae7a
PS2, Line 4: #define __noreturn
> What's this? __noreturn comes from src/commonlib/bsd/include/commonlib/bsd/compiler. […]
This is here to block `__noreturn` effect on `die()` function, which falls `failed()` to signal an error in the code. Original `die()` has the `__noreturn` attribute, which can be pretty tricky to deal with if one wants to check if ode really fails using `expect_assert_failure()`.
And, I see, what I did wrong in the `die()` implementation. `fail()` cannot be catched, but `(mock_)assert()` can.
https://review.coreboot.org/c/coreboot/+/56601/comment/ca869a7f_ecc8f5d9
PS2, Line 38: #define HASH_ATTR_SIZE (sizeof(struct cbfs_file_attr_hash))
> Oh, this is the VB2_SUPPORT_SHA512 issue. Okay, yeah, this needs to be defined differently. […]
Looks good to me
https://review.coreboot.org/c/coreboot/+/56601/comment/169a0aff_44ba65b0
PS2, Line 121: {
> These should also use the check...() functions to make sure they're only called when intended. […]
`ulzman()` and `ulz4fn()` will be called only for files with compression enabled and when the `cbfs_cache` is available (so, when CONFIG_ARCH_X86=0). Moreover the `cbfs_file_attr_compression` attribute is required.
I think, that this test does not aim to check if attributes (compression attr included) are correctly interpreted. In my opinion `fail()` is sufficient here. Compression will be tested in the `cbfs-lookup-test` (or similar name), which I am currently working on.
https://review.coreboot.org/c/coreboot/+/56601/comment/da7b643c_e91ba390
PS2, Line 167: assert_null(mapping);
> I guess with the way the objcopy weaking mocks work now, you can't both mock a function and still call the underlying to make a little wrapper that checks arguments?
It is not possible. Weak symbol is dropped during linking. I tried swapping symbols using --redefine-sym, but it was not giving correct results.
> Maybe using --add-symbol to define a (non-weak) __real_<functionname> symbol for the same address as each <functionname> that's marked as mockable?
The problem with --add-symbol is, we have to know, what address of <functionname> is. To do this, we have to scan all produced object files to find the exact file and address of that symbol.
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56693 )
Change subject: soc/amd/common/block/include/gpio_banks: use gpio_t for gpio numbers
......................................................................
soc/amd/common/block/include/gpio_banks: use gpio_t for gpio numbers
With the addition of the remote GPIO support, the GPIO number won't fit
into 8 bit any more, so use the gpio_t type instead which is an uint32_t
typedef.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I3de93fd3a2f2af3c1e3b335fef84019c56482051
---
M src/soc/amd/common/block/gpio_banks/gpio.c
M src/soc/amd/common/block/include/amdblocks/gpio_banks.h
2 files changed, 6 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/56693/1
diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c
index 85f2736..108635a 100644
--- a/src/soc/amd/common/block/gpio_banks/gpio.c
+++ b/src/soc/amd/common/block/gpio_banks/gpio.c
@@ -15,7 +15,7 @@
#include <assert.h>
#include <string.h>
-static int get_gpio_gevent(uint8_t gpio, const struct soc_amd_event *table,
+static int get_gpio_gevent(gpio_t gpio, const struct soc_amd_event *table,
size_t items)
{
int i;
diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h
index 098208b..d17aa7a 100644
--- a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h
+++ b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h
@@ -6,15 +6,17 @@
#include <types.h>
#include "gpio_defs.h"
+typedef uint32_t gpio_t;
+
struct soc_amd_gpio {
- uint8_t gpio;
+ gpio_t gpio;
uint8_t function;
uint32_t control;
uint32_t flags;
};
struct soc_amd_event {
- uint8_t gpio;
+ gpio_t gpio;
uint8_t event;
};
@@ -24,7 +26,7 @@
/* Number of wake_gpio with a valid setting. */
uint32_t num_valid_wake_gpios;
/* GPIO index number that caused a wake. */
- uint8_t wake_gpios[16];
+ gpio_t wake_gpios[16];
};
/* Fill gpio_wake_state object for future event reporting. */
@@ -52,8 +54,6 @@
return (flags & GPIO_FLAG_EVENT_ACTIVE_MASK) == GPIO_FLAG_EVENT_ACTIVE_LOW;
}
-typedef uint32_t gpio_t;
-
/*
* gpio_configure_pads_with_override accepts as input two GPIO tables:
* 1. Base config
--
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