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Change subject: soc/amd/common/block/spi: Enable host burst to 4 DWORD when using DMA
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56683/comment/272e87a5_d9c4dcb3
PS1, Line 9: Early SPI initialization disables 4 DWORD burst.
> Why does it need to be disabled at all?
IIRC that thing is broken on stoneyridge and needs to be switched off there
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Change subject: soc/amd/common/block/spi: Enable host burst to 4 DWORD when using DMA
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/common/block/spi/fch_spi.c:
https://review.coreboot.org/c/coreboot/+/56683/comment/f0ef8105_6a776791
PS1, Line 64: if (!CONFIG(SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA))
Is this only being used in the case of using the SPI DMA? IIRC we needed to do the fch_spi_disable_4dw_burst call for stoneyridge due to some silicon bug. If there are some other cases where keeping the 4DW bursts enabled when not using the SPI DMA would be useful, it's probably better to have an additional kconfig option like SOC_AMD_COMMON_BLOCK_LPC_SPI_4DW_BURST which gets selected by SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA.
I don't think that printing a debug message would be useful here; only thing it would do is adding some boot time
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Change subject: soc/intel/common/block/cpu: Add core recovery feature support
......................................................................
soc/intel/common/block/cpu: Add core recovery feature support
Core recovery is a new mechanism that allows the CPU core configuration.
The new mechanism doesn't guarantee the bootstrap processor (BSP) LAPIC
ID always starts from 0.
Currently coreboot assumes that BSP always has LAPIC ID 0. Hence, the
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Change-Id: Ied00d2c3d960c8714c0d18a6b65dfd371915b2ff
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---
M src/soc/intel/common/block/cpu/Kconfig
M src/soc/intel/common/block/cpu/mp_init.c
2 files changed, 33 insertions(+), 0 deletions(-)
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Change subject: soc/intel/common/block/cpu: Add core recovery feature support
......................................................................
soc/intel/common/block/cpu: Add core recovery feature support
Core recovery is a new mechanism that allows the CPU core configuration.
The new mechanism doesn't guarantee the bootstrap processor (BSP) LAPIC
ID always starts from 0.
Currently coreboot assumes that BSP always has LAPIC ID 0. Hence, the
non-presence CPU core with LAPIC ID 0 will be added into the CPU topology
along with the other valid CPU cores during coreboot initialization.
Finally, at Linux kernel, the non-presence core will fail at initialization
and be set as an offline CPU.
BUG=None
BRANCH=None
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core available in SoC.
Change-Id: Ied00d2c3d960c8714c0d18a6b65dfd371915b2ff
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---
M src/soc/intel/common/block/cpu/Kconfig
M src/soc/intel/common/block/cpu/mp_init.c
2 files changed, 33 insertions(+), 0 deletions(-)
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Change subject: soc/intel/common/block/cpu: Add core recovery feature support
......................................................................
soc/intel/common/block/cpu: Add core recovery feature support
Core recovery is a new mechanism that allows the CPU core configuration.
The new mechanism doesn't guarantee the bootstrap processor (BSP) LAPIC
ID always starts from 0.
Currently coreboot assumes that BSP always has LAPIC ID 0. Hence, the
non-presence CPU core with LAPIC ID 0 will be added into the CPU
topology along with the other valid CPU cores during coreboot
initialization.
Finally, at Linux kernel, the non-presence core will fail at
initialization and be set as an offline CPU.
BUG=None
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core available in SoC.
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---
M src/soc/intel/common/block/cpu/Kconfig
M src/soc/intel/common/block/cpu/mp_init.c
2 files changed, 33 insertions(+), 0 deletions(-)
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Change subject: soc/intel/common/block/cpu: Add core recovery feature support
......................................................................
soc/intel/common/block/cpu: Add core recovery feature support
Core recovery is a new mechanism that allows the CPU core configuration.
The new mechanism doesn't guarantee the bootstrap processor (BSP) LAPIC
ID always starts from 0.
Currently coreboot assumes that BSP always has LAPIC ID 0. Hence, the
non-presence CPU core with LAPIC ID 0 will be added into the CPU topology
along with the other valid CPU cores during coreboot initialization.
Finally, at Linux kernel, the non-presence core will fail at initialization
and be set as an offline CPU.
BUG=None
BRANCH=None
TEST=check the number of cores in `lscpu` is matching as per the maximum
core available in SoC.
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---
M src/soc/intel/common/block/cpu/Kconfig
M src/soc/intel/common/block/cpu/mp_init.c
2 files changed, 33 insertions(+), 0 deletions(-)
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Change subject: soc/intel/common/block/cpu: Add core recovery feature support
......................................................................
soc/intel/common/block/cpu: Add core recovery feature support
Core recovery is a new mechanism that allows the CPU core configuration.
The new mechanism doesn't guarantee the bootstrap processor (BSP) LAPIC
ID always starts from 0.
Currently coreboot assumes that BSP always has LAPIC ID 0. Hence, the
non-presence CPU core with LAPIC ID 0 will be added into the CPU topology
along with the other valid CPU cores during coreboot initialization.
Finally, at Linux kernel, the non-presence core will fail at initialization
and be set as an offline CPU.
BUG=None
BRANCH=None
TEST=check the number of cores in `lscpu` is matching as per the maximum
core available in SoC.
Change-Id: Ied00d2c3d960c8714c0d18a6b65dfd371915b2ff
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com>
---
M src/soc/intel/common/block/cpu/Kconfig
M src/soc/intel/common/block/cpu/mp_init.c
2 files changed, 33 insertions(+), 0 deletions(-)
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Change subject: soc/intel/common/block/cpu: Add core recovery feature support
......................................................................
Patch Set 1:
(3 comments)
File src/soc/intel/common/block/cpu/mp_init.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-125441):
https://review.coreboot.org/c/coreboot/+/56695/comment/24fb2a74_031d9376
PS1, Line 155: if(!CONFIG(CPU_SUPPORTS_CORE_RECOVERY))
space required before the open parenthesis '('
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-125441):
https://review.coreboot.org/c/coreboot/+/56695/comment/3ba3d599_e5c34e12
PS1, Line 163: if(dev->path.apic.apic_id != bsp_apic_id)
space required before the open parenthesis '('
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-125441):
https://review.coreboot.org/c/coreboot/+/56695/comment/4855a94b_2a6bf479
PS1, Line 164: dev->path.apic.apic_id = bsp_apic_id;
code indent should use tabs where possible
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