Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56682 )
Change subject: vc/intel/fsp/fsp2_0/alderlake: Update MemInfoHob.h for new FSP
......................................................................
vc/intel/fsp/fsp2_0/alderlake: Update MemInfoHob.h for new FSP
Sync the MemInfoHob.h with current FSP code.
BUG=b:190339677
TEST=dmidecode -t 17 can show the memory information.
Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com>
Change-Id: I80d1252b1f12b164d4f6d3a01221507cdfbe4d08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56682
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subrata.banik(a)intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
---
M src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h
1 file changed, 17 insertions(+), 14 deletions(-)
Approvals:
build bot (Jenkins): Verified
Subrata Banik: Looks good to me, approved
Maulik V Vaghela: Looks good to me, approved
Amanda Hwang: Looks good to me, approved
diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h
index 3fad944..3722749 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h
@@ -132,27 +132,21 @@
//
// Matches MrcDdrType enum in MRC
//
-#ifndef MRC_DDR_TYPE_DDR4
-#define MRC_DDR_TYPE_DDR4 0
+#ifndef MRC_DDR_TYPE_DDR5
+#define MRC_DDR_TYPE_DDR5 1
#endif
-#ifndef MRC_DDR_TYPE_DDR3
-#define MRC_DDR_TYPE_DDR3 1
-#endif
-#ifndef MRC_DDR_TYPE_LPDDR3
-#define MRC_DDR_TYPE_LPDDR3 2
+#ifndef MRC_DDR_TYPE_LPDDR5
+#define MRC_DDR_TYPE_LPDDR5 2
#endif
#ifndef MRC_DDR_TYPE_LPDDR4
#define MRC_DDR_TYPE_LPDDR4 3
#endif
-#ifndef MRC_DDR_TYPE_WIO2
-#define MRC_DDR_TYPE_WIO2 4
-#endif
#ifndef MRC_DDR_TYPE_UNKNOWN
-#define MRC_DDR_TYPE_UNKNOWN 5
+#define MRC_DDR_TYPE_UNKNOWN 4
#endif
-#define MAX_PROFILE_NUM 4 // number of memory profiles supported
-#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
+#define MAX_PROFILE_NUM 7 // number of memory profiles supported
+#define MAX_XMP_PROFILE_NUM 5 // number of XMP profiles supported
#define MAX_TRACE_REGION 5
#define MAX_TRACE_CACHE_TYPE 2
@@ -262,9 +256,18 @@
SiMrcVersion Version;
BOOLEAN EccSupport;
UINT8 MemoryProfile;
+ UINT8 IsDMBRunning; ///< Memory Trained with Dynamic Memory Boost (DMB)
UINT32 TotalPhysicalMemorySize;
UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
- UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
+ ///
+ /// Set of bit flags showing XMP and User Profile capability status for the DIMMs detected in system. For each bit, 1 is supported, 0 is unsupported.
+ /// Bit 0: XMP Profile 1 capability status
+ /// Bit 1: XMP Profile 2 capability status
+ /// Bit 2: XMP Profile 3 capability status
+ /// Bit 3: User Profile 4 capability status
+ /// Bit 4: User Profile 5 capability status
+ ///
+ UINT8 XmpProfileEnable;
UINT8 XmpConfigWarning; ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed
UINT8 Ratio; ///< DDR Frequency Ratio, Max Value 255
UINT8 RefClk;
--
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56682 )
Change subject: vc/intel/fsp/fsp2_0/alderlake: Update MemInfoHob.h for new FSP
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
This is fixing a regression from FSP (unable to decode DRAM information), submitting early with 3 +2s.
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Change subject: mb/siemens/mc_ehl: Add code to wait for legacy devices before PCI scan
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Patch Set 3: Code-Review+1
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Change subject: mb/google/kukui: Add new config 'pico' in coreboot
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Patch Set 1:
(1 comment)
File src/mainboard/google/kukui/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/56691/comment/4bcdaab4_35304aa5
PS1, Line 84:
src/mainboard/google/kukui/Kconfig.name has multiple final newlines.
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Change subject: mb/siemens/mc_ehl: Add code to wait for legacy devices before PCI scan
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Change subject: util/kconfig: detect ncurses on FreeBSD
......................................................................
Patch Set 4:
(1 comment)
File util/kconfig/mconf-cfg.sh:
https://review.coreboot.org/c/coreboot/+/56677/comment/bab50341_5c8f9fd2
PS2, Line 40: fi
It looks like Linux upstream removed that in commit c0f975af17 (kconfig: Support building mconf with vendor sysroot ncurses) [1].
[1]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?…
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