Attention is currently required from: Martin Roth.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56677
to look at the new patch set (#4).
Change subject: util/kconfig: detect ncurses on FreeBSD
......................................................................
util/kconfig: detect ncurses on FreeBSD
Signed-off-by: Idwer Vollering <vidwer(a)gmail.com>
Change-Id: I4344ba2116c0b8618357db4248d993509cbb666e
---
M util/kconfig/mconf-cfg.sh
A util/kconfig/patches/0013-util-kconfig-detect-ncurses-on-FreeBSD.patch
M util/kconfig/patches/series
3 files changed, 38 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/56677/4
--
To view, visit https://review.coreboot.org/c/coreboot/+/56677
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I4344ba2116c0b8618357db4248d993509cbb666e
Gerrit-Change-Number: 56677
Gerrit-PatchSet: 4
Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Martin Roth <martinroth(a)google.com>
Gerrit-MessageType: newpatchset
Attention is currently required from: Martin Roth, Idwer Vollering.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56677
to look at the new patch set (#3).
Change subject: util/kconfig: detect ncurses on FreeBSD
......................................................................
util/kconfig: detect ncurses on FreeBSD
Signed-off-by: Idwer Vollering <vidwer(a)gmail.com>
Change-Id: I4344ba2116c0b8618357db4248d993509cbb666e
---
A util/kconfig/patches/0013-util-kconfig-detect-ncurses-on-FreeBSD.patch
M util/kconfig/patches/series
2 files changed, 32 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/56677/3
--
To view, visit https://review.coreboot.org/c/coreboot/+/56677
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I4344ba2116c0b8618357db4248d993509cbb666e
Gerrit-Change-Number: 56677
Gerrit-PatchSet: 3
Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Martin Roth <martinroth(a)google.com>
Gerrit-Attention: Idwer Vollering <vidwer(a)gmail.com>
Gerrit-MessageType: newpatchset
Attention is currently required from: Martin Roth, Idwer Vollering.
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56677 )
Change subject: util/kconfig: detect ncurses on FreeBSD
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Patchset:
PS2:
The change needs to be recorded as a patch in patches/ that is registered in series. Other than that, looks good.
--
To view, visit https://review.coreboot.org/c/coreboot/+/56677
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I4344ba2116c0b8618357db4248d993509cbb666e
Gerrit-Change-Number: 56677
Gerrit-PatchSet: 2
Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Martin Roth <martinroth(a)google.com>
Gerrit-Attention: Idwer Vollering <vidwer(a)gmail.com>
Gerrit-Comment-Date: Thu, 29 Jul 2021 10:03:16 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: Yes
Gerrit-MessageType: comment
Stanley Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56689 )
Change subject: mb/google/dedede/var/boten: Set the xHCI LFPS period sampling off time to 0ms
......................................................................
mb/google/dedede/var/boten: Set the xHCI LFPS period sampling off time to 0ms
LTE module L850-GL may encounter U3 wakeup race condition with the host.
Setting xHCI LFPS periodic sampling off time to 0ms so that the host would not
miss the device-initiated U3 wakeup thus avoid the race condition.
BUG=b:187801363
BRANCH=dedede
TEST=flash the image to the device. Run following command to check the bits[7:4] is 0x0:
iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: stanley.wu <stanley1.wu(a)lcfc.corp-partner.google.com>
Change-Id: I9328e758ed92389e44b25ff4daf6ec19b37ae7d6
---
M src/mainboard/google/dedede/variants/boten/overridetree.cb
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/56689/1
diff --git a/src/mainboard/google/dedede/variants/boten/overridetree.cb b/src/mainboard/google/dedede/variants/boten/overridetree.cb
index 8c68f7e..d310f91 100644
--- a/src/mainboard/google/dedede/variants/boten/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/boten/overridetree.cb
@@ -80,6 +80,9 @@
register "SlowSlewRate" = "SlewRateFastBy8"
register "FastPkgCRampDisable" = "1"
+ # Set xHCI LFPS period sampling off time to 0 ms
+ register "xhci_lfps_sampling_offtime_ms" = "0"
+
device domain 0 on
device pci 04.0 on
chip drivers/intel/dptf
--
To view, visit https://review.coreboot.org/c/coreboot/+/56689
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I9328e758ed92389e44b25ff4daf6ec19b37ae7d6
Gerrit-Change-Number: 56689
Gerrit-PatchSet: 1
Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com>
Gerrit-MessageType: newchange
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56595 )
Change subject: mb/siemens/mc_ehl1: Disable LTR for all PCIe root ports
......................................................................
mb/siemens/mc_ehl1: Disable LTR for all PCIe root ports
Latency Tolerance Reporting is yet another PCIe power management feature
which can have a bad influence on realtime performance. Disable this
feature for all PCIe root ports.
Change-Id: I38023e095ca55efd2178ad944f651fee1f1c34cd
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56595
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
1 file changed, 8 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Mario Scheithauer: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
index d1c5c82..f05f025 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
@@ -77,6 +77,14 @@
register "PcieRpL1Substates[4]" = "L1_SS_DISABLED"
register "PcieRpL1Substates[5]" = "L1_SS_DISABLED"
+ # Disable LTR for all PCIe root ports
+ register "PcieRpLtrDisable[0]" = "true"
+ register "PcieRpLtrDisable[1]" = "true"
+ register "PcieRpLtrDisable[2]" = "true"
+ register "PcieRpLtrDisable[3]" = "true"
+ register "PcieRpLtrDisable[4]" = "true"
+ register "PcieRpLtrDisable[5]" = "true"
+
# Storage (SATA/SDCARD/EMMC) related UPDs
register "SataSalpSupport" = "0"
register "SataPortsEnable[0]" = "1"
--
To view, visit https://review.coreboot.org/c/coreboot/+/56595
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I38023e095ca55efd2178ad944f651fee1f1c34cd
Gerrit-Change-Number: 56595
Gerrit-PatchSet: 4
Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56594 )
Change subject: mb/siemens/mc_ehl1: Disable L1 substates for PCIe root ports
......................................................................
mb/siemens/mc_ehl1: Disable L1 substates for PCIe root ports
L1 substates of a PCIe link are meant to save some power when the link
is not active but have the drawback that the PCIe latency is increased
as PLLs are switched on and off as needed.
In order to get a better realtime performance, disable all substates for
every PCIe root port.
Change-Id: Ic5bc8410709d0f0094810bc11a7723e88c30e397
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56594
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
1 file changed, 8 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Mario Scheithauer: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
index 1eece7a..d1c5c82 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
@@ -69,6 +69,14 @@
register "PcieClkSrcClkReq[4]" = "0xFF"
register "PcieClkSrcClkReq[5]" = "0xFF"
+ # Disable all L1 substates for PCIe root ports
+ register "PcieRpL1Substates[0]" = "L1_SS_DISABLED"
+ register "PcieRpL1Substates[1]" = "L1_SS_DISABLED"
+ register "PcieRpL1Substates[2]" = "L1_SS_DISABLED"
+ register "PcieRpL1Substates[3]" = "L1_SS_DISABLED"
+ register "PcieRpL1Substates[4]" = "L1_SS_DISABLED"
+ register "PcieRpL1Substates[5]" = "L1_SS_DISABLED"
+
# Storage (SATA/SDCARD/EMMC) related UPDs
register "SataSalpSupport" = "0"
register "SataPortsEnable[0]" = "1"
--
To view, visit https://review.coreboot.org/c/coreboot/+/56594
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic5bc8410709d0f0094810bc11a7723e88c30e397
Gerrit-Change-Number: 56594
Gerrit-PatchSet: 4
Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56567 )
Change subject: mb/siemens/mc_ehl1: Enable Intel I210 MACPHY driver
......................................................................
mb/siemens/mc_ehl1: Enable Intel I210 MACPHY driver
This variant uses I210 MACPHYs so enable the I210 driver in order to set
the needed MAC addresses. In addition add the function to retrieve a
valid MAC address for the given MACPHY.
Change-Id: Id1d59349db1b86cfdd71bbe27577c0530e8f0b51
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56567
Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/siemens/mc_ehl/mainboard.c
M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Kconfig
2 files changed, 83 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Mario Scheithauer: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_ehl/mainboard.c b/src/mainboard/siemens/mc_ehl/mainboard.c
index c63beb74..fc7d31f 100644
--- a/src/mainboard/siemens/mc_ehl/mainboard.c
+++ b/src/mainboard/siemens/mc_ehl/mainboard.c
@@ -1,8 +1,87 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <baseboard/variants.h>
+#include <console/console.h>
#include <device/device.h>
+#include <hwilib.h>
+#include <i210.h>
#include <soc/gpio.h>
+#include <string.h>
+
+#define MAX_PATH_DEPTH 12
+#define MAX_NUM_MAPPINGS 10
+
+/** \brief This function can decide if a given MAC address is valid or not.
+ * Currently, addresses filled with 0xff or 0x00 are not valid.
+ * @param mac Buffer to the MAC address to check
+ * @return 0 if address is not valid, otherwise 1
+ */
+static uint8_t is_mac_adr_valid(uint8_t mac[MAC_ADDR_LEN])
+{
+ for (size_t i = 0; i < MAC_ADDR_LEN; i++) {
+ if (mac[i] != 0x00 && mac[i] != 0xff)
+ return 1;
+ if (mac[i] != mac[0])
+ return 1;
+ }
+ return 0;
+}
+
+/** \brief This function will search for a MAC address which can be assigned
+ * to a MACPHY.
+ * @param dev pointer to PCI device
+ * @param mac buffer where to store the MAC address
+ * @return cb_err CB_ERR or CB_SUCCESS
+ */
+enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[MAC_ADDR_LEN])
+{
+ struct bus *parent = dev->bus;
+ uint8_t buf[16], mapping[16], i = 0, chain_len = 0;
+
+ memset(buf, 0, sizeof(buf));
+ memset(mapping, 0, sizeof(mapping));
+
+ /* The first entry in the tree is the device itself. */
+ buf[0] = dev->path.pci.devfn;
+ chain_len = 1;
+ for (i = 1; i < MAX_PATH_DEPTH && parent->dev->bus->subordinate; i++) {
+ buf[i] = parent->dev->path.pci.devfn;
+ chain_len++;
+ parent = parent->dev->bus;
+ }
+ if (i == MAX_PATH_DEPTH) {
+ /* The path is deeper than MAX_PATH_DEPTH devices, error. */
+ printk(BIOS_ERR, "Too many bridges for %s\n", dev_path(dev));
+ return CB_ERR;
+ }
+ /*
+ * Now construct the mapping based on the device chain starting from
+ * root bridge device to the device itself.
+ */
+ mapping[0] = 1;
+ mapping[1] = chain_len;
+ for (i = 0; i < chain_len; i++)
+ mapping[i + 4] = buf[chain_len - i - 1];
+
+ /* Open main hwinfo block */
+ if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS)
+ return CB_ERR;
+ /* Now try to find a valid MAC address in hwinfo for this mapping. */
+ for (i = 0; i < MAX_NUM_MAPPINGS; i++) {
+ if (hwilib_get_field(XMac1Mapping + i, buf, 16) != 16)
+ continue;
+ if (memcmp(buf, mapping, chain_len + 4))
+ continue;
+ /* There is a matching mapping available, get MAC address. */
+ if (hwilib_get_field(XMac1 + i, mac, MAC_ADDR_LEN) == MAC_ADDR_LEN) {
+ if (is_mac_adr_valid(mac))
+ return CB_SUCCESS;
+ }
+ return CB_ERR;
+ }
+ /* No MAC address found for */
+ return CB_ERR;
+}
static void mainboard_init(void *chip_info)
{
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Kconfig
index f484eaa..a9a5a4c 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Kconfig
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Kconfig
@@ -1,5 +1,9 @@
if BOARD_SIEMENS_MC_EHL1
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select DRIVER_INTEL_I210
+
config FMDFILE
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/mc_ehl.fmd"
--
To view, visit https://review.coreboot.org/c/coreboot/+/56567
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Id1d59349db1b86cfdd71bbe27577c0530e8f0b51
Gerrit-Change-Number: 56567
Gerrit-PatchSet: 4
Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-MessageType: merged
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56565 )
Change subject: mb/siemens/mc_ehl: Enable SIEMENS_HWILIB
......................................................................
mb/siemens/mc_ehl: Enable SIEMENS_HWILIB
All variants based on mc_ehl will use the Siemens HWILIB. Select the
Kconfig switch on baseboard level.
Change-Id: I940f84a4a7449487fe78c793f8dbb1c1b49fa54b
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56565
Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/siemens/mc_ehl/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Mario Scheithauer: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_ehl/Kconfig b/src/mainboard/siemens/mc_ehl/Kconfig
index 6f22e5b..5f1ddcf 100644
--- a/src/mainboard/siemens/mc_ehl/Kconfig
+++ b/src/mainboard/siemens/mc_ehl/Kconfig
@@ -9,6 +9,7 @@
select MAINBOARD_HAS_TPM2
select MAINBOARD_HAS_LPC_TPM
select TPM_MEASURED_BOOT
+ select USE_SIEMENS_HWILIB
source "src/mainboard/siemens/mc_ehl/variants/*/Kconfig"
--
To view, visit https://review.coreboot.org/c/coreboot/+/56565
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I940f84a4a7449487fe78c793f8dbb1c1b49fa54b
Gerrit-Change-Number: 56565
Gerrit-PatchSet: 4
Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-MessageType: merged