coreboot-gerrit June 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in
by Cliff Huang (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Cliff Huang, Patrick Rudolph. Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55127 to look at the new patch set (#2). Change subject: soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in ...................................................................... soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in This change adds S0ix device specific method _DSM ( UUID: 57a6512e-3979-4e9d-9708-ff13b2508972) for Intel Power Engine Plug-in. Alone with this change, two kernel changes are also required: https://chromium-review.googlesource.com/2800280 https://chromium-review.googlesource.com/2800281 Once done, substate_requirement_registers is created under /sys/kernel/debug/pmc_core/ Use: 'cat /sys/kernel/debug/pmc_core/substate_requirement_registers' to check the content. BUG=b:185437326 brya: _DSM method need to implemented in coreboot for PMC requirement register. Change-Id: I991662cbebf63bd71139ed37ff2588ba73f30398 Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> --- M src/soc/intel/common/block/acpi/acpi/globalnvs.asl M src/soc/intel/common/block/acpi/acpi/pep.asl 2 files changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/55127/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I991662cbebf63bd71139ed37ff2588ba73f30398 Gerrit-Change-Number: 55127 Gerrit-PatchSet: 2 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mainboard: Add labtop series
by Star Labs (Code Review) 01 Jun '21

01 Jun '21

Star Labs has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/52798 ) Change subject: soc/mainboard: Add labtop series ...................................................................... Abandoned Gerrit not allowing rebase -- To view, visit https://review.coreboot.org/c/coreboot/+/52798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37c74d03d86fb124ed96e45d1bf137eb2ec57251 Gerrit-Change-Number: 52798 Gerrit-PatchSet: 27 Gerrit-Owner: Star Labs <admin(a)starlabs.systems> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: drivers/intel/mipi_camera: Add macros to increase code readability
by Tim Wawrzynczak (Code Review) 01 Jun '21

01 Jun '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55097 ) Change subject: drivers/intel/mipi_camera: Add macros to increase code readability ...................................................................... drivers/intel/mipi_camera: Add macros to increase code readability This will be used to pass information to driver through ACPI in devicetree. Example https://review.coreboot.org/c/coreboot/+/52013 register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3" register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" TEST=Add these macros in devicetree, build and check static.c for consistency Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.corp-partner.google.com> Change-Id: Ia4137e09c934bf06857ceedb933e616bed5070dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/55097 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/intel/mipi_camera/chip.h 1 file changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Rizwan Qureshi: Looks good to me, approved Subrata Banik: Looks good to me, approved Maulik V Vaghela: Looks good to me, approved diff --git a/src/drivers/intel/mipi_camera/chip.h b/src/drivers/intel/mipi_camera/chip.h index 64942b6..35a90bd 100644 --- a/src/drivers/intel/mipi_camera/chip.h +++ b/src/drivers/intel/mipi_camera/chip.h @@ -14,6 +14,14 @@ #define MAX_GPIO_CONFIGS 4 #define MAX_PWR_OPS 5 #define MAX_GUARDED_RESOURCES 10 +#define IMGCLKOUT_0 0 +#define IMGCLKOUT_1 1 +#define IMGCLKOUT_2 2 +#define IMGCLKOUT_3 3 +#define IMGCLKOUT_4 4 +#define IMGCLKOUT_5 5 +#define FREQ_24_MHZ 0 +#define FREQ_19_2_MHZ 1 #define SEQ_OPS_CLK_ENABLE(ind, delay) \ { .type = IMGCLK, .index = (ind), .action = ENABLE, .delay_ms = (delay) } -- To view, visit https://review.coreboot.org/c/coreboot/+/55097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4137e09c934bf06857ceedb933e616bed5070dd Gerrit-Change-Number: 55097 Gerrit-PatchSet: 8 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Enable WFC
by Tim Wawrzynczak (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Varshit B Pandya, Furquan Shaikh, Rizwan Qureshi, Meera Ravindranath, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52013 ) Change subject: mb/google/brya: Enable WFC ...................................................................... Patch Set 9: (1 comment) File src/mainboard/google/brya/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/52013/comment/d6a7a0ed_022c4a4e PS3, Line 188: register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" > to be frank I have not tried this sequence, the data sheet suggested to bring the sensor out of Rese […] This does seem OK with the datasheet. -- To view, visit https://review.coreboot.org/c/coreboot/+/52013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5e9c28f255bdf86a68ce80a4f853be4e7c7ccfe Gerrit-Change-Number: 52013 Gerrit-PatchSet: 9 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Shobhit Srivastava <shobhit.srivastava(a)intel.com> Gerrit-CC: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 01 Jun 2021 21:36:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Varshit B Pandya <varshit.b.pandya(a)intel.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Enable WFC
by Tim Wawrzynczak (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Varshit B Pandya, Furquan Shaikh, Rizwan Qureshi, Meera Ravindranath, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52013 ) Change subject: mb/google/brya: Enable WFC ...................................................................... Patch Set 9: Code-Review+2 (5 comments) Patchset: PS9: Thanks Varshit! File src/mainboard/google/brya/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/52013/comment/6fd758d0_300c6429 PS8, Line 179: 3 > > Could we get an SoC #define or enum for these? […] Done https://review.coreboot.org/c/coreboot/+/52013/comment/eba7282c_5dbbbba9 PS8, Line 179: 3 > > Could we get an SoC #define or enum for these? […] Done https://review.coreboot.org/c/coreboot/+/52013/comment/2a7093fe_b46b4ef9 PS8, Line 180: 1 > something like this ? […] Done https://review.coreboot.org/c/coreboot/+/52013/comment/caffbea3_0a484b14 PS8, Line 180: 1 > something like this ? […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5e9c28f255bdf86a68ce80a4f853be4e7c7ccfe Gerrit-Change-Number: 52013 Gerrit-PatchSet: 9 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Shobhit Srivastava <shobhit.srivastava(a)intel.com> Gerrit-CC: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 01 Jun 2021 21:35:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Varshit B Pandya <varshit.b.pandya(a)intel.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP]Allow to build romstage sources inside the bootblock
by Aaron Durbin (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Arthur Heymans, Raul Rangel, Furquan Shaikh, Philipp Hug, ron minnich, Stefan Reinauer, Angel Pons, Subrata Banik, Julius Werner, Andrey Petrov, Patrick Rudolph, Piotr Król, Jason Glenesk, Michał Żygowski, Martin Roth, Marshall Dawson, Ron Minnich, Felix Held. Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55068 ) Change subject: [WIP]Allow to build romstage sources inside the bootblock ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: Could you please elaborate on what diligence was done in the analysis w.r.t. semantics of existing code? I know we've built a lot of infrastructure around ENV_x, etc. This change obviously allows previously mutually exclusive settings to coexist. -- To view, visit https://review.coreboot.org/c/coreboot/+/55068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id68390edc1ba228b121cca89b80c64a92553e284 Gerrit-Change-Number: 55068 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)chromium.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Branden Waldner <scruffy99(a)gmail.com> Gerrit-CC: Keith Hui <buurin(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: ron minnich <rminnich(a)chromium.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 01 Jun 2021 21:33:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in
by build bot (Jenkins) (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55127 ) Change subject: soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/block/acpi/acpi/pep.asl: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120480): https://review.coreboot.org/c/coreboot/+/55127/comment/ae85c56e_dea59e00 PS1, Line 27: trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/55127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I991662cbebf63bd71139ed37ff2588ba73f30398 Gerrit-Change-Number: 55127 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 01 Jun 2021 21:31:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in
by Cliff Huang (Code Review) 01 Jun '21

01 Jun '21

Cliff Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55127 ) Change subject: soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in ...................................................................... soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in This change adds S0ix device specific method _DSM ( UUID: 57a6512e-3979-4e9d-9708-ff13b2508972) for Intel Power Engine Plug-in. Alone with this change, two kernel changes are also required: https://chromium-review.googlesource.com/2800280 https://chromium-review.googlesource.com/2800281 Once done, substate_requirement_registers is created under /sys/kernel/debug/pmc_core/ Use: 'cat /sys/kernel/debug/pmc_core/substate_requirement_registers' to check the content. BUG=b:185437326 brya: _DSM method need to implemented in coreboot for PMC requirement register. Change-Id: I991662cbebf63bd71139ed37ff2588ba73f30398 Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> --- M src/soc/intel/common/block/acpi/acpi/globalnvs.asl M src/soc/intel/common/block/acpi/acpi/pep.asl 2 files changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/55127/1 diff --git a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl index 161381f..d4096d4 100644 --- a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl +++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl @@ -24,4 +24,5 @@ UIOR, 8, // 0x2f - UART debug controller init on S3 resume A4GB, 64, // 0x30 - 0x37 Base of above 4GB MMIO Resource A4GS, 64, // 0x38 - 0x3f Length of above 4GB MMIO Resource + LPMR, 32, // 0x40 - 0x43 Low Power Mode required register Address } diff --git a/src/soc/intel/common/block/acpi/acpi/pep.asl b/src/soc/intel/common/block/acpi/acpi/pep.asl index 2e2a25f..223b899 100644 --- a/src/soc/intel/common/block/acpi/acpi/pep.asl +++ b/src/soc/intel/common/block/acpi/acpi/pep.asl @@ -9,6 +9,11 @@ #define PEPD_DSM_LPI_S0IX_ENTRY 5 #define PEPD_DSM_LPI_S0IX_EXIT 6 +/* Low Power Mode requirements - data length (byte) */ +#define PEPD_PMC_PWRM_LPM_REQ_DATA_LEN 192 +/* Low Power Mode requirements - data length (bit) */ +#define PEPD_PMC_PWRM_LPM_REQ_BITS_DATA_LEN 1536 + External(\_SB.MS0X, MethodObj) External(\_SB.PCI0.LPCB.EC0.S0IX, MethodObj) External(\_SB.PCI0.EGPM, MethodObj) @@ -18,6 +23,15 @@ { Name(_HID, "INT33A1") /* Intel Power Engine */ Name(_CID, EISAID("PNP0D80")) + Name (LBUF, Buffer(PEPD_PMC_PWRM_LPM_REQ_DATA_LEN) {}) + + OperationRegion (LS0I, SystemMemory, LPMR, PEPD_PMC_PWRM_LPM_REQ_DATA_LEN) + Field (LS0I, ByteAcc, Lock, Preserve) + { + /* Low Power Mode Required Register */ + L0IX, PEPD_PMC_PWRM_LPM_REQ_BITS_DATA_LEN, + } + Method(_DSM, 4) { /* Low Power Idle S0 helper */ @@ -120,6 +134,18 @@ } } + If ((Arg0 == ToUUID ("57a6512e-3979-4e9d-9708-ff13b2508972"))) + { + If ((Arg2 == Zero)) { + Return (Buffer(One) { 0x03 }) + } + If ((Arg2 == 0x01)) + { + Store (L0IX, LBUF) + Return (LBUF) + } + } + Return(Buffer(One) {0x00}) } // Method(_DSM) } // Device (PEPD) -- To view, visit https://review.coreboot.org/c/coreboot/+/55127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I991662cbebf63bd71139ed37ff2588ba73f30398 Gerrit-Change-Number: 55127 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: include: always unsigned long for size_t
by Julius Werner (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Paul Menzel, Jacob Garber. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55075 ) Change subject: include: always unsigned long for size_t ...................................................................... Patch Set 1: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55075/comment/bb4a1285_b7113c27 PS1, Line 13: printf format specifiers) I'm not against cleaning this up in general, but note that printf() format strings should be using the `z` length specifier (e.g. "%zu") for size_t types anyway, which already works correctly. https://review.coreboot.org/c/coreboot/+/55075/comment/bb09467d_9a162663 PS1, Line 15: This also removes a weird macro hack for defining ssize_t. Note that the same construct exists in libpayload, in case you want to fix that as well. Patchset: PS1: > Example build failure: […] `z` is intended for use with size_t and needs to continue to work. I'm just not really sure why it doesn't here. I guess GCC hardcodes which type it expects as size_t for a given architecture? Which would be unfortunate, but if that's the case I think we need to keep this as it is because we still want to be able to use that modifier. (Still can clean up the macro stuff, at least.) File src/include/stddef.h: https://review.coreboot.org/c/coreboot/+/55075/comment/56b93f57_ef4b0b2e PS1, Line 9: typedef signed long ssize_t; nit: might be nice to add a _Static_assert() check for the size (should be same as sizeof(void *)) like the stdint.h types have while you're here? -- To view, visit https://review.coreboot.org/c/coreboot/+/55075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a8fa97c6961991dd8e291d2dc7d8762f83cad6d Gerrit-Change-Number: 55075 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Comment-Date: Tue, 01 Jun 2021 21:30:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: Reserve wlan & wpss dram regions index order corrected
by Shelley Chen (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Ravi kumar. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55102 ) Change subject: sc7280: Reserve wlan & wpss dram regions index order corrected ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8501e9ce52bb296bb42797d8b43fd38174b80550 Gerrit-Change-Number: 55102 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Comment-Date: Tue, 01 Jun 2021 21:22:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit June 2021