coreboot-gerrit June 2021

coreboot-gerrit@coreboot.org

1 participants
7127 discussions

Change in coreboot[master]: mb/google/volteer/var/volet: Update gpio and devicetree settings
by Tim Wawrzynczak (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Nick Vaccaro, Sheng-Liang Pan, YH Lin. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55113 ) Change subject: mb/google/volteer/var/volet: Update gpio and devicetree settings ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Needs to be rebased on master -- To view, visit https://review.coreboot.org/c/coreboot/+/55113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0e9557e01ce1e7a49a3dddf6da3e4a29587a8b7 Gerrit-Change-Number: 55113 Gerrit-PatchSet: 3 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Comment-Date: Wed, 02 Jun 2021 02:46:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/volteer/var/volet: add volet memory configuration.
by Tim Wawrzynczak (Code Review) 02 Jun '21

02 Jun '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55096 ) Change subject: mb/google/volteer/var/volet: add volet memory configuration. ...................................................................... mb/google/volteer/var/volet: add volet memory configuration. volet use same memory configuration from Voxel, copy voxel setting to volet. BUG=b:186334008 TEST=FW_NAME=volet emerge-volteer coreboot chromeos-bootimage Signed-off-by: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Change-Id: I7e65b18f2ddae3d1ce02d9006153269697188f61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55096 Reviewed-by: Paul Fagerburg <pfagerburg(a)chromium.org> Reviewed-by: YH Lin <yueherngl(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/mainboard/google/volteer/variants/volet/Makefile.inc A src/mainboard/google/volteer/variants/volet/memory.c M src/mainboard/google/volteer/variants/volet/memory/Makefile.inc M src/mainboard/google/volteer/variants/volet/memory/dram_id.generated.txt M src/mainboard/google/volteer/variants/volet/memory/mem_parts_used.txt 5 files changed, 81 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified YH Lin: Looks good to me, but someone else must approve Sheng-Liang Pan: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved Paul Fagerburg: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/volteer/variants/volet/Makefile.inc b/src/mainboard/google/volteer/variants/volet/Makefile.inc new file mode 100644 index 0000000..9064208 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volet/Makefile.inc @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-y += memory.c diff --git a/src/mainboard/google/volteer/variants/volet/memory.c b/src/mainboard/google/volteer/variants/volet/memory.c new file mode 100644 index 0000000..fe2b2b1 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volet/memory.c @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> + +static const struct mb_cfg board_memcfg = { + .type = MEM_TYPE_LP4X, + + /* DQ byte map */ + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 3, 0, 1, 2, 6, 7, 5, 4, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 12, 15, 14, 13, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ + }, + .ddr1 = { + .dq0 = { 12, 15, 13, 14, 10, 8, 11, 9, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 5, 6, 7, 4, 0, 3, 1, 2 }, /* DDR1_DQ1[7:0] */ + }, + .ddr2 = { + .dq0 = { 2, 3, 0, 1, 7, 6, 5, 4, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 12, 14, 15, 13, 10, 9, 8, 11 }, /* DDR2_DQ1[7:0] */ + }, + .ddr3 = { + .dq0 = { 15, 12, 13, 14, 8, 9, 10, 11, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 7, 6, 4, 5, 2, 0, 3, 1 }, /* DDR3_DQ1[7:0] */ + }, + .ddr4 = { + .dq0 = { 6, 5, 4, 7, 0, 3, 2, 1, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 15, 14, 13, 12, 11, 8, 9, 10 }, /* DDR4_DQ1[7:0] */ + }, + .ddr5 = { + .dq0 = { 11, 9, 10, 8, 12, 14, 13, 15, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 1, 0, 2, 3, 6, 7, 5, 4 }, /* DDR5_DQ1[7:0] */ + }, + .ddr6 = { + .dq0 = { 2, 3, 0, 1, 5, 4, 6, 7, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 13, 14, 15, 12, 11, 10, 8, 9 }, /* DDR6_DQ1[7:0] */ + }, + .ddr7 = { + .dq0 = { 14, 13, 15, 12, 9, 8, 10, 11, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 4, 5, 1, 2, 6, 0, 3, 7 }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR7_DQS[1:0] */ + }, + + .ect = true, /* Enable Early Command Training */ +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &board_memcfg; +} diff --git a/src/mainboard/google/volteer/variants/volet/memory/Makefile.inc b/src/mainboard/google/volteer/variants/volet/memory/Makefile.inc index b0ca222..f40fba6 100644 --- a/src/mainboard/google/volteer/variants/volet/memory/Makefile.inc +++ b/src/mainboard/google/volteer/variants/volet/memory/Makefile.inc @@ -1,5 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-or-later ## This is an auto-generated file. Do not edit!! -## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. -SPD_SOURCES = placeholder.spd.hex +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR +SPD_SOURCES += lp4x-spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += lp4x-spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR diff --git a/src/mainboard/google/volteer/variants/volet/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/volet/memory/dram_id.generated.txt index fa24790..8d472df 100644 --- a/src/mainboard/google/volteer/variants/volet/memory/dram_id.generated.txt +++ b/src/mainboard/google/volteer/variants/volet/memory/dram_id.generated.txt @@ -1 +1,7 @@ DRAM Part Name ID to assign +MT53E512M32D2NP-046 WT:E 0 (0000) +H9HCNNNBKMMLXR-NEE 0 (0000) +K4U6E3S4AA-MGCR 0 (0000) +MT53E1G32D2NP-046 WT:A 1 (0001) +H9HCNNNCPMMLXR-NEE 2 (0010) +K4UBE3D4AA-MGCR 2 (0010) diff --git a/src/mainboard/google/volteer/variants/volet/memory/mem_parts_used.txt b/src/mainboard/google/volteer/variants/volet/memory/mem_parts_used.txt index e4258b5..5ddd52e 100644 --- a/src/mainboard/google/volteer/variants/volet/memory/mem_parts_used.txt +++ b/src/mainboard/google/volteer/variants/volet/memory/mem_parts_used.txt @@ -1,11 +1,6 @@ -# This is a CSV file containing a list of memory parts used by this variant. -# One part per line with an optional fixed ID in column 2. -# Only include a fixed ID if it is required for legacy reasons! -# Generated IDs are dependent on the order of parts in this file, -# so new parts must always be added at the end of the file! -# -# Generate an updated Makefile.inc and dram_id.generated.txt by running the -# gen_part_id tool from util/spd_tools/{ddr4,lp4x}. -# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. - -# Part Name +MT53E512M32D2NP-046 WT:E +H9HCNNNBKMMLXR-NEE +K4U6E3S4AA-MGCR +MT53E1G32D2NP-046 WT:A +H9HCNNNCPMMLXR-NEE +K4UBE3D4AA-MGCR -- To view, visit https://review.coreboot.org/c/coreboot/+/55096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e65b18f2ddae3d1ce02d9006153269697188f61 Gerrit-Change-Number: 55096 Gerrit-PatchSet: 4 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: drivers/pcie/rtd3/device: Add PCIe RTD3 driver
by Furquan Shaikh (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Tim Wawrzynczak, Karthik Ramasubramanian, Felix Held. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54966 ) Change subject: drivers/pcie/rtd3/device: Add PCIe RTD3 driver ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/54966/comment/1952b91a_f4eda5f8 PS1, Line 9: I decided : to copy and modify it because the Intel driver has a lot of Intel : specific code. > I filed b/189834892 to track the `GL9755` issue. Thanks Raul! File src/soc/amd/common/block/rtd3/rtd3.c: https://review.coreboot.org/c/coreboot/+/54966/comment/4d5018a6_57b70bc1 PS1, Line 210: pci_dev_read_resources > It sounds like we need some type of composition. How about something like this? […] That seems okay to me. Tim? -- To view, visit https://review.coreboot.org/c/coreboot/+/54966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2adfc925183ff7a19ab97e89212bc87c40d552d0 Gerrit-Change-Number: 54966 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Mario Limonciello <mario.limonciello(a)amd.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 02 Jun 2021 02:20:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: intel/common/block/memory: Add saving memory info API to common block
by Furquan Shaikh (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Martin Roth, Selma Bensaid, Tim Wawrzynczak, Subrata Banik, Bernardo Perez Priego, Usha P, Andrey Petrov, Patrick Rudolph. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51105 ) Change subject: intel/common/block/memory: Add saving memory info API to common block ...................................................................... Patch Set 7: (13 comments) File src/soc/intel/common/block/memory/Kconfig: https://review.coreboot.org/c/coreboot/+/51105/comment/ab4e4ea3_8f53a89a PS7, Line 30: endif The new Kconfig should probably be under this if...endif block? File src/soc/intel/common/block/memory/meminfo.c: https://review.coreboot.org/c/coreboot/+/51105/comment/a0a9fe0e_7a4bae19 PS7, Line 3: #include <arch/symbols.h> Is this required? https://review.coreboot.org/c/coreboot/+/51105/comment/11085c5a_fc276ba6 PS7, Line 4: #include <assert.h> : #include <cbfs.h> I don't think these are required. https://review.coreboot.org/c/coreboot/+/51105/comment/75fbb5af_b69e020f PS7, Line 13: #include <smbios.h> Is this required? https://review.coreboot.org/c/coreboot/+/51105/comment/7352e9c4_670040fb PS7, Line 22: CONTROLLER_INFO Just curious: Are CONTROLLER_INFO, CHANNEL_INFO, DIMM_INFO, MAX_NODE, MAX_CH, etc. definitions pulled in by fsp/api.h? It would be good to capture these expectations in meminfo.h and outline all the macros that are expected to be defined by the SoC FSP headers. https://review.coreboot.org/c/coreboot/+/51105/comment/bd56dfe8_da3802f8 PS7, Line 36: SMBIOS Add "ERROR:" prefix so that it gets caught by scripts. https://review.coreboot.org/c/coreboot/+/51105/comment/b8015820_44e5aba6 PS7, Line 46: CBMEM Same here with "ERROR:" prefix. https://review.coreboot.org/c/coreboot/+/51105/comment/1b127c7c_445fc1ed PS7, Line 46: entry for DIMM info missing Rather than missing, it could not be allocated. https://review.coreboot.org/c/coreboot/+/51105/comment/8a0af272_0d296877 PS7, Line 64: channel++) { This most likely fits on the previous line with 96-character limit. https://review.coreboot.org/c/coreboot/+/51105/comment/51d76e0f_09ba2cd6 PS7, Line 70: dimm++) { This too most likely fits on the previous line. https://review.coreboot.org/c/coreboot/+/51105/comment/a79d500f_1cc91a26 PS7, Line 77: MRC_DDR_TYPE_DDR4 Are these MRC memory types supposed to be different than the SMBIOS memory types? I remember that MRC was using a different memory type for LPDDR3, but haven't seen that for any other memory types. It would be good to restrict this to only those types that actually need a conversion and also add a comment here explaining why that is being done. https://review.coreboot.org/c/coreboot/+/51105/comment/2efc8de7_8c697d0d PS7, Line 90: /* If there is no DRAM part number overridden by : * mainboard then use original one. */ Please use one of the recommended comment styles: https://doc.coreboot.org/contributing/coding_style.html#commenting https://review.coreboot.org/c/coreboot/+/51105/comment/bd92c034_41231d09 PS7, Line 100: SPD_SAVE_OFFSET_SERIAL; This probably fits on the previous line. -- To view, visit https://review.coreboot.org/c/coreboot/+/51105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78d14c71d5d19f58e6a27ed5ef8269c6678f32a5 Gerrit-Change-Number: 51105 Gerrit-PatchSet: 7 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 02 Jun 2021 02:07:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/dedede/var/sasukette: Modify the touch pad I2C address
by Tao Xia (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Henry Sun, Paul Menzel. Tao Xia has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55035 ) Change subject: mb/google/dedede/var/sasukette: Modify the touch pad I2C address ...................................................................... Patch Set 4: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55035/comment/42998829_1ad56ee2 PS3, Line 7: slave > Nit: slave -> I2C just as an effort to use inclusive language. Done https://review.coreboot.org/c/coreboot/+/55035/comment/b905303a_82fdd367 PS3, Line 9: slave > Same comment as above. Done https://review.coreboot.org/c/coreboot/+/55035/comment/2c82e7aa_22ce5c6b PS3, Line 10: > Nit: remove extra space at the end of the line. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/55035 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0bd80baa27dfeb7bcb43f0ca4b02e1228e372a6 Gerrit-Change-Number: 55035 Gerrit-PatchSet: 4 Gerrit-Owner: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-CC: Jessie Xu <xuyanan(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 02 Jun 2021 01:46:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/dedede/var/blipper: Configure I2C times for touchpad/touchp...
by zanxi chen (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Furquan Shaikh, Henry Sun, Paul Menzel, Tao Xia, Karthik Ramasubramanian, Karthikeyan Ramasubramanian. zanxi chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54249 ) Change subject: mb/google/dedede/var/blipper: Configure I2C times for touchpad/touchpanel/codec ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/dedede/variants/blipper/overridetree.cb: https://review.coreboot.org/c/coreboot/+/54249/comment/80a3b72a_93f1f592 PS3, Line 24: .rise_time_ns=247, > Use space before and after = i.e. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/54249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8438e37be49f8a74f53fd8460110dac1a3f06993 Gerrit-Change-Number: 54249 Gerrit-PatchSet: 4 Gerrit-Owner: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ginger Zhang <zhangqingchun(a)huaqin.corp-partner.google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-CC: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Comment-Date: Wed, 02 Jun 2021 01:34:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek: Initialize SSPM
by Hung-Te Lin (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Rex-BC Chen, Paul Menzel. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55051 ) Change subject: soc/mediatek: Initialize SSPM ...................................................................... Patch Set 8: (1 comment) File src/soc/mediatek/mt8195/Kconfig: https://review.coreboot.org/c/coreboot/+/55051/comment/56edf8ff_c0f3ce4a PS2, Line 32: The file name of the MediaTek SSPM firmware. > That can be easily found in Makefile. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/55051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia227ea9f7d58129068cb36ec2de7d9feb677006b Gerrit-Change-Number: 55051 Gerrit-PatchSet: 8 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 02 Jun 2021 01:24:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek: Initialize SSPM
by Yu-Ping Wu (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Paul Menzel. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55051 ) Change subject: soc/mediatek: Initialize SSPM ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/55051/comment/ebc5a856_786fbf2d PS7, Line 9: Load SSPM firmware and boot up SSPM in ramstage. : : DUT info: : CBFS: Found 'sspm.bin' @0x3bd80 size 0xc00f in mcache @0xffffea64 : mtk_init_mcu: Loaded (and reset) sspm.bin in 23 msecs (137348 bytes) > Load SSPM firmware and boot up SSPM in ramstage. This adds 23ms to the boot time. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/55051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia227ea9f7d58129068cb36ec2de7d9feb677006b Gerrit-Change-Number: 55051 Gerrit-PatchSet: 8 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 02 Jun 2021 01:18:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya: Create primus variant
by Scott Chao (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Scott Chao. Scott Chao has removed Tim Wawrzynczak from this change. ( https://review.coreboot.org/c/coreboot/+/55129 ) Change subject: mb/google/brya: Create primus variant ...................................................................... Removed reviewer Tim Wawrzynczak. -- To view, visit https://review.coreboot.org/c/coreboot/+/55129 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib59d2e506c39ea8cbd78960d4c7b301f267ac1ad Gerrit-Change-Number: 55129 Gerrit-PatchSet: 2 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-MessageType: deleteReviewer

1 0

Change in coreboot[master]: soc: common: gpio: Add support for common GPIO driver
by Shelley Chen (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Ravi kumar, Taniya Das, Julius Werner, mturney mturney. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55076 ) Change subject: soc: common: gpio: Add support for common GPIO driver ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia672130c6ca938d9284cae5071307637709480d1 Gerrit-Change-Number: 55076 Gerrit-PatchSet: 2 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Taniya Das <tdas(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Wed, 02 Jun 2021 01:09:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2021