coreboot-gerrit June 2021

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Change in coreboot[master]: mb/google/volteer/var/volet: Update gpio and devicetree settings
by Tim Wawrzynczak (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Nick Vaccaro, Sheng-Liang Pan, YH Lin. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55113 ) Change subject: mb/google/volteer/var/volet: Update gpio and devicetree settings ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0e9557e01ce1e7a49a3dddf6da3e4a29587a8b7 Gerrit-Change-Number: 55113 Gerrit-PatchSet: 3 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Comment-Date: Wed, 02 Jun 2021 00:59:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/var/volet: Update gpio and devicetree settings
by Sheng-Liang Pan (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, YH Lin. Sheng-Liang Pan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55113 ) Change subject: mb/google/volteer/var/volet: Update gpio and devicetree settings ...................................................................... Patch Set 3: Code-Review+1 (3 comments) File src/mainboard/google/volteer/variants/volet/overridetree.cb: https://review.coreboot.org/c/coreboot/+/55113/comment/aabc566f_c0fa90ee PS2, Line 26: device i2c 1a on : end > nit: […] done https://review.coreboot.org/c/coreboot/+/55113/comment/908ac5d7_300a500b PS2, Line 44: device i2c 32 on : end > ``` […] done https://review.coreboot.org/c/coreboot/+/55113/comment/d8d49330_6241afba PS2, Line 112: 0x2c > Please be consistent with i2c address formats: […] done -- To view, visit https://review.coreboot.org/c/coreboot/+/55113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0e9557e01ce1e7a49a3dddf6da3e4a29587a8b7 Gerrit-Change-Number: 55113 Gerrit-PatchSet: 3 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Comment-Date: Wed, 02 Jun 2021 00:55:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/var/volet: Update gpio and devicetree settings
by Sheng-Liang Pan (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Nick Vaccaro, Sheng-Liang Pan, YH Lin. Hello build bot (Jenkins), YH Lin, Tim Wawrzynczak, Nick Vaccaro, YH Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55113 to look at the new patch set (#3). Change subject: mb/google/volteer/var/volet: Update gpio and devicetree settings ...................................................................... mb/google/volteer/var/volet: Update gpio and devicetree settings Based on schematic and gpio table of volet, update gpio and devicetree settings for volet Proto. BUG=b:186334008 TEST=FW_NAME=volet emerge-volteer coreboot chromeos-bootimage Signed-off-by: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Change-Id: Ia0e9557e01ce1e7a49a3dddf6da3e4a29587a8b7 --- M src/mainboard/google/volteer/variants/volet/Makefile.inc A src/mainboard/google/volteer/variants/volet/gpio.c M src/mainboard/google/volteer/variants/volet/overridetree.cb A src/mainboard/google/volteer/variants/volet/ramstage.c 4 files changed, 530 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/55113/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/55113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0e9557e01ce1e7a49a3dddf6da3e4a29587a8b7 Gerrit-Change-Number: 55113 Gerrit-PatchSet: 3 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya: Create primus variant
by Scott Chao (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Tim Wawrzynczak. Hello Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55129 to look at the new patch set (#2). Change subject: mb/google/brya: Create primus variant ...................................................................... mb/google/brya: Create primus variant Create the primus variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-generated by create_coreboot_variant.sh version 4.5.0) BUG=b:188272162 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_PRIMUS Signed-off-by: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Change-Id: Ib59d2e506c39ea8cbd78960d4c7b301f267ac1ad --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/primus/include/variant/ec.h A src/mainboard/google/brya/variants/primus/include/variant/gpio.h A src/mainboard/google/brya/variants/primus/memory/Makefile.inc A src/mainboard/google/brya/variants/primus/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/primus/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/primus/overridetree.cb 8 files changed, 46 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/55129/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55129 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib59d2e506c39ea8cbd78960d4c7b301f267ac1ad Gerrit-Change-Number: 55129 Gerrit-PatchSet: 2 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: intel/common/block/memory: Add saving memory info API to common block
by Bernardo Perez Priego (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Furquan Shaikh, Martin Roth, Selma Bensaid, Subrata Banik, Usha P, Andrey Petrov, Patrick Rudolph. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Selma Bensaid, Subrata Banik, Usha P, Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51105 to look at the new patch set (#7). Change subject: intel/common/block/memory: Add saving memory info API to common block ...................................................................... intel/common/block/memory: Add saving memory info API to common block Memory information is stored into CBMEM later to be used to generate SMBIOS table 17. This function can be part of intel common block and is available by defining SOC_INTEL_COMMON_BLOCK_MEMINFO. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Change-Id: I78d14c71d5d19f58e6a27ed5ef8269c6678f32a5 --- A src/soc/intel/common/block/include/intelblocks/meminfo.h M src/soc/intel/common/block/memory/Kconfig M src/soc/intel/common/block/memory/Makefile.inc A src/soc/intel/common/block/memory/meminfo.c 4 files changed, 143 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/51105/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/51105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78d14c71d5d19f58e6a27ed5ef8269c6678f32a5 Gerrit-Change-Number: 51105 Gerrit-PatchSet: 7 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya: Create primus variant
by Scott Chao (Code Review) 02 Jun '21

02 Jun '21

Scott Chao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55129 ) Change subject: mb/google/brya: Create primus variant ...................................................................... mb/google/brya: Create primus variant Create the primus variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-generated by create_coreboot_variant.sh version 4.5.0) BUG=b:188272162 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_PRIMUS Signed-off-by: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Change-Id: Ib59d2e506c39ea8cbd78960d4c7b301f267ac1ad --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/primus/include/variant/ec.h A src/mainboard/google/brya/variants/primus/include/variant/gpio.h A src/mainboard/google/brya/variants/primus/memory/Makefile.inc A src/mainboard/google/brya/variants/primus/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/primus/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/primus/overridetree.cb 8 files changed, 46 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/55129/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index c28c293..3acb07e 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -72,10 +72,12 @@ config MAINBOARD_PART_NUMBER string default "Brya" if BOARD_GOOGLE_BRYA0 + default "Primus" if BOARD_GOOGLE_PRIMUS config VARIANT_DIR string default "brya0" if BOARD_GOOGLE_BRYA0 + default "primus" if BOARD_GOOGLE_PRIMUS config DIMM_SPD_SIZE int diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 70af2d2..4bf5ca4 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -5,3 +5,8 @@ select BOARD_ROMSIZE_KB_32768 select ADL_ENABLE_USB4_PCIE_RESOURCES select DRIVERS_GENESYSLOGIC_GL9755 + +config BOARD_GOOGLE_PRIMUS + bool "-> Primus" + select BOARD_GOOGLE_BASEBOARD_BRYA + select BASEBOARD_BRYA_LAPTOP diff --git a/src/mainboard/google/brya/variants/primus/include/variant/ec.h b/src/mainboard/google/brya/variants/primus/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/brya/variants/primus/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/primus/include/variant/gpio.h b/src/mainboard/google/brya/variants/primus/include/variant/gpio.h new file mode 100644 index 0000000..c4fe342 --- /dev/null +++ b/src/mainboard/google/brya/variants/primus/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/primus/memory/Makefile.inc b/src/mainboard/google/brya/variants/primus/memory/Makefile.inc new file mode 100644 index 0000000..b0ca222 --- /dev/null +++ b/src/mainboard/google/brya/variants/primus/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder.spd.hex diff --git a/src/mainboard/google/brya/variants/primus/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/primus/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/brya/variants/primus/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/brya/variants/primus/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/primus/memory/mem_parts_used.txt new file mode 100644 index 0000000..9cff262 --- /dev/null +++ b/src/mainboard/google/brya/variants/primus/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/lp4x. +# See util/spd_tools/lp4x/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb new file mode 100644 index 0000000..4f2c04a --- /dev/null +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/55129 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib59d2e506c39ea8cbd78960d4c7b301f267ac1ad Gerrit-Change-Number: 55129 Gerrit-PatchSet: 1 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: acpi/device: Add ability to generate proper _STA for PowerResource
by Lance Zhao (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Raul Rangel, Furquan Shaikh, Tim Wawrzynczak. Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55027 ) Change subject: acpi/device: Add ability to generate proper _STA for PowerResource ...................................................................... Patch Set 2: (1 comment) File src/include/acpi/acpi_device.h: https://review.coreboot.org/c/coreboot/+/55027/comment/a3dc84f2_06104d9d PS2, Line 459: : /* Write a _STA method that checks the state of the GPIOs. Otherwise : * the _STA method will always return _ON. : */ : bool enable_status; > +1 to `use_gpio_for_status` that's good, also +1. -- To view, visit https://review.coreboot.org/c/coreboot/+/55027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91410556db002c620fd9aaa99981457808da93a5 Gerrit-Change-Number: 55027 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 01 Jun 2021 23:46:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Lance Zhao Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: commonlib/lz4_wrapper.c: do not use bitfields
by Julius Werner (Code Review) 02 Jun '21

02 Jun '21

Attention is currently required from: Krystian Hebel. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55040 ) Change subject: commonlib/lz4_wrapper.c: do not use bitfields ...................................................................... Patch Set 3: Code-Review+2 (2 comments) Patchset: PS3: It's really frustrating that GCC doesn't just offer an option to control this ordering somehow, but I guess we're stuck with doing it like this. File src/commonlib/bsd/lz4_wrapper.c: https://review.coreboot.org/c/coreboot/+/55040/comment/5efeebc3_2f104d27 PS3, Line 129: lz4_block_header nit: don't think there's much of a point in having this type anymore now, could just use a raw uint32_t -- To view, visit https://review.coreboot.org/c/coreboot/+/55040 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief7d87ddb25c9baa931f27dbd54a4ca730b6ece7 Gerrit-Change-Number: 55040 Gerrit-PatchSet: 3 Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Comment-Date: Tue, 01 Jun 2021 23:18:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp_m: Enable LTR for PCIE
by Tim Wawrzynczak (Code Review) 02 Jun '21

02 Jun '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54492 ) Change subject: mb/intel/adlrvp_m: Enable LTR for PCIE ...................................................................... mb/intel/adlrvp_m: Enable LTR for PCIE BUG=none TEST=Use command $ lspci -vv LTR+ is listed on DevCtl2 Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Change-Id: If65d08a46b9e7304fbe4b92b7f1e6d4e08c599e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54492 Reviewed-by: Ryan A Albazzaz <ryan.a.albazzaz(a)intel.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/intel/adlrvp/devicetree_m.cb 1 file changed, 8 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Ryan A Albazzaz: Looks good to me, but someone else must approve diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index 9c66bd7..4e4135f 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -42,28 +42,32 @@ register "pch_pcie_rp[PCH_RP(4)]" = "{ .clk_src = 5, .clk_req = 5, - .flags = PCIE_RP_CLK_REQ_DETECT, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, + .PcieRpL1Substates = L1_SS_L1_2, }" # Enable PCH PCIE RP 5 using CLK 2 register "pch_pcie_rp[PCH_RP(5)]" = "{ .clk_src = 2, .clk_req = 2, - .flags = PCIE_RP_CLK_REQ_DETECT, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, + .PcieRpL1Substates = L1_SS_L1_2, }" # Enable PCH PCIE RP 9 using CLK 3 register "pch_pcie_rp[PCH_RP(9)]" = "{ .clk_src = 3, .clk_req = 3, - .flags = PCIE_RP_CLK_REQ_DETECT, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, + .PcieRpL1Substates = L1_SS_L1_2, }" #Enable PCH PCIE RP 10 using CLK 1 register "pch_pcie_rp[PCH_RP(10)]" = "{ .clk_src = 1, .clk_req = 1, - .flags = PCIE_RP_CLK_REQ_DETECT, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, + .PcieRpL1Substates = L1_SS_L1_2, }" # Hybrid storage mode -- To view, visit https://review.coreboot.org/c/coreboot/+/54492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If65d08a46b9e7304fbe4b92b7f1e6d4e08c599e7 Gerrit-Change-Number: 54492 Gerrit-PatchSet: 3 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Ryan A Albazzaz <ryan.a.albazzaz(a)intel.corp-partner.google.com> Gerrit-Reviewer: Ryan Albazzaz <ryan.a.albazzaz(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Enable WFC
by Tim Wawrzynczak (Code Review) 02 Jun '21

02 Jun '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52013 ) Change subject: mb/google/brya: Enable WFC ...................................................................... mb/google/brya: Enable WFC 1. Add 1 port and 1 endpoint 2. Add support for OVTI8856 WFC is on I2C0 BUG=None BRANCH=None TEST=Build and boot brya Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: Ic5e9c28f255bdf86a68ce80a4f853be4e7c7ccfe Reviewed-on: https://review.coreboot.org/c/coreboot/+/52013 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/dsdt.asl M src/mainboard/google/brya/variants/baseboard/devicetree.cb 3 files changed, 88 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 70af2d2..2a7a51c 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -5,3 +5,5 @@ select BOARD_ROMSIZE_KB_32768 select ADL_ENABLE_USB4_PCIE_RESOURCES select DRIVERS_GENESYSLOGIC_GL9755 + select DRIVERS_INTEL_MIPI_CAMERA + select SOC_INTEL_COMMON_BLOCK_IPU diff --git a/src/mainboard/google/brya/dsdt.asl b/src/mainboard/google/brya/dsdt.asl index 2bfb497..ac5b82a 100644 --- a/src/mainboard/google/brya/dsdt.asl +++ b/src/mainboard/google/brya/dsdt.asl @@ -29,7 +29,6 @@ #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/alderlake/acpi/southbridge.asl> #include <soc/intel/alderlake/acpi/tcss.asl> - #include <soc/intel/common/block/acpi/acpi/ipu.asl> } } diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index cabbeea..ddb1ece 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -95,13 +95,12 @@ #+-------------------+---------------------------+ #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| GSPI1 | Fingerprint MCU | - #| I2C0 | Audio | + #| I2C0 | Audio and WFC | #| I2C1 | Touchscreen | #| I2C2 | SAR0 | #| I2C3 | cr50 TPM. Early init is | #| | required to set up a BAR | #| | for TPM communication | - #| I2C4 | CAM | #| I2C5 | Trackpad | #+-------------------+---------------------------+ register "common_soc_config" = "{ @@ -130,7 +129,19 @@ device domain 0 on device ref igpu on end device ref dtt on end - device ref ipu on end + device ref ipu on + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + + register "cio2_num_ports" = "1" + register "cio2_lanes_used" = "{4}" # 4 CSI Camera lanes are used + register "cio2_lane_endpoint[0]" = ""^I2C0.CAM0"" + register "cio2_prt[0]" = "2" + device generic 0 on end + end + end device ref tbt_pcie_rp0 on end device ref tbt_pcie_rp1 on end device ref tbt_pcie_rp2 on end @@ -145,6 +156,78 @@ device generic 0 on end end end + + device ref i2c0 on + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI8856"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 8856 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "4" + register "ssdb.link_used" = "0" + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM0"" + register "num_freq_entries" = "2" + register "link_freq[0]" = "360 * MHz" # 360 MHz + register "link_freq[1]" = "180 * MHz" # 180 MHz + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3" + register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" #power_enable_2p8 + register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" #power_enable_1p2 + register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" #reset + + #_ON + register "on_seq.ops_cnt" = "5" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" + register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + + #_OFF + register "off_seq.ops_cnt" = "4" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 10 on end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "2" + register "acpi_name" = ""VCM0"" + register "chip_name" = ""DW9768 VCM"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "pr0" = ""\\_SB.PCI0.I2C0.CAM0.PRIC"" + register "vcm_compat" = ""dongwoon,dw9768"" + + device i2c 0C on end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "1" + register "acpi_name" = ""NVM0"" + register "chip_name" = ""AT24 EEPROM"" + register "device_type" = "INTEL_ACPI_CAMERA_NVM" + + register "pr0" = ""\\_SB.PCI0.I2C0.CAM0.PRIC"" + register "nvm_compat" = ""atmel,24c1024"" + + register "nvm_size" = "0x2800" + register "nvm_pagesize" = "0x01" + register "nvm_readonly" = "0x01" + register "nvm_width" = "0x0E" + + device i2c 58 on end + end + end #I2C0 device ref i2c3 on chip drivers/i2c/tpm register "hid" = ""GOOG0005"" -- To view, visit https://review.coreboot.org/c/coreboot/+/52013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5e9c28f255bdf86a68ce80a4f853be4e7c7ccfe Gerrit-Change-Number: 52013 Gerrit-PatchSet: 10 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Shobhit Srivastava <shobhit.srivastava(a)intel.com> Gerrit-CC: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: merged

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coreboot-gerrit June 2021