coreboot-gerrit June 2021

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Change in coreboot[master]: soc/mainboard: Add labtop series
by Star Labs (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Star Labs, Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52798 to look at the new patch set (#27). Change subject: soc/mainboard: Add labtop series ...................................................................... soc/mainboard: Add labtop series Add support for LabTop Mk III (kblr) and LabTop Mk IV (cml) Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I37c74d03d86fb124ed96e45d1bf137eb2ec57251 --- M Documentation/distributions.md M Documentation/mainboard/index.md A src/mainboard/starlabs/Kconfig A src/mainboard/starlabs/Kconfig.name A src/mainboard/starlabs/labtop/Kconfig A src/mainboard/starlabs/labtop/Kconfig.name A src/mainboard/starlabs/labtop/Makefile.inc A src/mainboard/starlabs/labtop/acpi/ec.asl A src/mainboard/starlabs/labtop/acpi/mainboard.asl A src/mainboard/starlabs/labtop/acpi/sleep.asl A src/mainboard/starlabs/labtop/acpi/superio.asl A src/mainboard/starlabs/labtop/board_info.txt A src/mainboard/starlabs/labtop/bootblock.c A src/mainboard/starlabs/labtop/cmos.default A src/mainboard/starlabs/labtop/cmos.layout A src/mainboard/starlabs/labtop/dsdt.asl A src/mainboard/starlabs/labtop/hda_verb.c A src/mainboard/starlabs/labtop/mainboard.c A src/mainboard/starlabs/labtop/ramstage.c A src/mainboard/starlabs/labtop/spd/Makefile.inc A src/mainboard/starlabs/labtop/spd/empty_ddr4.spd.hex A src/mainboard/starlabs/labtop/spd/gskill-F4-3200C22S.hex A src/mainboard/starlabs/labtop/spd/micron-MT40A1G16KD-062E-E.spd.hex A src/mainboard/starlabs/labtop/spd/micron_dimm_MT40A1G16KD-062EE.spd.hex A src/mainboard/starlabs/labtop/spd/samsung-K4A8G165WB-BCRC.spd.hex A src/mainboard/starlabs/labtop/spd/spd.h A src/mainboard/starlabs/labtop/spd/spd_util.c A src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/memory.h A src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/romstage.h A src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/variants.h A src/mainboard/starlabs/labtop/variants/cml/Makefile.inc A src/mainboard/starlabs/labtop/variants/cml/board.fmd A src/mainboard/starlabs/labtop/variants/cml/data.vbt A src/mainboard/starlabs/labtop/variants/cml/devicetree.cb A src/mainboard/starlabs/labtop/variants/cml/gma-mainboard.ads A src/mainboard/starlabs/labtop/variants/cml/include/variant/gpio.h A src/mainboard/starlabs/labtop/variants/cml/include/variant/hda_verb.h A src/mainboard/starlabs/labtop/variants/cml/romstage.c A src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc A src/mainboard/starlabs/labtop/variants/kbl/board.fmd A src/mainboard/starlabs/labtop/variants/kbl/data.vbt A src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb A src/mainboard/starlabs/labtop/variants/kbl/gma-mainboard.ads A src/mainboard/starlabs/labtop/variants/kbl/include/variant/gpio.h A src/mainboard/starlabs/labtop/variants/kbl/include/variant/hda_verb.h A src/mainboard/starlabs/labtop/variants/kbl/romstage.c 46 files changed, 2,084 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/52798/27 -- To view, visit https://review.coreboot.org/c/coreboot/+/52798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37c74d03d86fb124ed96e45d1bf137eb2ec57251 Gerrit-Change-Number: 52798 Gerrit-PatchSet: 27 Gerrit-Owner: Star Labs <admin(a)starlabs.systems> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Star Labs <admin(a)starlabs.systems> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/cezanne/include/iomap: properly align defines
by Felix Held (Code Review) 01 Jun '21

01 Jun '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55100 ) Change subject: soc/amd/cezanne/include/iomap: properly align defines ...................................................................... soc/amd/cezanne/include/iomap: properly align defines Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I14647b3d88146602b96fc1dff2347a293bab0c26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55100 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/cezanne/include/soc/iomap.h 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h index 486e3cf..4c4252a 100644 --- a/src/soc/amd/cezanne/include/soc/iomap.h +++ b/src/soc/amd/cezanne/include/soc/iomap.h @@ -45,7 +45,7 @@ /* I/O Ranges */ #define NCP_ERR 0x00f0 -#define ACPI_IO_BASE 0x0400 +#define ACPI_IO_BASE 0x0400 #define ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00) #define ACPI_PM1_STS (ACPI_PM_EVT_BLK + 0x00) #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) -- To view, visit https://review.coreboot.org/c/coreboot/+/55100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14647b3d88146602b96fc1dff2347a293bab0c26 Gerrit-Change-Number: 55100 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mainboard: Add labtop series
by Star Labs (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Star Labs, Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52798 to look at the new patch set (#26). Change subject: soc/mainboard: Add labtop series ...................................................................... soc/mainboard: Add labtop series Add support for LabTop Mk III (kblr) and LabTop Mk IV (cml) Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I37c74d03d86fb124ed96e45d1bf137eb2ec57251 --- D Documentation/distributions.md D Documentation/mainboard/index.md A src/mainboard/starlabs/Kconfig A src/mainboard/starlabs/Kconfig.name A src/mainboard/starlabs/labtop/Kconfig A src/mainboard/starlabs/labtop/Kconfig.name A src/mainboard/starlabs/labtop/Makefile.inc A src/mainboard/starlabs/labtop/acpi/ec.asl A src/mainboard/starlabs/labtop/acpi/mainboard.asl A src/mainboard/starlabs/labtop/acpi/sleep.asl A src/mainboard/starlabs/labtop/acpi/superio.asl A src/mainboard/starlabs/labtop/board_info.txt A src/mainboard/starlabs/labtop/bootblock.c A src/mainboard/starlabs/labtop/cmos.default A src/mainboard/starlabs/labtop/cmos.layout A src/mainboard/starlabs/labtop/dsdt.asl A src/mainboard/starlabs/labtop/hda_verb.c A src/mainboard/starlabs/labtop/mainboard.c A src/mainboard/starlabs/labtop/ramstage.c A src/mainboard/starlabs/labtop/spd/Makefile.inc A src/mainboard/starlabs/labtop/spd/empty_ddr4.spd.hex A src/mainboard/starlabs/labtop/spd/gskill-F4-3200C22S.hex A src/mainboard/starlabs/labtop/spd/micron-MT40A1G16KD-062E-E.spd.hex A src/mainboard/starlabs/labtop/spd/micron_dimm_MT40A1G16KD-062EE.spd.hex A src/mainboard/starlabs/labtop/spd/samsung-K4A8G165WB-BCRC.spd.hex A src/mainboard/starlabs/labtop/spd/spd.h A src/mainboard/starlabs/labtop/spd/spd_util.c A src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/memory.h A src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/romstage.h A src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/variants.h A src/mainboard/starlabs/labtop/variants/cml/Makefile.inc A src/mainboard/starlabs/labtop/variants/cml/board.fmd A src/mainboard/starlabs/labtop/variants/cml/data.vbt A src/mainboard/starlabs/labtop/variants/cml/devicetree.cb A src/mainboard/starlabs/labtop/variants/cml/gma-mainboard.ads A src/mainboard/starlabs/labtop/variants/cml/include/variant/gpio.h A src/mainboard/starlabs/labtop/variants/cml/include/variant/hda_verb.h A src/mainboard/starlabs/labtop/variants/cml/romstage.c A src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc A src/mainboard/starlabs/labtop/variants/kbl/board.fmd A src/mainboard/starlabs/labtop/variants/kbl/data.vbt A src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb A src/mainboard/starlabs/labtop/variants/kbl/gma-mainboard.ads A src/mainboard/starlabs/labtop/variants/kbl/include/variant/gpio.h A src/mainboard/starlabs/labtop/variants/kbl/include/variant/hda_verb.h A src/mainboard/starlabs/labtop/variants/kbl/romstage.c 46 files changed, 2,055 insertions(+), 271 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/52798/26 -- To view, visit https://review.coreboot.org/c/coreboot/+/52798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37c74d03d86fb124ed96e45d1bf137eb2ec57251 Gerrit-Change-Number: 52798 Gerrit-PatchSet: 26 Gerrit-Owner: Star Labs <admin(a)starlabs.systems> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Star Labs <admin(a)starlabs.systems> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/sm: Enable TCSS
by Tim Wawrzynczak (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Deepti Deshatty, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54091 ) Change subject: mb/intel/sm: Enable TCSS ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8be796295a900bed58b5c7ed6c2300fe504d58a3 Gerrit-Change-Number: 54091 Gerrit-PatchSet: 10 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 01 Jun 2021 20:52:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Enable TCSS
by Tim Wawrzynczak (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Deepti Deshatty. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54090 ) Change subject: mb/google/brya: Enable TCSS ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3cb8b8836b17fa00ab0089d03fca9f22c4d702e Gerrit-Change-Number: 54090 Gerrit-PatchSet: 10 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Comment-Date: Tue, 01 Jun 2021 20:51:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer:intel/common/block: Move mainboard api to tcss comm...
by Tim Wawrzynczak (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Furquan Shaikh, Paul Menzel, Sridhar Siricilla, Deepti Deshatty, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54733 ) Change subject: mb/google/volteer:intel/common/block: Move mainboard api to tcss common block ...................................................................... Patch Set 5: (3 comments) File src/soc/intel/common/block/tcss/tcss.c: https://review.coreboot.org/c/coreboot/+/54733/comment/bebbfd8d_03b81bf4 PS5, Line 342: const struct device *get_pmc_mux(void) : { : const struct device *pmc; : const struct device *mux; : : pmc = pcidev_path_on_root(PCH_DEVFN_PMC); : if (!pmc || !pmc->link_list) { : printk(BIOS_ERR, "%s: unable to find PMC device or its mux\n", __func__); : return NULL; : } : : mux = pmc->link_list->children; : return mux; : } This function isn't required, it can be rolled up into the call to `find_dev_nested_path` below https://review.coreboot.org/c/coreboot/+/54733/comment/e1ce582a_9f8227e5 PS5, Line 361: : const struct device *mux = get_pmc_mux(); : : if (!mux || !mux->link_list) { : printk(BIOS_ERR, "%s: unable to find PMC mux device or its connector\n", : __func__); : return NULL; : } same as above, this won't be required https://review.coreboot.org/c/coreboot/+/54733/comment/892e5e25_8eb3ca25 PS5, Line 372: const struct device_path conn_path[] = { : {.type = DEVICE_PATH_GENERIC, .generic.id = port, .generic.subid = 0}, : }; : const struct device *conn = find_dev_nested_path(mux->link_list, conn_path, : ARRAY_SIZE(conn_path)); You can get rid of the two above sections and just add the PMC device into this list here: ``` const struct device_path conn_path[] = { {.type = DEVICE_PATH_PCI, .pci.devfn = PCH_DEVFN_PMC }, {.type = DEVICE_PATH_GENERIC, .generic.id = port, .generic.subid = 0}}; const struct device *conn = find_dev_nested_path(pci_root_bus(), conn_path, ARRAY_SIZE(conn_path)); ``` find_dev_nested_path will then find the PMC device and search its children for the connector with the given port -- To view, visit https://review.coreboot.org/c/coreboot/+/54733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7894363df4862f7cfe733d93e6160677fb8a9e31 Gerrit-Change-Number: 54733 Gerrit-PatchSet: 5 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 01 Jun 2021 20:51:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mainboards using soc/amd/picasso: use aliases for remaining PCIe devices
by Felix Held (Code Review) 01 Jun '21

01 Jun '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55104 ) Change subject: mainboards using soc/amd/picasso: use aliases for remaining PCIe devices ...................................................................... mainboards using soc/amd/picasso: use aliases for remaining PCIe devices Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Id2bdce5871f57e9edb17f89cba61b5c5ae018566 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55104 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/mainboard/amd/bilby/devicetree.cb M src/mainboard/amd/mandolin/variants/cereme/devicetree.cb M src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb M src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb M src/mainboard/google/zork/variants/vilboz/overridetree.cb 6 files changed, 49 insertions(+), 49 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/amd/bilby/devicetree.cb b/src/mainboard/amd/bilby/devicetree.cb index 10a5d2e..932d280 100644 --- a/src/mainboard/amd/bilby/devicetree.cb +++ b/src/mainboard/amd/bilby/devicetree.cb @@ -145,19 +145,19 @@ device ref gpp_bridge_1 on end device ref gpp_bridge_4 on end # NVMe device ref internal_bridge_a on - device pci 0.0 on end # Internal GPU - device pci 0.1 on end # Display HDA - device pci 0.2 on end # Crypto Coprocessor - device pci 0.3 on end # USB 3.1 - device pci 0.4 off end # USB 3.1 - device pci 0.5 on end # Audio - device pci 0.6 on end # HDA - device pci 0.7 on end # non-Sensor Fusion Hub device + device ref gfx on end # Internal GPU + device ref gfx_hda on end # Display HDA + device ref crypto on end # Crypto Coprocessor + device ref xhci_0 on end # USB 3.1 + device ref xhci_1 off end # USB 3.1 + device ref acp on end # Audio + device ref hda on end # HDA + device ref mp2 on end # non-Sensor Fusion Hub device end device ref internal_bridge_b on - device pci 0.0 off end # AHCI - device pci 0.1 off end # integrated Ethernet MAC - device pci 0.2 off end # integrated Ethernet MAC + device ref sata off end # AHCI + device ref xgbe_0 off end # integrated Ethernet MAC + device ref xgbe_1 off end # integrated Ethernet MAC end device ref lpc_bridge on chip superio/smsc/sio1036 # optional debug card diff --git a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb index 9b21895..6a1a3bc 100644 --- a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb @@ -143,19 +143,19 @@ device ref iommu on end device ref gpp_bridge_0 on end # Bridge to PCIe Ethernet chip device ref internal_bridge_a on - device pci 0.0 on end # Internal GPU - device pci 0.1 on end # Display HDA - device pci 0.2 on end # Crypto Coprocessor - device pci 0.3 on end # USB 3.1 - device pci 0.4 off end # USB 3.1 - device pci 0.5 on end # Audio - device pci 0.6 on end # HDA - device pci 0.7 on end # non-Sensor Fusion Hub device + device ref gfx on end # Internal GPU + device ref gfx_hda on end # Display HDA + device ref crypto on end # Crypto Coprocessor + device ref xhci_0 on end # USB 3.1 + device ref xhci_1 off end # USB 3.1 + device ref acp on end # Audio + device ref hda on end # HDA + device ref mp2 on end # non-Sensor Fusion Hub device end device ref internal_bridge_b on - device pci 0.0 off end # AHCI - device pci 0.1 off end # integrated Ethernet MAC - device pci 0.2 off end # integrated Ethernet MAC + device ref sata off end # AHCI + device ref xgbe_0 off end # integrated Ethernet MAC + device ref xgbe_1 off end # integrated Ethernet MAC end device ref lpc_bridge on chip superio/smsc/sio1036 # optional debug card diff --git a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb index fef625f..a12d318 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb @@ -143,19 +143,19 @@ device ref iommu on end device ref gpp_bridge_2 on end # Bridge to PCIe Ethernet chip device ref internal_bridge_a on - device pci 0.0 on end # Internal GPU - device pci 0.1 on end # Display HDA - device pci 0.2 on end # Crypto Coprocessor - device pci 0.3 on end # USB 3.1 - device pci 0.4 on end # USB 3.1 - device pci 0.5 on end # Audio - device pci 0.6 on end # HDA - device pci 0.7 on end # non-Sensor Fusion Hub device + device ref gfx on end # Internal GPU + device ref gfx_hda on end # Display HDA + device ref crypto on end # Crypto Coprocessor + device ref xhci_0 on end # USB 3.1 + device ref xhci_1 on end # USB 3.1 + device ref acp on end # Audio + device ref hda on end # HDA + device ref mp2 on end # non-Sensor Fusion Hub device end device ref internal_bridge_b on - device pci 0.0 on end # AHCI - device pci 0.1 off end # integrated Ethernet MAC - device pci 0.2 off end # integrated Ethernet MAC + device ref sata on end # AHCI + device ref xgbe_0 off end # integrated Ethernet MAC + device ref xgbe_1 off end # integrated Ethernet MAC end device ref lpc_bridge on chip superio/smsc/sio1036 # optional debug card diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 57710c2..f3ad329 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -264,10 +264,10 @@ end device ref gpp_bridge_2 on end # SD device ref internal_bridge_a on - device pci 0.0 on end # Internal GPU - device pci 0.1 on end # Display HDA - device pci 0.2 on end # Crypto Coprocessor - device pci 0.3 on # USB 3.1 + device ref gfx on end # Internal GPU + device ref gfx_hda on end # Display HDA + device ref crypto on end # Crypto Coprocessor + device ref xhci_0 on # USB 3.1 chip drivers/usb/acpi register "desc" = ""Root Hub"" register "type" = "UPC_TYPE_HUB" @@ -334,7 +334,7 @@ end end end - device pci 0.5 on + device ref acp on chip drivers/amd/i2s_machine_dev register "hid" = ""AMDI5682"" # DMIC select GPIO for ACP machine device @@ -350,8 +350,8 @@ device generic 0.0 on end end end # Audio - device pci 0.6 off end # HDA - device pci 0.7 on end # non-Sensor Fusion Hub device + device ref hda off end # HDA + device ref mp2 on end # non-Sensor Fusion Hub device end device ref lpc_bridge on chip ec/google/chromeec diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 1ddc763..364458b2 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -258,10 +258,10 @@ device ref gpp_bridge_2 on end # SD device ref gpp_bridge_6 on end # NVME device ref internal_bridge_a on - device pci 0.0 on end # Internal GPU - device pci 0.1 on end # Display HDA - device pci 0.2 on end # Crypto Coprocessor - device pci 0.3 on # USB 3.1 + device ref gfx on end # Internal GPU + device ref gfx_hda on end # Display HDA + device ref crypto on end # Crypto Coprocessor + device ref xhci_0 on # USB 3.1 chip drivers/usb/acpi register "desc" = ""Root Hub"" register "type" = "UPC_TYPE_HUB" @@ -330,7 +330,7 @@ end end end - device pci 0.4 on # USB 3.1 + device ref xhci_1 on # USB 3.1 chip drivers/usb/acpi # The following devices are only enabled on Picasso SKUs register "desc" = ""Root Hub"" @@ -355,7 +355,7 @@ end end end - device pci 0.5 on + device ref acp on chip drivers/amd/i2s_machine_dev register "hid" = ""AMDI5682"" # DMIC select GPIO for ACP machine device @@ -371,8 +371,8 @@ device generic 0.0 on end end end # Audio - device pci 0.6 off end # HDA - device pci 0.7 on end # non-Sensor Fusion Hub device + device ref hda off end # HDA + device ref mp2 on end # non-Sensor Fusion Hub device end device ref lpc_bridge on chip ec/google/chromeec diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index 7cadaf8..5469b32 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -159,7 +159,7 @@ end end # SD device ref internal_bridge_a on - device pci 0.5 on + device ref acp on chip drivers/amd/i2s_machine_dev register "hid" = ""AMDI1015"" # DMIC select GPIO for ACP machine device -- To view, visit https://review.coreboot.org/c/coreboot/+/55104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2bdce5871f57e9edb17f89cba61b5c5ae018566 Gerrit-Change-Number: 55104 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mainboards using soc/amd/picasso: use aliases for PCIe devices on bus 0
by Felix Held (Code Review) 01 Jun '21

01 Jun '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55103 ) Change subject: mainboards using soc/amd/picasso: use aliases for PCIe devices on bus 0 ...................................................................... mainboards using soc/amd/picasso: use aliases for PCIe devices on bus 0 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ia6199c70163d32467abe5ba5da55c73ff62ba10f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55103 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/mainboard/amd/bilby/devicetree.cb M src/mainboard/amd/mandolin/variants/cereme/devicetree.cb M src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb M src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb M src/mainboard/google/zork/variants/vilboz/overridetree.cb M util/mainboard/google/trembyle/template/overridetree.cb 7 files changed, 33 insertions(+), 33 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/amd/bilby/devicetree.cb b/src/mainboard/amd/bilby/devicetree.cb index 7015185..10a5d2e 100644 --- a/src/mainboard/amd/bilby/devicetree.cb +++ b/src/mainboard/amd/bilby/devicetree.cb @@ -140,11 +140,11 @@ device domain 0 on subsystemid 0x1022 0x1510 inherit - device pci 0.2 on end # IOMMU - device pci 1.1 on end # GPP Bridge 0 - device pci 1.2 on end # GPP Bridge 1 - device pci 1.5 on end # NVMe - device pci 8.1 on # Bridge to Bus A + device ref iommu on end + device ref gpp_bridge_0 on end + device ref gpp_bridge_1 on end + device ref gpp_bridge_4 on end # NVMe + device ref internal_bridge_a on device pci 0.0 on end # Internal GPU device pci 0.1 on end # Display HDA device pci 0.2 on end # Crypto Coprocessor @@ -154,12 +154,12 @@ device pci 0.6 on end # HDA device pci 0.7 on end # non-Sensor Fusion Hub device end - device pci 8.2 on # Bridge to Bus B + device ref internal_bridge_b on device pci 0.0 off end # AHCI device pci 0.1 off end # integrated Ethernet MAC device pci 0.2 off end # integrated Ethernet MAC end - device pci 14.3 on # D14F3 bridge + device ref lpc_bridge on chip superio/smsc/sio1036 # optional debug card end end diff --git a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb index d1e0241..9b21895 100644 --- a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb @@ -140,9 +140,9 @@ device domain 0 on subsystemid 0x1022 0x1510 inherit - device pci 0.2 on end # IOMMU - device pci 1.1 on end # Bridge to PCIe Ethernet chip - device pci 8.1 on # Bridge to Bus A + device ref iommu on end + device ref gpp_bridge_0 on end # Bridge to PCIe Ethernet chip + device ref internal_bridge_a on device pci 0.0 on end # Internal GPU device pci 0.1 on end # Display HDA device pci 0.2 on end # Crypto Coprocessor @@ -152,12 +152,12 @@ device pci 0.6 on end # HDA device pci 0.7 on end # non-Sensor Fusion Hub device end - device pci 8.2 on # Bridge to Bus B + device ref internal_bridge_b on device pci 0.0 off end # AHCI device pci 0.1 off end # integrated Ethernet MAC device pci 0.2 off end # integrated Ethernet MAC end - device pci 14.3 on # D14F3 bridge + device ref lpc_bridge on chip superio/smsc/sio1036 # optional debug card end end diff --git a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb index 1c20095..fef625f 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb @@ -140,9 +140,9 @@ device domain 0 on subsystemid 0x1022 0x1510 inherit - device pci 0.2 on end # IOMMU - device pci 1.3 on end # Bridge to PCIe Ethernet chip - device pci 8.1 on # Bridge to Bus A + device ref iommu on end + device ref gpp_bridge_2 on end # Bridge to PCIe Ethernet chip + device ref internal_bridge_a on device pci 0.0 on end # Internal GPU device pci 0.1 on end # Display HDA device pci 0.2 on end # Crypto Coprocessor @@ -152,12 +152,12 @@ device pci 0.6 on end # HDA device pci 0.7 on end # non-Sensor Fusion Hub device end - device pci 8.2 on # Bridge to Bus B + device ref internal_bridge_b on device pci 0.0 on end # AHCI device pci 0.1 off end # integrated Ethernet MAC device pci 0.2 off end # integrated Ethernet MAC end - device pci 14.3 on # D14F3 bridge + device ref lpc_bridge on chip superio/smsc/sio1036 # optional debug card end end diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 0d0e829..57710c2 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -255,15 +255,15 @@ # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit - device pci 0.2 on end # IOMMU - device pci 1.2 on # GPP Bridge 1 - Wifi + device ref iommu on end + device ref gpp_bridge_1 on # Wifi chip drivers/wifi/generic register "wake" = "GEVENT_8" device pci 00.0 on end end end - device pci 1.3 on end # GPP Bridge 2 - SD - device pci 8.1 on # Internal GPP Bridge 0 to Bus A + device ref gpp_bridge_2 on end # SD + device ref internal_bridge_a on device pci 0.0 on end # Internal GPU device pci 0.1 on end # Display HDA device pci 0.2 on end # Crypto Coprocessor @@ -353,7 +353,7 @@ device pci 0.6 off end # HDA device pci 0.7 on end # non-Sensor Fusion Hub device end - device pci 14.3 on # - D14F3 bridge + device ref lpc_bridge on chip ec/google/chromeec device pnp 0c09.0 on chip ec/google/chromeec/i2c_tunnel diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 8d0abad..1ddc763 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -248,16 +248,16 @@ # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit - device pci 0.2 on end # IOMMU - device pci 1.2 on # GPP Bridge 1 - Wifi + device ref iommu on end + device ref gpp_bridge_1 on # Wifi chip drivers/wifi/generic register "wake" = "GEVENT_8" device pci 00.0 on end end end - device pci 1.3 on end # GPP Bridge 2 - SD - device pci 1.7 on end # GPP Bridge 6 - NVME - device pci 8.1 on # Internal GPP Bridge 0 to Bus A + device ref gpp_bridge_2 on end # SD + device ref gpp_bridge_6 on end # NVME + device ref internal_bridge_a on device pci 0.0 on end # Internal GPU device pci 0.1 on end # Display HDA device pci 0.2 on end # Crypto Coprocessor @@ -374,7 +374,7 @@ device pci 0.6 off end # HDA device pci 0.7 on end # non-Sensor Fusion Hub device end - device pci 14.3 on # - D14F3 bridge + device ref lpc_bridge on chip ec/google/chromeec device pnp 0c09.0 on chip ec/google/chromeec/i2c_tunnel diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index 43a64b0d..7cadaf8 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -152,13 +152,13 @@ # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit - device pci 1.3 on + device ref gpp_bridge_2 on chip drivers/generic/bayhub_lv2 register "enable_power_saving" = "1" device pci 00.0 on end end - end # GPP Bridge 2 - SD - device pci 8.1 on + end # SD + device ref internal_bridge_a on device pci 0.5 on chip drivers/amd/i2s_machine_dev register "hid" = ""AMDI1015"" @@ -200,7 +200,7 @@ end end # Audio end - device pci 14.3 on # - D14F3 bridge + device ref lpc_bridge on chip ec/google/chromeec device pnp 0c09.0 on chip ec/google/chromeec/i2c_tunnel diff --git a/util/mainboard/google/trembyle/template/overridetree.cb b/util/mainboard/google/trembyle/template/overridetree.cb index d09c942..52607d1 100644 --- a/util/mainboard/google/trembyle/template/overridetree.cb +++ b/util/mainboard/google/trembyle/template/overridetree.cb @@ -37,7 +37,7 @@ # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit - device pci 1.7 on end # GPP Bridge 6 - NVME + device ref gpp_bridge_6 on end # NVME end # domain device mmio 0xfedc4000 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/55103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6199c70163d32467abe5ba5da55c73ff62ba10f Gerrit-Change-Number: 55103 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/amd/picasso: introduce and use chipset device tree
by Felix Held (Code Review) 01 Jun '21

01 Jun '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50626 ) Change subject: soc/amd/picasso: introduce and use chipset device tree ...................................................................... soc/amd/picasso: introduce and use chipset device tree The chipset devicetree only has the essential PCIe devices enabled that are needed for the SoC code to work. It also defines aliases for all PCIe devices that can be used to reference the devices in the mainboard- specific devicetrees and devicetree overrides. To make the change easier to review that part will be done in a follow-up patch. Despite missing in the PPR, device pci 18.7 exists on Picasso. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I6b7c3fd32579a23539594672593a243172c161c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50626 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/mainboard/amd/bilby/devicetree.cb M src/mainboard/amd/mandolin/variants/cereme/devicetree.cb M src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb M src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb M src/soc/amd/picasso/Kconfig A src/soc/amd/picasso/chipset.cb M util/mainboard/google/trembyle/template/overridetree.cb 8 files changed, 50 insertions(+), 94 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/amd/bilby/devicetree.cb b/src/mainboard/amd/bilby/devicetree.cb index 8adbaa2..7015185 100644 --- a/src/mainboard/amd/bilby/devicetree.cb +++ b/src/mainboard/amd/bilby/devicetree.cb @@ -138,18 +138,12 @@ register "pspp_policy" = "DXIO_PSPP_BALANCED" - device cpu_cluster 0 on - device lapic 0 on end - end device domain 0 on subsystemid 0x1022 0x1510 inherit - device pci 0.0 on end # Root Complex device pci 0.2 on end # IOMMU - device pci 1.0 on end # Dummy Host Bridge device pci 1.1 on end # GPP Bridge 0 device pci 1.2 on end # GPP Bridge 1 device pci 1.5 on end # NVMe - device pci 8.0 on end # Dummy Host Bridge device pci 8.1 on # Bridge to Bus A device pci 0.0 on end # Internal GPU device pci 0.1 on end # Display HDA @@ -165,20 +159,10 @@ device pci 0.1 off end # integrated Ethernet MAC device pci 0.2 off end # integrated Ethernet MAC end - device pci 14.0 on end # SMBus device pci 14.3 on # D14F3 bridge chip superio/smsc/sio1036 # optional debug card end end - device pci 14.6 off end # SDHCI - device pci 18.0 on end # Data fabric [0-7] - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - device pci 18.6 on end - device pci 18.7 on end end # domain device mmio 0xfedc9000 on end # UART0 diff --git a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb index f82f958..d1e0241 100644 --- a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb @@ -138,16 +138,10 @@ register "pspp_policy" = "DXIO_PSPP_BALANCED" - device cpu_cluster 0 on - device lapic 0 on end - end device domain 0 on subsystemid 0x1022 0x1510 inherit - device pci 0.0 on end # Root Complex device pci 0.2 on end # IOMMU - device pci 1.0 on end # Dummy Host Bridge device pci 1.1 on end # Bridge to PCIe Ethernet chip - device pci 8.0 on end # Dummy Host Bridge device pci 8.1 on # Bridge to Bus A device pci 0.0 on end # Internal GPU device pci 0.1 on end # Display HDA @@ -163,20 +157,10 @@ device pci 0.1 off end # integrated Ethernet MAC device pci 0.2 off end # integrated Ethernet MAC end - device pci 14.0 on end # SMBus device pci 14.3 on # D14F3 bridge chip superio/smsc/sio1036 # optional debug card end end - device pci 14.6 off end # SDHCI - device pci 18.0 on end # Data fabric [0-7] - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - device pci 18.6 on end - device pci 18.7 on end end # domain device mmio 0xfedc9000 on end # UART0 diff --git a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb index c82f388..1c20095 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb @@ -138,16 +138,10 @@ register "pspp_policy" = "DXIO_PSPP_BALANCED" - device cpu_cluster 0 on - device lapic 0 on end - end device domain 0 on subsystemid 0x1022 0x1510 inherit - device pci 0.0 on end # Root Complex device pci 0.2 on end # IOMMU - device pci 1.0 on end # Dummy Host Bridge device pci 1.3 on end # Bridge to PCIe Ethernet chip - device pci 8.0 on end # Dummy Host Bridge device pci 8.1 on # Bridge to Bus A device pci 0.0 on end # Internal GPU device pci 0.1 on end # Display HDA @@ -163,20 +157,10 @@ device pci 0.1 off end # integrated Ethernet MAC device pci 0.2 off end # integrated Ethernet MAC end - device pci 14.0 on end # SMBus device pci 14.3 on # D14F3 bridge chip superio/smsc/sio1036 # optional debug card end end - device pci 14.6 off end # SDHCI - device pci 18.0 on end # Data fabric [0-7] - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - device pci 18.6 on end - device pci 18.7 on end end # domain device mmio 0xfedc9000 on end # UART0 diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 2525400..0d0e829 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -252,17 +252,10 @@ register "pspp_policy" = "DXIO_PSPP_POWERSAVE" - device cpu_cluster 0 on - device lapic 0 on end - end - # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit - device pci 0.0 on end # Root Complex device pci 0.2 on end # IOMMU - device pci 1.0 on end # Dummy Host Bridge, must be enabled - device pci 1.1 off end # GPP Bridge 0 device pci 1.2 on # GPP Bridge 1 - Wifi chip drivers/wifi/generic register "wake" = "GEVENT_8" @@ -270,9 +263,6 @@ end end device pci 1.3 on end # GPP Bridge 2 - SD - device pci 1.4 off end # GPP Bridge 3 - device pci 1.5 off end # GPP Bridge 4 - device pci 8.0 on end # Dummy Host Bridge, must be enabled device pci 8.1 on # Internal GPP Bridge 0 to Bus A device pci 0.0 on end # Internal GPU device pci 0.1 on end # Display HDA @@ -363,10 +353,6 @@ device pci 0.6 off end # HDA device pci 0.7 on end # non-Sensor Fusion Hub device end - device pci 8.2 off # Internal GPP Bridge 0 to Bus B - device pci 0.0 off end # AHCI - end - device pci 14.0 on end # SM device pci 14.3 on # - D14F3 bridge chip ec/google/chromeec device pnp 0c09.0 on @@ -398,13 +384,6 @@ end end end - device pci 18.0 on end # Data fabric [0-7] - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - device pci 18.6 on end end # domain device mmio 0xfedc5000 on diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 89bca93..8d0abad 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -245,17 +245,10 @@ register "pspp_policy" = "DXIO_PSPP_POWERSAVE" - device cpu_cluster 0 on - device lapic 0 on end - end - # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit - device pci 0.0 on end # Root Complex device pci 0.2 on end # IOMMU - device pci 1.0 on end # Dummy Host Bridge, must be enabled - device pci 1.1 off end # GPP Bridge 0 device pci 1.2 on # GPP Bridge 1 - Wifi chip drivers/wifi/generic register "wake" = "GEVENT_8" @@ -263,11 +256,7 @@ end end device pci 1.3 on end # GPP Bridge 2 - SD - device pci 1.4 off end # GPP Bridge 3 - device pci 1.5 off end # GPP Bridge 4 - device pci 1.6 off end # GPP Bridge 5 device pci 1.7 on end # GPP Bridge 6 - NVME - device pci 8.0 on end # Dummy Host Bridge, must be enabled device pci 8.1 on # Internal GPP Bridge 0 to Bus A device pci 0.0 on end # Internal GPU device pci 0.1 on end # Display HDA @@ -385,10 +374,6 @@ device pci 0.6 off end # HDA device pci 0.7 on end # non-Sensor Fusion Hub device end - device pci 8.2 off # Internal GPP Bridge 0 to Bus B - device pci 0.0 off end # AHCI - end - device pci 14.0 on end # SM device pci 14.3 on # - D14F3 bridge chip ec/google/chromeec device pnp 0c09.0 on @@ -434,14 +419,6 @@ end end end - device pci 14.6 off end # Non-Functional SDHCI - device pci 18.0 on end # Data fabric [0-7] - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - device pci 18.6 on end end # domain chip drivers/generic/max98357a diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 4bfd093..e9ed845 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -71,6 +71,10 @@ config SOC_AMD_COMMON_BLOCK_UCODE_SIZE default 3200 +config CHIPSET_DEVICETREE + string + default "soc/amd/picasso/chipset.cb" + config FSP_M_FILE string "FSP-M (memory init) binary path and filename" depends on ADD_FSP_BINARIES diff --git a/src/soc/amd/picasso/chipset.cb b/src/soc/amd/picasso/chipset.cb new file mode 100644 index 0000000..906b18d --- /dev/null +++ b/src/soc/amd/picasso/chipset.cb @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/amd/picasso + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 alias gnb on end + device pci 00.2 alias iommu off end + device pci 01.0 on end # Dummy Host Bridge, do not disable + device pci 01.1 alias gpp_bridge_0 off end + device pci 01.2 alias gpp_bridge_1 off end + device pci 01.3 alias gpp_bridge_2 off end + device pci 01.4 alias gpp_bridge_3 off end + device pci 01.5 alias gpp_bridge_4 off end + device pci 01.6 alias gpp_bridge_5 off end + device pci 01.7 alias gpp_bridge_6 off end + device pci 08.0 on end # Dummy Host Bridge, do not disable + device pci 08.1 alias internal_bridge_a off # internal bridge to bus A + device pci 0.0 alias gfx off end # internal GPU + device pci 0.1 alias gfx_hda off end # display HD Audio controller + device pci 0.2 alias crypto off end # cryptography coprocessor + device pci 0.3 alias xhci_0 off end + device pci 0.4 alias xhci_1 off end + device pci 0.5 alias acp off end # audio co-processor + device pci 0.6 alias hda off end # main HD Audio Controller + device pci 0.7 alias mp2 off end # sensor fusion hub (MP2) + end + device pci 08.2 alias internal_bridge_b off # internal bridge to bus B + device pci 0.0 alias sata off end + device pci 0.1 alias xgbe_0 off end + device pci 0.2 alias xgbe_1 off end + end + device pci 14.0 alias smbus on end # primary FCH function + device pci 14.3 alias lpc_bridge on end + device pci 14.6 alias sdhci off end + device pci 18.0 alias data_fabric_0 on end + device pci 18.1 alias data_fabric_1 on end + device pci 18.2 alias data_fabric_2 on end + device pci 18.3 alias data_fabric_3 on end + device pci 18.4 alias data_fabric_4 on end + device pci 18.5 alias data_fabric_5 on end + device pci 18.6 alias data_fabric_6 on end + device pci 18.7 alias data_fabric_7 on end + end +end diff --git a/util/mainboard/google/trembyle/template/overridetree.cb b/util/mainboard/google/trembyle/template/overridetree.cb index 6f545b2..d09c942 100644 --- a/util/mainboard/google/trembyle/template/overridetree.cb +++ b/util/mainboard/google/trembyle/template/overridetree.cb @@ -37,9 +37,7 @@ # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit - device pci 1.6 off end # GPP Bridge 5 device pci 1.7 on end # GPP Bridge 6 - NVME - device pci 14.6 off end # Non-Functional SDHCI end # domain device mmio 0xfedc4000 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/50626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b7c3fd32579a23539594672593a243172c161c7 Gerrit-Change-Number: 50626 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mainboard: Add labtop series
by Star Labs (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52798 to look at the new patch set (#22). Change subject: soc/mainboard: Add labtop series ...................................................................... soc/mainboard: Add labtop series Add support for LabTop Mk III (kblr) and LabTop Mk IV (cml) Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I37c74d03d86fb124ed96e45d1bf137eb2ec57251 --- M Documentation/distributions.md M Documentation/mainboard/index.md A src/mainboard/starlabs/Kconfig A src/mainboard/starlabs/Kconfig.name A src/mainboard/starlabs/labtop/Kconfig A src/mainboard/starlabs/labtop/Kconfig.name A src/mainboard/starlabs/labtop/Makefile.inc A src/mainboard/starlabs/labtop/acpi/ec.asl A src/mainboard/starlabs/labtop/acpi/mainboard.asl A src/mainboard/starlabs/labtop/acpi/sleep.asl A src/mainboard/starlabs/labtop/acpi/superio.asl A src/mainboard/starlabs/labtop/board_info.txt A src/mainboard/starlabs/labtop/bootblock.c A src/mainboard/starlabs/labtop/cmos.default A src/mainboard/starlabs/labtop/cmos.layout A src/mainboard/starlabs/labtop/dsdt.asl A src/mainboard/starlabs/labtop/hda_verb.c A src/mainboard/starlabs/labtop/mainboard.c A src/mainboard/starlabs/labtop/ramstage.c A src/mainboard/starlabs/labtop/spd/Makefile.inc A src/mainboard/starlabs/labtop/spd/empty_ddr4.spd.hex A src/mainboard/starlabs/labtop/spd/gskill-F4-3200C22S.hex A src/mainboard/starlabs/labtop/spd/micron-MT40A1G16KD-062E-E.spd.hex A src/mainboard/starlabs/labtop/spd/micron_dimm_MT40A1G16KD-062EE.spd.hex A src/mainboard/starlabs/labtop/spd/samsung-K4A8G165WB-BCRC.spd.hex A src/mainboard/starlabs/labtop/spd/spd.h A src/mainboard/starlabs/labtop/spd/spd_util.c A src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/memory.h A src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/romstage.h A src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/variants.h A src/mainboard/starlabs/labtop/variants/cml/Makefile.inc A src/mainboard/starlabs/labtop/variants/cml/board.fmd A src/mainboard/starlabs/labtop/variants/cml/data.vbt A src/mainboard/starlabs/labtop/variants/cml/devicetree.cb A src/mainboard/starlabs/labtop/variants/cml/gma-mainboard.ads A src/mainboard/starlabs/labtop/variants/cml/include/variant/gpio.h A src/mainboard/starlabs/labtop/variants/cml/include/variant/hda_verb.h A src/mainboard/starlabs/labtop/variants/cml/romstage.c A src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc A src/mainboard/starlabs/labtop/variants/kbl/board.fmd A src/mainboard/starlabs/labtop/variants/kbl/data.vbt A src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb A src/mainboard/starlabs/labtop/variants/kbl/gma-mainboard.ads A src/mainboard/starlabs/labtop/variants/kbl/include/variant/gpio.h A src/mainboard/starlabs/labtop/variants/kbl/include/variant/hda_verb.h A src/mainboard/starlabs/labtop/variants/kbl/romstage.c 46 files changed, 2,066 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/52798/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/52798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37c74d03d86fb124ed96e45d1bf137eb2ec57251 Gerrit-Change-Number: 52798 Gerrit-PatchSet: 22 Gerrit-Owner: Star Labs <admin(a)starlabs.systems> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit June 2021