coreboot-gerrit June 2021

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Change in coreboot[master]: mb/google/dedede/var/metaknight: Turn off lte power when s0ix
by Paul Menzel (Code Review) 07 Jun '21

07 Jun '21

Attention is currently required from: David Wu, Evan Green, Tim Wawrzynczak, Karthik Ramasubramanian. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55249 ) Change subject: mb/google/dedede/var/metaknight: Turn off lte power when s0ix ...................................................................... Patch Set 6: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55249/comment/d7b0af1c_45a525a3 PS6, Line 9: Turn off lte power when s0ix for power saving. Please mention that this is done using ACPI. https://review.coreboot.org/c/coreboot/+/55249/comment/7040354e_152664b2 PS6, Line 12: TEST= measure lte power comsumption is 0mV under s0ix How much was it before? File src/mainboard/google/dedede/variants/metaknight/include/variant/acpi/lte.asl: https://review.coreboot.org/c/coreboot/+/55249/comment/046909b1_e0d0b638 PS6, Line 3: LTE_EN What does EN mean? https://review.coreboot.org/c/coreboot/+/55249/comment/bbd97acc_db141ba5 PS6, Line 5: enter entering https://review.coreboot.org/c/coreboot/+/55249/comment/665f35ad_7335a667 PS6, Line 8: If (Arg0) { Is there a way to check in ACPI/ASL, if the device is present? -- To view, visit https://review.coreboot.org/c/coreboot/+/55249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78a39d8cd7a348ad36be9b5969f5c75ed48df833 Gerrit-Change-Number: 55249 Gerrit-PatchSet: 6 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Evan Green <evgreen(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 07 Jun 2021 10:51:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Update PMC Descriptor for Alderlake B0 silicon
by Rizwan Qureshi (Code Review) 07 Jun '21

07 Jun '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak, Sridhar Siricilla, Patrick Rudolph. Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55254 ) Change subject: soc/intel/alderlake: Update PMC Descriptor for Alderlake B0 silicon ...................................................................... Patch Set 5: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55254/comment/a07473db_81e50fd8 PS3, Line 9: Descriptpr Descriptor What is the definition of this field? https://review.coreboot.org/c/coreboot/+/55254/comment/2caed736_2a769610 PS3, Line 9: The patch updates PMC Descriptpr which is part of Descriptor Region if : system equipped with Alderlake B silicon. Why are we doing this change, what problem is being fixed? File src/soc/intel/alderlake/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/55254/comment/ccf88a71_cb959c93 PS4, Line 150: SI_DESC_REGION_SZ we don't need to read the whole region, we should be fine by just reading the required offset https://review.coreboot.org/c/coreboot/+/55254/comment/021b0609_d367741f PS4, Line 158: SI_DESC_REGION_SZ just update the offset, as opposed to the entire region File src/soc/intel/alderlake/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/55254/comment/23506474_5ec0d67d PS5, Line 132: cse this doesn't seem to be related to CSE at all Also, you can just have this check in the calling function itself instead of here. -- To view, visit https://review.coreboot.org/c/coreboot/+/55254 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d9a2ce0f0b3e386eefa1962ce706b58f31a8576 Gerrit-Change-Number: 55254 Gerrit-PatchSet: 5 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Jun 2021 09:52:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp/cpx/acpi: Align MADT IO APIC ID's with DMAR
by Arthur Heymans (Code Review) 07 Jun '21

07 Jun '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46503 ) Change subject: soc/intel/xeon_sp/cpx/acpi: Align MADT IO APIC ID's with DMAR ...................................................................... soc/intel/xeon_sp/cpx/acpi: Align MADT IO APIC ID's with DMAR In MADT loop over each stack and compare it against the same IO APIC ID table as during the DMAR table generation. This fixes Linux (5.8) warning: "DMAR-IR: [Firmware Bug]: ioapic 12 has no mapping iommu, interrupt remapping will be disabled" Change-Id: I32caf9036f0d548520b30b82324265cd4d0c3b8f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/cpx/acpi.c 1 file changed, 42 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/46503/1 diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index a1ebc4a..c7172b2 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -78,49 +78,56 @@ unsigned long acpi_fill_madt(unsigned long current) { - int cur_index; - struct iiostack_resource stack_info = {0}; + int cur_index = 0; + size_t hob_size; + const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); /* With CPX-SP FSP, PCH IOAPIC is allocated with first 120 GSIs. */ - int gsi_bases[] = { 0, 0x78, 0x80, 0x88, 0x90, 0x98, 0xA0, 0xA8, 0xB0 }; - int ioapic_ids[] = { 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0x10, 0x11, 0x12 }; + const int gsi_bases[] = { 0, 0x78, 0x80, 0x88, 0x90, 0x98, 0xA0, 0xA8, 0xB0 }; + const int IoApicID[] = { + // socket 0 + PC00_IOAPIC_ID, PC01_IOAPIC_ID, PC02_IOAPIC_ID, PC03_IOAPIC_ID, + PC04_IOAPIC_ID, PC05_IOAPIC_ID, + // socket 1 + PC06_IOAPIC_ID, PC07_IOAPIC_ID, PC08_IOAPIC_ID, PC09_IOAPIC_ID, + PC10_IOAPIC_ID, PC11_IOAPIC_ID, + }; + + assert(hob != NULL && hob_size != 0); /* Local APICs */ current = xeonsp_acpi_create_madt_lapics(current); - cur_index = 0; - get_iiostack_info(&stack_info); + /* + * Stack 0 has non-PCH IOAPIC and PCH IOAPIC. + * Add entry for PCH IOAPIC. + */ + { + const STACK_RES *ri = &hob->PlatformData.IIO_resource[0].StackRes[0]; + const int gsi_base = gsi_bases[cur_index]; + printk(BIOS_DEBUG, "Adding MADT IOAPIC for PCH: ioapic_id: 0x%x, " + "ioapic_base: 0x%x, gsi_base: 0x%x\n", + PCH_IOAPIC_ID, ri->IoApicBase, gsi_base); + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, PCH_IOAPIC_ID, + ri->IoApicBase, gsi_base); + cur_index++; + } - for (int stack = 0; stack < stack_info.no_of_stacks; ++stack) { - const STACK_RES *ri = &stack_info.res[stack]; - assert(cur_index < ARRAY_SIZE(ioapic_ids)); - assert(cur_index < ARRAY_SIZE(gsi_bases)); - int ioapic_id = ioapic_ids[cur_index]; - int gsi_base = gsi_bases[cur_index]; - printk(BIOS_DEBUG, "Adding MADT IOAPIC for stack: %d, ioapic_id: 0x%x, " - "ioapic_base: 0x%x, gsi_base: 0x%x\n", - stack, ioapic_id, ri->IoApicBase, gsi_base); - current += acpi_create_madt_ioapic( - (acpi_madt_ioapic_t *)current, - ioapic_id, ri->IoApicBase, gsi_base); - ++cur_index; - /* - * Stack 0 has non-PCH IOAPIC and PCH IOAPIC. - * Add entry for PCH IOAPIC. - */ - if (stack == 0) { /* PCH IOAPIC */ - assert(cur_index < ARRAY_SIZE(ioapic_ids)); - assert(cur_index < ARRAY_SIZE(gsi_bases)); - ioapic_id = ioapic_ids[cur_index]; - gsi_base = gsi_bases[cur_index]; - printk(BIOS_DEBUG, "Adding MADT IOAPIC for stack: %d, ioapic_id: 0x%x, " - "ioapic_base: 0x%x, gsi_base: 0x%x\n", - stack, ioapic_id, - ri->IoApicBase + 0x1000, gsi_base); - current += acpi_create_madt_ioapic( - (acpi_madt_ioapic_t *)current, - ioapic_id, ri->IoApicBase + 0x1000, gsi_base); + // DRHD + for (int iio = 0; iio < hob->PlatformData.numofIIO; ++iio) { + for (int stack = 0; stack < MAX_IIO_STACK; stack++) { + const STACK_RES *ri = &hob->PlatformData.IIO_resource[iio].StackRes[stack]; + if (ri->Personality != TYPE_UBOX_IIO) + continue; + const int ioapic_id = IoApicID[(iio * MAX_IIO_STACK) + stack]; + const int gsi_base = gsi_bases[cur_index]; + uint32_t apic_base = ri->IoApicBase; + if (iio == 0 && stack == 0) + apic_base += 0x1000; + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, + ioapic_id, apic_base, gsi_base); ++cur_index; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32caf9036f0d548520b30b82324265cd4d0c3b8f Gerrit-Change-Number: 46503 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/adlrvp:[TEST] hardcode board id
by build bot (Jenkins) (Code Review) 07 Jun '21

07 Jun '21

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55264 ) Change subject: mb/intel/adlrvp:[TEST] hardcode board id ...................................................................... Patch Set 1: (1 comment) File src/mainboard/intel/adlrvp/board_id.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120929): https://review.coreboot.org/c/coreboot/+/55264/comment/47ad12ae_57e54b06 PS1, Line 35: id=0x13; spaces required around that '=' (ctx:VxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/55264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94593f00c787fb4900ea7af0346b33b8026b7a40 Gerrit-Change-Number: 55264 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 07 Jun 2021 09:26:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp:[TEST] hardcode board id
by Sridhar Siricilla (Code Review) 07 Jun '21

07 Jun '21

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55264 ) Change subject: mb/intel/adlrvp:[TEST] hardcode board id ...................................................................... mb/intel/adlrvp:[TEST] hardcode board id Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I94593f00c787fb4900ea7af0346b33b8026b7a40 --- M src/mainboard/intel/adlrvp/board_id.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/55264/1 diff --git a/src/mainboard/intel/adlrvp/board_id.c b/src/mainboard/intel/adlrvp/board_id.c index 332ba1b..6364b35 100644 --- a/src/mainboard/intel/adlrvp/board_id.c +++ b/src/mainboard/intel/adlrvp/board_id.c @@ -32,5 +32,6 @@ } } } + id=0x13; return (id & BOARD_ID_MASK); } -- To view, visit https://review.coreboot.org/c/coreboot/+/55264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94593f00c787fb4900ea7af0346b33b8026b7a40 Gerrit-Change-Number: 55264 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: ec: Add Star Labs ITE 5570E support
by Sean Rhodes (Code Review) 07 Jun '21

07 Jun '21

Attention is currently required from: Sean Rhodes. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55263 to look at the new patch set (#2). Change subject: ec: Add Star Labs ITE 5570E support ...................................................................... ec: Add Star Labs ITE 5570E support Support for Star Labs labtop series EC Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I52287cd3c7606aa210621bb491665410c6fcab96 --- A src/ec/starlabs/it5570/Kconfig A src/ec/starlabs/it5570/Makefile.inc A src/ec/starlabs/it5570/acpi/ac.asl A src/ec/starlabs/it5570/acpi/battery.asl A src/ec/starlabs/it5570/acpi/cmos.asl A src/ec/starlabs/it5570/acpi/ec.asl A src/ec/starlabs/it5570/acpi/hid.asl A src/ec/starlabs/it5570/acpi/keyboard.asl A src/ec/starlabs/it5570/acpi/lid.asl A src/ec/starlabs/it5570/acpi/thermal.asl A src/ec/starlabs/it5570/chip.h A src/ec/starlabs/it5570/ec.c A src/ec/starlabs/it5570/ec.h 13 files changed, 782 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/55263/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55263 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52287cd3c7606aa210621bb491665410c6fcab96 Gerrit-Change-Number: 55263 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: ec: Add Star Labs ITE 5570E support
by build bot (Jenkins) (Code Review) 07 Jun '21

07 Jun '21

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55263 ) Change subject: ec: Add Star Labs ITE 5570E support ...................................................................... Patch Set 1: (30 comments) File src/ec/starlabs/it5570/acpi/ac.asl: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120926): https://review.coreboot.org/c/coreboot/+/55263/comment/ab9aacb0_6b06e0db PS1, Line 32: trailing whitespace File src/ec/starlabs/it5570/acpi/battery.asl: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120926): https://review.coreboot.org/c/coreboot/+/55263/comment/0326eb1f_d9b364d0 PS1, Line 41: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120926): https://review.coreboot.org/c/coreboot/+/55263/comment/53ea74f2_4c7a4832 PS1, Line 50: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120926): https://review.coreboot.org/c/coreboot/+/55263/comment/e6bbc2e7_6d1b2573 PS1, Line 67: trailing whitespace File src/ec/starlabs/it5570/acpi/cmos.asl: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120926): https://review.coreboot.org/c/coreboot/+/55263/comment/968850d4_ec2030a6 PS1, Line 6: NVRI, 8, trailing whitespace File src/ec/starlabs/it5570/acpi/ec.asl: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120926): https://review.coreboot.org/c/coreboot/+/55263/comment/1944a95a_1b66f46b PS1, Line 21: // Our embedded controller device. trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120926): https://review.coreboot.org/c/coreboot/+/55263/comment/5c9213f8_1cac9299 PS1, Line 24: Name(_HID, EISAID("PNP0C09")) trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120926): https://review.coreboot.org/c/coreboot/+/55263/comment/424406c3_02b13416 PS1, Line 61: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120926): https://review.coreboot.org/c/coreboot/+/55263/comment/ed177ec4_1d04b861 PS1, Line 92: B1RP, 8, //0x93 Battery#1 Remaining percentage trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120926): https://review.coreboot.org/c/coreboot/+/55263/comment/40d52b1b_5d526708 PS1, Line 136: Local0 = Acquire(ECMT, 1000) // save Acquire result so we can check for Mutex acquired trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120926): https://review.coreboot.org/c/coreboot/+/55263/comment/19770a1b_5497022a PS1, Line 146: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120926): https://review.coreboot.org/c/coreboot/+/55263/comment/6446ba4e_f74d6b3f PS1, Line 154: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120926): https://review.coreboot.org/c/coreboot/+/55263/comment/7f4dfdd0_529b2e6b PS1, Line 159: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120926): https://review.coreboot.org/c/coreboot/+/55263/comment/a60805a4_f90bf8ec PS1, Line 162: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120926): https://review.coreboot.org/c/coreboot/+/55263/comment/aa79d77a_662515da PS1, Line 165: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120926): https://review.coreboot.org/c/coreboot/+/55263/comment/b7e98ba7_8eb794d3 PS1, Line 167: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120926): https://review.coreboot.org/c/coreboot/+/55263/comment/f392702f_35a24047 PS1, Line 177: trailing whitespace File src/ec/starlabs/it5570/acpi/hid.asl: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120926): https://review.coreboot.org/c/coreboot/+/55263/comment/df93b12c_c7710830 PS1, Line 12: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120926): https://review.coreboot.org/c/coreboot/+/55263/comment/e1dc2f7f_0617a4c7 PS1, Line 21: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120926): https://review.coreboot.org/c/coreboot/+/55263/comment/2b4ddbf3_8e59dae3 PS1, Line 28: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120926): https://review.coreboot.org/c/coreboot/+/55263/comment/a40bca71_183933a5 PS1, Line 38: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120926): https://review.coreboot.org/c/coreboot/+/55263/comment/7a617fa3_272b3863 PS1, Line 48: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120926): https://review.coreboot.org/c/coreboot/+/55263/comment/6630fb55_a180569d PS1, Line 74: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120926): https://review.coreboot.org/c/coreboot/+/55263/comment/1558dc78_008ed2bb PS1, Line 98: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120926): https://review.coreboot.org/c/coreboot/+/55263/comment/b2b1401e_b07d3b97 PS1, Line 102: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120926): https://review.coreboot.org/c/coreboot/+/55263/comment/c72781f5_330e2e34 PS1, Line 106: trailing whitespace File src/ec/starlabs/it5570/acpi/keyboard.asl: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120926): https://review.coreboot.org/c/coreboot/+/55263/comment/65a0fcac_9120cf0f PS1, Line 17: } trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120926): https://review.coreboot.org/c/coreboot/+/55263/comment/914a6956_61dd9e96 PS1, Line 22: \_SB.HIDD.HPEM(8) trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120926): https://review.coreboot.org/c/coreboot/+/55263/comment/9a8b227e_ec11954b PS1, Line 29: } trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120926): https://review.coreboot.org/c/coreboot/+/55263/comment/53920db5_afb3ba10 PS1, Line 34: } trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/55263 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52287cd3c7606aa210621bb491665410c6fcab96 Gerrit-Change-Number: 55263 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 07 Jun 2021 08:59:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: ec: Add Star Labs ITE 5570E support
by Sean Rhodes (Code Review) 07 Jun '21

07 Jun '21

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55263 ) Change subject: ec: Add Star Labs ITE 5570E support ...................................................................... ec: Add Star Labs ITE 5570E support Support for Star Labs labtop series EC Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I52287cd3c7606aa210621bb491665410c6fcab96 --- A src/ec/starlabs/it5570/Kconfig A src/ec/starlabs/it5570/Makefile.inc A src/ec/starlabs/it5570/acpi/ac.asl A src/ec/starlabs/it5570/acpi/battery.asl A src/ec/starlabs/it5570/acpi/cmos.asl A src/ec/starlabs/it5570/acpi/ec.asl A src/ec/starlabs/it5570/acpi/hid.asl A src/ec/starlabs/it5570/acpi/keyboard.asl A src/ec/starlabs/it5570/acpi/lid.asl A src/ec/starlabs/it5570/acpi/thermal.asl A src/ec/starlabs/it5570/chip.h A src/ec/starlabs/it5570/ec.c A src/ec/starlabs/it5570/ec.h 13 files changed, 782 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/55263/1 diff --git a/src/ec/starlabs/it5570/Kconfig b/src/ec/starlabs/it5570/Kconfig new file mode 100644 index 0000000..7651757 --- /dev/null +++ b/src/ec/starlabs/it5570/Kconfig @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config EC_STARLABS_IT5570 + bool + select EC_ACPI + help + Interface to IT8987 embedded controller principally in Star Labs notebooks. diff --git a/src/ec/starlabs/it5570/Makefile.inc b/src/ec/starlabs/it5570/Makefile.inc new file mode 100644 index 0000000..3d93ab5 --- /dev/null +++ b/src/ec/starlabs/it5570/Makefile.inc @@ -0,0 +1,26 @@ +## SPDX-License-Identifier: GPL-2.0-only + +PHONY+=add_ite_fw +INTERMEDIATE+=add_ite_fw + +ifeq ($(CONFIG_EC_STARLABS_IT5570),y) +all-y += ec.c +smm-$(CONFIG_DEBUG_SMI) += ec.c + +ifeq ($(CONFIG_EC_STARLABS_IT_BIN),y) +add_ite_fw: $(obj)/coreboot.pre + $(CBFSTOOL) $(obj)/coreboot.pre write -r EC -f $(CONFIG_EC_STARLABS_IT_BIN_PATH) -u +endif + +ifeq ($(CONFIG_EC_STARLABS_IT_BIN_PATH),) +files_added:: warn_no_ite_fw +endif + +PHONY+=warn_no_ite_fw +warn_no_ite_fw: + printf "\n\t** WARNING **\n" + printf "coreboot has been built without the IT5570 EC Firmware.\n" + printf "Do not flash this image. Your LabTop Mk IV's power button\n" + printf "may not respond when you press it.\n\n" + +endif diff --git a/src/ec/starlabs/it5570/acpi/ac.asl b/src/ec/starlabs/it5570/acpi/ac.asl new file mode 100644 index 0000000..3b4b3eb --- /dev/null +++ b/src/ec/starlabs/it5570/acpi/ac.asl @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (ADP1) +{ + Name (_HID, "ACPI0003") + Name (_PCL, Package () { \_SB }) + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_PSR, 0, NotSerialized) // _PSR: Power Source + { + If (ECRD (RefOf (ECPS)) & 0x01) + { + PWRS = 1 + } + Else + { + PWRS = 0 + } + Return (PWRS) + } +} + +Method (_Q0A, 0, NotSerialized) +{ + Notify(BAT0, 0x81) + Notify(ADP1, 0x80) +} + +Method (_Q0B, 0, NotSerialized) +{ + Notify(BAT0, 0x81) + Notify(BAT0, 0x80) +} diff --git a/src/ec/starlabs/it5570/acpi/battery.asl b/src/ec/starlabs/it5570/acpi/battery.asl new file mode 100644 index 0000000..883cd65 --- /dev/null +++ b/src/ec/starlabs/it5570/acpi/battery.asl @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device(BAT0) +{ + Name(_HID, EISAID("PNP0C0A")) + Name(_UID, 1) + Name (_PCL, Package () { \_SB }) + + Method(_STA, 0) + { + If(And(ECRD(RefOf(ECPS)), 0x02)) + { + Return(0x1F) + } + Return(0x0F) + } + + Name(BPKG, Package() { + 1, // 0: Power Unit + 0xFFFFFFFF, // 1: Design Capacity + 0xFFFFFFFF, // 2: Last Full Charge Capacity + 1, // 3: Battery Technology(Rechargeable) + 0xFFFFFFFF, // 4: Design Voltage 10.8V + 0, // 5: Design capacity of warning + 0, // 6: Design capacity of low + 0x00000100, // 7: Battery capacity granularity 1 + 0x00000040, // 8: Battery capacity granularity 2 + "CN6613-2S3P", // 9: Model Number + "6UA3", // 10: Serial Number + "Real", // 11: Battery Type + "GDPT" // 12: OEM Information + }) + + Name (B1CN, "Real") + + Method(_BIF, 0, Serialized) + { + BPKG[1] = ECRD (RefOf(B1DC)) + BPKG[2] = ECRD (RefOf(B1FC)) + BPKG[4] = ECRD (RefOf(B1DV)) + + If(ECRD(RefOf(B1FC))) + { + BPKG[5] = ECRD (RefOf(B1FC)) / 10 + BPKG[6] = ECRD (RefOf(B1FC)) / 25 + BPKG[7] = ECRD (RefOf(B1DC)) / 100 + } + Return(BPKG) + } + + Name(PKG1, Package() { + 0xFFFFFFFF, // Battery State. + 0xFFFFFFFF, // Battery Present Rate. (in mWh) + 0xFFFFFFFF, // Battery Remaining Capacity. (in mWh) + 0xFFFFFFFF // Battery Present Voltage. (in mV) + }) + + Method(_BST, 0, Serialized) + { + PKG1[0] = ECRD (RefOf(B1ST)) & 0x07 + PKG1[1] = ECRD (RefOf(B1PR)) + PKG1[2] = ECRD (RefOf(B1RC)) + PKG1[3] = ECRD (RefOf(B1PV)) + Return(PKG1) + } +} + diff --git a/src/ec/starlabs/it5570/acpi/cmos.asl b/src/ec/starlabs/it5570/acpi/cmos.asl new file mode 100644 index 0000000..3368473 --- /dev/null +++ b/src/ec/starlabs/it5570/acpi/cmos.asl @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +OperationRegion (CMOS, SystemIO, 0x70, 0x02) +Field (CMOS, ByteAcc, NoLock, Preserve) +{ + NVRI, 8, + NVRD, 8 +} + +IndexField (NVRI, NVRD, ByteAcc, NoLock, Preserve) +{ + Offset (0x40), + KBBL, 8, // Keyboard backlight timeout + FNSW, 8, // Ctrl Fn Reverse (make keyboard Apple-like) + + Offset (0x7D), + FNLC, 8 // Current state of Fn Lock key. +} diff --git a/src/ec/starlabs/it5570/acpi/ec.asl b/src/ec/starlabs/it5570/acpi/ec.asl new file mode 100644 index 0000000..ff3e445 --- /dev/null +++ b/src/ec/starlabs/it5570/acpi/ec.asl @@ -0,0 +1,196 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define ASL_PVOL_DEFOF_NUM 0xe8 + +Scope (\_SB) +{ + #include "hid.asl" +} + +Scope (\_SB.PCI0) +{ + // Add the entries for the PS/2 keyboard and mouse. + #include <drivers/pc80/pc/ps2_controller.asl> +} + +Scope (\_SB.PCI0.LPCB) +{ + // Include the definitions for accessing CMOS. + #include "cmos.asl" + + // Our embedded controller device. + Device (H_EC) + { + Name(_HID, EISAID("PNP0C09")) + Name(_UID,1) + Name(ECAV, Zero) // OS Bug Checks if EC OpRegion accessed before Embedded Controller Driver loaded + Name(ECTK, One) // ECDT (Embedded Controller Boot Resources Table) Check to correct ECAV flag in the beginning + Name(LIDS, 0) + + Mutex(ECMT, 0) // EC Mutex + + Name (BFFR, ResourceTemplate() + { + IO(Decode16, 0x62, 0x62, 0, 1) // DIN/DOUT + IO(Decode16, 0x66, 0x66, 0, 1) // CMD/STS + }) + + Method (_CRS, 0, Serialized) + { + Return(BFFR) + } + + Method (_STA, 0, NotSerialized) + { + // Store (0x03, \_SB.PCI0.GFX0.CLID) + Return (0x0F) + } + + Method (_REG, 2) + { + If ((Arg0 == 0x03) && (Arg1 == 0x01)) + { + EREG() + } + } + + OperationRegion (SMIP,SystemIO, 0xB2, 0x1) + Field (SMIP, ByteAcc, Lock, Preserve) { + SMB2, 8 + } + + // EC RAM fields + OperationRegion(ECF2, EmbeddedControl, 0, 0xFF) + Field (ECF2, ByteAcc, Lock, Preserve) + { + Offset(0x00), + ECMV, 8, //0x00 EC Firmware main version + ECSV, 8, //0x01 EC Firmware sub version + KBVS, 8, //0x02 Keyboard revision + ECTV, 8, //0x03 EC Firmware test version + OSFG, 8, //0X04 Flag for enter OS //ICL_010+ + + Offset(0x2C), + FNST, 8, + + Offset(0x7F), //Support LID feature + LSTE, 1, //BIT0LID GPI + , 7, //Reserved + + Offset(0x80), + ECPS, 8, //0x80 AC & Battery status + B1MN, 8, //0x81 Battery#1 Model Number Code + B1SN, 16, //0x82~83 Battery#1 Serial Number + B1DC, 16, //0x84~85 Battery#1 Design Capacity + B1DV, 16, //0x86~87 Battery#1 Design Voltage + B1FC, 16, //0x88~89 Battery#1 Last Full Charge Capacity + B1TP, 16, //0x8A~8B Battery#1 Trip Point + B1ST, 8, //0x8C Battery#1 State + B1PR, 16, //0x8D~8E Battery#1 Present Rate + B1RC, 16, //0x8F~90 Battery#1 Remaining Capacity + B1PV, 16, //0x91~92 Battery#1 Present Voltage + B1RP, 8, //0x93 Battery#1 Remaining percentage + } + + Method (ECRD, 1, Serialized, 0, IntObj, FieldUnitObj) + { + // Check for ECDT support, set ECAV to One if ECDT is supported by OS + // Only check once at beginning since ECAV might be clear later in certain conditions + If (ECTK) + { + If (_REV >= 2) + { + ECAV = 0x01 + } + ECTK = 0x00 // Clear flag for checking once only + } + + Local0 = Acquire(ECMT, 1000) // save Acquire result so we can check for Mutex acquired + If (Local0 == 0x00) + { + If (ECAV) + { + Store(DerefOf (Arg0), Local1) // Execute Read from EC + Release(ECMT) + Return(Local1) + } + Else + { + Release(ECMT) + } + } + Return(0) + } + + Method(ECWT,2,Serialized,,, {IntObj, FieldUnitObj}) + { + If (ECTK) + { + If (_REV >= 2) + { + ECAV = 1 + } + ECTK = 0x00 + } + + Local0 = Acquire(ECMT, 1000) // save Acquire result so we can check for Mutex acquired + If (Local0 == 0x00) + { + If (ECAV) + { + Arg1 = Arg0 // Execute Write to EC + } + Release(ECMT) + } + } + + // EREG method will be used in _REG (evaluated by OS without + // ECDT support) or _INI (for OS with ECDT support) + Method (EREG) + { + // Update ECAV Object. ASL should check for this value + // to be 1 before accessing EC OpRegion. + ECAV = 1 + + LIDS = ECRD (RefOf (LSTE)) + + // Report OSFG to notify EC + ECWT(0x01, RefOf (OSFG)) + + // Save the current Power State for later. + // PWRS = Local0 + + // Update power state + PWRS = (ECRD (RefOf (ECPS)) & 0x01) + + //\_SB.CPPC = 0x00 // Note: \_SB.CPPC must be an Integer not a Method + + //Perform needed ACPI Notifications. + PNOT() + } + + Method(_GPE) + { + Local0 = 0x6E // GPI6E for eSPI + Return (Local0) + } + + Method (PTS, 1, Serialized) + { + Debug = Concatenate("EC: PTS: ", ToHexString(Arg0)) + \_SB.PCI0.LPCB.H_EC.OSFG = 0 + } + + Method (WAK, 1, Serialized) + { + Debug = Concatenate("EC: WAK: ", ToHexString(Arg0)) + \_SB.PCI0.LPCB.H_EC.OSFG = 1 + } + + // Include the other parts of the Embedded Controller ASL. + #include "keyboard.asl" + #include "battery.asl" + #include "ac.asl" + #include "lid.asl" + } +} diff --git a/src/ec/starlabs/it5570/acpi/hid.asl b/src/ec/starlabs/it5570/acpi/hid.asl new file mode 100644 index 0000000..f1c3ecf --- /dev/null +++ b/src/ec/starlabs/it5570/acpi/hid.asl @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device(HIDD) //HID ACPI Device. +{ + Name(_HID,"INTC1051") // Intel Ultrabook HID Platform Event Driver. + Name (HBSY, 0) // HID Busy + Name (HIDX, 0) // HID Index + Name (HMDE, 0) // HID Mode + Name (HRDY, 0) // HID Ready + Name (BTLD, 0) // Button Driver Loaded + Name (BTS1, 0) // Button Status + + Method(_STA,0,Serialized) + { + If (OSYS > 2013) { + Return(0x0F) + } Else { + Return(0) + } + } + + Method(HDDM,0,Serialized) + { + // Placeholder. + Name(DPKG, Package(4) {0x11111111, 0x22222222, 0x33333333, 0x44444444}) + Return(DPKG) + } + + Method(HDEM,0,Serialized) + { + HBSY = 0x00 // Clear HID Busy. + If (LEqual(HMDE,0)) + { + Return(HIDX) + } + Return(HMDE) + } + + Method(HDMM,0,Serialized) + { + Return(HMDE) // Return Mode of operation. + } + + Method(HDSM,1,Serialized) + { + HRDY = Arg0 // Store HID Ready Status. + } + + Method(HPEM,1,Serialized) // HID Platform Event Method. + { + HBSY = 1 + If (LEqual(HMDE,0)) + { + HIDX = Arg0 + } Else { + HIDX = Arg0 + } + Notify(\_SB.HIDD,0xC0) + Local0 = 0 + While((Local0 < 250) && (HBSY)) + { + Sleep(4) + Increment(Local0) + } + If (HBSY <= 1) + { + HBSY = 0 + HIDX = 0 + Return(1) + } Else { + Return(0) + } + } + + Method(BTNL,0,Serialized) + { + BTS1 = 0 + } + + Method(BTNE,1,Serialized) + { + Return(BTS1) + } + + Method(BTNS,0,Serialized) + { + Return(BTS1) + } + + Method(BTNC,0,Serialized) // HID Button Capabilities Method + { + Return(0x1F) + } + + Method (HEBC,0,Serialized) { + Return (0x00063002) + } + + Method (H2BC,0,Serialized) { + Return (0x00063002) + } + + Method (HEEC,0,Serialized) { + Return(0) + } + + Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) + { + If (LEqual(Arg0, ToUUID ("EEEC56B3-4442-408F-A792-4EDD4D758054"))) + { + If (LEqual(1,ToInteger(Arg1))) + { + Switch (ToInteger(Arg2)) + { + Case (0) + { + Return (Buffer() {0xFF, 0x03}) + } + + Case (1) + { + BTNL() + } + + Case (2) + { + Return(HDMM()) + } + + Case (3) + { + HDSM(DeRefOf(Index(Arg3, 0))) + } + + Case (4) + { + Return(HDEM()) + } + + Case (5) + { + Return(BTNS()) + } + + Case (6) + { + BTNE(DeRefOf(Index(Arg3, 0))) + } + + Case (7) + { + Return(HEBC()) + } + + Case (8) + { + Return(0x40) + } + + Case (9) + { + Return(H2BC()) + } + } + } + } + Return (Buffer() {0x00}) + } +} + +Method(PWPR, 0, Serialized) // Power Button Press Helper Method +{ + Notify(\_SB.HIDD,0xCE) // Notify HID driver that Power button is pressed. +} + +Method(PWRR, 0, Serialized) // Power Button Release Helper Method +{ + Notify(\_SB.HIDD,0xCF) // Notify HID driver that Power button is released. +} diff --git a/src/ec/starlabs/it5570/acpi/keyboard.asl b/src/ec/starlabs/it5570/acpi/keyboard.asl new file mode 100644 index 0000000..fd7ab97 --- /dev/null +++ b/src/ec/starlabs/it5570/acpi/keyboard.asl @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_Q80) // Volume up +{ + Store ("-----> _Q80", Debug) + Notify (\_SB.HIDD, 0xC4) + Notify (\_SB.HIDD, 0xC5) + Store ("<----- _Q80", Debug) +} + +Method(_Q81) // Volume down +{ + Store ("-----> _Q81", Debug) + Notify (\_SB.HIDD, 0xC6) + Notify (\_SB.HIDD, 0xC7) + Store ("<----- _Q81", Debug) +} + +Method(_Q99) // Wireless mode +{ + Store ("-----> _Q99", Debug) + \_SB.HIDD.HPEM(8) + Store ("<----- _Q80", Debug) +} + +Method(_Q06) // Brightness decrease +{ + \_SB.PCI0.GFX0.DECB() +} + +Method(_Q07) // Brightness increase +{ + \_SB.PCI0.GFX0.INCB() +} + +Method(_Q08) // FN lock QEvent +{ + FNLC = FNST +} + +Method(_Q54) // Power Button Event +{ + Store ("-----> _Q54", Debug) + If (CondRefOf (\_SB.PWRB)) + { + Notify(\_SB.PWRB, 0x80) + } + Store ("<----- _Q54", Debug) +} + +Method(_QD5) // 10 second power button press +{ + Store ("-----> _QD5", Debug) + \_SB.PWPR() + Store ("<----- _QD5", Debug) +} + +Method(_QD6) // 10 second power button de-press +{ + Store ("-----> _QD6", Debug) + \_SB.PWRR() + Store ("<----- _QD6", Debug) +} diff --git a/src/ec/starlabs/it5570/acpi/lid.asl b/src/ec/starlabs/it5570/acpi/lid.asl new file mode 100644 index 0000000..2295a24 --- /dev/null +++ b/src/ec/starlabs/it5570/acpi/lid.asl @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +Device (LID0) +{ + Name (_HID, EisaId ("PNP0C0D")) + + Method (_STA, 0, NotSerialized) + { + DEBUG = "---> IT5570 LID: _STA" + Return (0x0F) + } + + + Method (_LID, 0, NotSerialized) + { + DEBUG = "---> IT5570 LID: _LID" + If (\_SB.PCI0.LPCB.H_EC.ECRD (RefOf (\_SB.PCI0.LPCB.H_EC.LSTE)) == 0x01) + { + Local0 = 1 + } + else + { + Local0 = 0 + } + Return (Local0) + } +} + +Method (_Q0C, 0, NotSerialized) // Lid close event +{ + DEBUG = "---> IT5570 LID: Q0C (close event)" + LIDS = 0 + \LIDS = \_SB.PCI0.LPCB.H_EC.LIDS + Notify (LID0, 0x80) +} + +Method (_Q0D, 0, NotSerialized) // Lid open event +{ + DEBUG = "---> IT5570 LID: Q0D (open event)" + LIDS = 1 + \LIDS = \_SB.PCI0.LPCB.H_EC.LIDS + Notify (LID0, 0x80) +} diff --git a/src/ec/starlabs/it5570/acpi/thermal.asl b/src/ec/starlabs/it5570/acpi/thermal.asl new file mode 100644 index 0000000..a112fa2 --- /dev/null +++ b/src/ec/starlabs/it5570/acpi/thermal.asl @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_QF0) // Thermal event. +{ + Notify (\_TZ.TZ01, 0x80 +} diff --git a/src/ec/starlabs/it5570/chip.h b/src/ec/starlabs/it5570/chip.h new file mode 100644 index 0000000..d822358 --- /dev/null +++ b/src/ec/starlabs/it5570/chip.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _EC_STARLABS_IT5570_CHIP_H +#define _EC_STARLABS_IT5570_CHIP_H + +struct ec_starlabs_it5570_config { + u8 cpuhot_limit; /* temperature in °C which asserts PROCHOT# */ +}; + +#endif /* _EC_STARLABS_IT5570_CHIP_H */ diff --git a/src/ec/starlabs/it5570/ec.c b/src/ec/starlabs/it5570/ec.c new file mode 100644 index 0000000..8ed2e87 --- /dev/null +++ b/src/ec/starlabs/it5570/ec.c @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pnp.h> +#include <pc80/keyboard.h> +#include <ec/acpi/ec.h> +#include <delay.h> +#include <option.h> + +#include "ec.h" +#include "chip.h" + +u16 it_get_version(void) +{ + return (ec_read(0x00) << 8) | ec_read(0x01); +} + +static void it5570_init(struct device *dev) +{ + if (!dev->enabled) + return; + + /* + * The address/data IO port pair for the it5570 EC are configurable + * through the EC domain and are fixed by the EC's firmware blob. If + * the value(s) passed through the "dev" structure don't match the + * expected values then output severe warnings. + */ + if (dev->path.pnp.port != IT5570E_FIXED_ADDR) { + printk(BIOS_ERR, "IT5570: Incorrect ports defined in devicetree.cb.\n"); + printk(BIOS_ERR, "IT5570: Serious operational issues will arise.\n"); + return; + } + + u8 chipid1 = pnp_read_index(dev->path.pnp.port, IT5570_CHIPID1); + u8 chipid2 = pnp_read_index(dev->path.pnp.port, IT5570_CHIPID2); + if (chipid1 != IT5570_CHIPID1_VAL || chipid2 != IT5570_CHIPID2_VAL) { + printk(BIOS_DEBUG, "IT5570: Device not found.\n"); + return; + } + + printk(BIOS_DEBUG, "IT5570: Initializing keyboard.\n"); + pc_keyboard_init(NO_AUX_DEVICE); + + /* Enable the keyboard backlight support. */ + ec_write(0x18, 0xaa); + ec_write(0x19, 0xdd); + + /* Set the timeout for the keyboard backlight. */ + ec_write(ECRAM_KBL_TIMEOUT, get_uint_option("kbl_timeout", 0)); + + /* + * Set the correct state for the Ctrl Fn Reverse option. This + * swaps the Ctrl and Fn keys to make it like an Apple keyboard. + */ + ec_write(ECRAM_FN_CTRL_REVERSE, get_uint_option("fn_ctrl_swap", 0)); + /* + * Copy the stored state of the fn_lock_state CMOS variable to the + * corresponding location within the EC RAM. + */ + ec_write(ECRAM_FN_LOCK_STATE, get_uint_option("fn_lock_state", 0)); +} + +static struct device_operations ops = { + .init = it5570_init, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, 0, 0, 0, } +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations ec_starlabs_it5570_ops = { + CHIP_NAME("ITE IT5570 EC") + .enable_dev = enable_dev +}; diff --git a/src/ec/starlabs/it5570/ec.h b/src/ec/starlabs/it5570/ec.h new file mode 100644 index 0000000..20da6db --- /dev/null +++ b/src/ec/starlabs/it5570/ec.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * EC communication interface for ITE IT5570 Embedded Controller. + */ + +#ifndef _EC_STARLABS_IT5570_H +#define _EC_STARLABS_IT5570_H + +/* + * Define the expected value of the PNP base address that is fixed through + * the BADRSEL register controlled within the EC domain by the binary blob. + */ +#define IT5570E_FIXED_ADDR 0x4e + +/* Logical device number (LDN) assignments. */ +#define IT5570E_SP1 0x01 /* Com1 */ +#define IT5570E_SP2 0x02 /* Com2 */ +#define IT5570E_SWUC 0x04 /* System Wake-Up */ +#define IT5570E_KBCM 0x05 /* PS/2 mouse */ +#define IT5570E_KBCK 0x06 /* PS/2 keyboard */ +#define IT5570E_IR 0x0a /* Consumer IR */ +#define IT5570E_SMFI 0x0f /* Shared Memory/Flash Interface */ +#define IT5570E_RTCT 0x10 /* RTC-like Timer */ +#define IT5570E_PMC1 0x11 /* Power Management Channel 1 */ +#define IT5570E_PMC2 0x12 /* Power Management Channel 2 */ +#define IT5570E_SSPI 0x13 /* Serial Peripheral Interface */ +#define IT5570E_PECI 0x14 /* Platform EC Interface */ +#define IT5570E_PMC3 0x17 /* Power Management Channel 3 */ +#define IT5570E_PMC4 0x18 /* Power Management Channel 4 */ +#define IT5570E_PMC5 0x19 /* Power Management Channel 5 */ + +/* Host domain registers. */ +#define IT5570_CHIPID1 0x20 /* Device ID register 1 */ +#define IT5570_CHIPID2 0x21 /* Device ID register 2 */ + +/* IT5570 chip ID byte values. */ +#define IT5570_CHIPID1_VAL 0x55 +#define IT5570_CHIPID2_VAL 0x70 + +/* EC RAM offsets. */ +#define ECRAM_KBL_TIMEOUT 0x07 +#define ECRAM_FN_CTRL_REVERSE 0x08 +#define ECRAM_FN_LOCK_STATE 0x2C + +u16 it_get_version(void); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/55263 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52287cd3c7606aa210621bb491665410c6fcab96 Gerrit-Change-Number: 55263 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/lapic: Split virtual_wire_mode_init()
by build bot (Jenkins) (Code Review) 07 Jun '21

07 Jun '21

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55261 ) Change subject: cpu/x86/lapic: Split virtual_wire_mode_init() ...................................................................... Patch Set 1: (1 comment) File src/cpu/x86/lapic/lapic.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120922): https://review.coreboot.org/c/coreboot/+/55261/comment/cb806f4b_9b3f44eb PS1, Line 70: if (need_lapic_init()) { braces {} are not necessary for any arm of this statement -- To view, visit https://review.coreboot.org/c/coreboot/+/55261 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5e37c1a0a91fa4e9542141aa74f1c1876fee94e Gerrit-Change-Number: 55261 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 07 Jun 2021 08:07:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/metaknight: Turn off lte power when s0ix
by David Wu (Code Review) 07 Jun '21

07 Jun '21

Attention is currently required from: David Wu. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55249 to look at the new patch set (#5). Change subject: mb/google/dedede/var/metaknight: Turn off lte power when s0ix ...................................................................... mb/google/dedede/var/metaknight: Turn off lte power when s0ix Turn off lte power when s0ix for power saving. BUG=b:188614547 TEST= measure lte power comsumption is 0mV under s0ix Change-Id: I78a39d8cd7a348ad36be9b5969f5c75ed48df833 Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Kconfig.name M src/mainboard/google/dedede/dsdt.asl A src/mainboard/google/dedede/variants/metaknight/include/variant/acpi/lte.asl 4 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/55249/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/55249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78a39d8cd7a348ad36be9b5969f5c75ed48df833 Gerrit-Change-Number: 55249 Gerrit-PatchSet: 5 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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