coreboot-gerrit June 2021

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Change in coreboot[master]: ec: Add Star Labs ITE 5570E support
by Sean Rhodes (Code Review) 07 Jun '21

07 Jun '21

Attention is currently required from: Paul Menzel. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55263 ) Change subject: ec: Add Star Labs ITE 5570E support ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/55263/comment/fac1657b_2834b74b PS3, Line 9: Support for Star Labs labtop series EC > Please elaborate what firmware the EC is running, what interface is implemented, and if you modeled […] What interface do you mean? -- To view, visit https://review.coreboot.org/c/coreboot/+/55263 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52287cd3c7606aa210621bb491665410c6fcab96 Gerrit-Change-Number: 55263 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 07 Jun 2021 11:37:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel/model_206ax/acpi.c: Do not report P_BLK
by Patrick Georgi (Code Review) 07 Jun '21

07 Jun '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55216 ) Change subject: cpu/intel/model_206ax/acpi.c: Do not report P_BLK ...................................................................... cpu/intel/model_206ax/acpi.c: Do not report P_BLK IO MWAIT redirection is disabled, which means reads to the P_LVL2 and P_LVL3 "registers" will never produce any C-state transition requests. Change-Id: Ibbf7b915a9909d6bc8e784a439df751e11ec5bee Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55216 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/cpu/intel/model_2065x/acpi.c 1 file changed, 2 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c index 39d028b..11899c6 100644 --- a/src/cpu/intel/model_2065x/acpi.c +++ b/src/cpu/intel/model_2065x/acpi.c @@ -205,7 +205,7 @@ void generate_cpu_entries(const struct device *device) { - int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; + int coreID, cpuID; int totalcores = dev_count_cpu(); int cores_per_package = get_cores_per_package(); int numcpus = totalcores/cores_per_package; @@ -215,15 +215,9 @@ for (cpuID = 1; cpuID <= numcpus; cpuID++) { for (coreID = 1; coreID <= cores_per_package; coreID++) { - if (coreID > 1) { - pcontrol_blk = 0; - plen = 0; - } - /* Generate processor \_SB.CPUx */ acpigen_write_processor( - (cpuID-1)*cores_per_package+coreID-1, - pcontrol_blk, plen); + (cpuID-1)*cores_per_package+coreID-1, 0, 0); /* Generate P-state tables */ generate_P_state_entries( -- To view, visit https://review.coreboot.org/c/coreboot/+/55216 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbf7b915a9909d6bc8e784a439df751e11ec5bee Gerrit-Change-Number: 55216 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: 3rdparty/intel-sec-tools: Update to support Boot Guard
by Patrick Georgi (Code Review) 07 Jun '21

07 Jun '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55013 ) Change subject: 3rdparty/intel-sec-tools: Update to support Boot Guard ...................................................................... 3rdparty/intel-sec-tools: Update to support Boot Guard Update intel-sec-tools to commit of BootGuard support. Remove --coreboot argument in src/security/intel/cbnt/Makefile.inc: was removed as argument for cbnt Change-Id: Iaf34bdb65a5f067d1d632e35d340b8fc49aaf318 Signed-off-by: Christopher Meis <christopher.meis(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55013 Reviewed-by: Christian Walter <christian.walter(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M 3rdparty/intel-sec-tools M src/security/intel/cbnt/Makefile.inc 2 files changed, 1 insertion(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Christian Walter: Looks good to me, approved diff --git a/3rdparty/intel-sec-tools b/3rdparty/intel-sec-tools index 875763e..6682883 160000 --- a/3rdparty/intel-sec-tools +++ b/3rdparty/intel-sec-tools @@ -1 +1 @@ -Subproject commit 875763e421ed3a76ec0e0f51c4ed93c6a0038771 +Subproject commit 6682883ba2dffb6a08ff4589590320e60ddf1f18 diff --git a/src/security/intel/cbnt/Makefile.inc b/src/security/intel/cbnt/Makefile.inc index 9b00d7d..7215a63 100644 --- a/src/security/intel/cbnt/Makefile.inc +++ b/src/security/intel/cbnt/Makefile.inc @@ -60,7 +60,6 @@ --ibbflags=$(CONFIG_INTEL_CBNT_IBB_FLAGS) \ --entrypoint=$(shell printf "%d" 0xfffffff0) \ --ibbhash=$(PK_HASH_ALG_SHA256),$(PK_HASH_ALG_SHA1),$(PK_HASH_ALG_SHA384) \ - --coreboot \ --sinitmin=$(CONFIG_INTEL_CBNT_SINIT_SVN) \ --txtflags=0 \ --powerdowninterval=$(CONFIG_INTEL_CBNT_PD_INTERVAL) \ -- To view, visit https://review.coreboot.org/c/coreboot/+/55013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf34bdb65a5f067d1d632e35d340b8fc49aaf318 Gerrit-Change-Number: 55013 Gerrit-PatchSet: 7 Gerrit-Owner: Christopher Meis Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: ec: Add Star Labs ITE 5570E support
by Sean Rhodes (Code Review) 07 Jun '21

07 Jun '21

Attention is currently required from: Sean Rhodes. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55263 to look at the new patch set (#4). Change subject: ec: Add Star Labs ITE 5570E support ...................................................................... ec: Add Star Labs ITE 5570E support Support for Star Labs labtop series EC (TGL) proprietry firmware. ASL mirrors the v1 format and function of the AMI BIOS. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I52287cd3c7606aa210621bb491665410c6fcab96 --- A src/ec/starlabs/it5570/Kconfig A src/ec/starlabs/it5570/Makefile.inc A src/ec/starlabs/it5570/acpi/ac.asl A src/ec/starlabs/it5570/acpi/battery.asl A src/ec/starlabs/it5570/acpi/cmos.asl A src/ec/starlabs/it5570/acpi/ec.asl A src/ec/starlabs/it5570/acpi/hid.asl A src/ec/starlabs/it5570/acpi/keyboard.asl A src/ec/starlabs/it5570/acpi/lid.asl A src/ec/starlabs/it5570/acpi/thermal.asl A src/ec/starlabs/it5570/chip.h A src/ec/starlabs/it5570/ec.c A src/ec/starlabs/it5570/ec.h 13 files changed, 781 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/55263/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/55263 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52287cd3c7606aa210621bb491665410c6fcab96 Gerrit-Change-Number: 55263 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede/var/kracko: Add P-sensor support
by Patrick Georgi (Code Review) 07 Jun '21

07 Jun '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55133 ) Change subject: mb/google/dedede/var/kracko: Add P-sensor support ...................................................................... mb/google/dedede/var/kracko: Add P-sensor support Configure GPIO D22/D23/E11. Add P-sensor to device tree, these registers are draft version. BUG=b:178092096 BRANCH=dedede TEST=built firmware and dmesg shows STH9324 initial success. Change-Id: I2c8feedd6efc1a471304322a17480c836e22349e Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55133 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/kracko/gpio.c M src/mainboard/google/dedede/variants/kracko/overridetree.cb 2 files changed, 60 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/kracko/gpio.c b/src/mainboard/google/dedede/variants/kracko/gpio.c index ca89730..b4c00bd 100644 --- a/src/mainboard/google/dedede/variants/kracko/gpio.c +++ b/src/mainboard/google/dedede/variants/kracko/gpio.c @@ -13,6 +13,13 @@ /* D0 : WWAN_HOST_WAKE ==> WWAN_WDISABLE_L */ PAD_CFG_GPO(GPP_D0, 1, DEEP), + /* D22 : AP_I2C_SUB_SDA*/ + PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), + /* D23 : AP_I2C_SUB_SCL */ + PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), + + /* E11 : AP_I2C_SUB_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_E11, NONE, PLTRST, LEVEL, NONE), /* H17 : WWAN_RST_L */ PAD_CFG_GPO(GPP_H17, 0, PLTRST), diff --git a/src/mainboard/google/dedede/variants/kracko/overridetree.cb b/src/mainboard/google/dedede/variants/kracko/overridetree.cb index 66fb274..3d9307b 100644 --- a/src/mainboard/google/dedede/variants/kracko/overridetree.cb +++ b/src/mainboard/google/dedede/variants/kracko/overridetree.cb @@ -136,6 +136,59 @@ device i2c 1a on end end end #I2C 4 + device pci 19.1 on + chip drivers/i2c/sx9324 + register "desc" = ""SAR Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)" + register "uid" = "2" + register "reg_gnrl_ctrl0" = "0x0a" + register "reg_gnrl_ctrl1" = "0x22" + register "reg_afe_ctrl0" = "0x20" + register "reg_afe_ctrl3" = "0x01" + register "reg_afe_ctrl4" = "0x47" + register "reg_afe_ctrl6" = "0x00" + register "reg_afe_ctrl7" = "0x47" + register "reg_afe_ctrl8" = "0x12" + register "reg_afe_ctrl9" = "0x0f" + register "reg_afe_ph0" = "0x37" + register "reg_afe_ph1" = "0x29" + register "reg_afe_ph2" = "0x1f" + register "reg_afe_ph3" = "0x3d" + register "reg_prox_ctrl0" = "0x0b" + register "reg_prox_ctrl1" = "0x0b" + register "reg_prox_ctrl2" = "0x20" + register "reg_prox_ctrl3" = "0x20" + register "reg_prox_ctrl4" = "0x0c" + register "reg_prox_ctrl5" = "0x00" + register "reg_prox_ctrl6" = "0x2d" + register "reg_prox_ctrl7" = "0xc0" + register "reg_adv_ctrl0" = "0x00" + register "reg_adv_ctrl1" = "0x00" + register "reg_adv_ctrl2" = "0x00" + register "reg_adv_ctrl3" = "0x00" + register "reg_adv_ctrl4" = "0x00" + register "reg_adv_ctrl5" = "0x05" + register "reg_adv_ctrl6" = "0x00" + register "reg_adv_ctrl7" = "0x00" + register "reg_adv_ctrl8" = "0x00" + register "reg_adv_ctrl9" = "0x00" + register "reg_adv_ctrl10" = "0x00" + register "reg_adv_ctrl11" = "0x00" + register "reg_adv_ctrl12" = "0x00" + register "reg_adv_ctrl13" = "0x00" + register "reg_adv_ctrl14" = "0x80" + register "reg_adv_ctrl15" = "0x0c" + register "reg_adv_ctrl16" = "0x04" + register "reg_adv_ctrl17" = "0x70" + register "reg_adv_ctrl18" = "0x40" + register "reg_adv_ctrl19" = "0x00" + register "reg_adv_ctrl20" = "0x00" + register "reg_irq_cfg0" = "0x00" + register "reg_irq_cfg1" = "0x80" + register "reg_irq_cfg2" = "0x00" + device i2c 28 on end + end + end # I2C 5 device pci 1f.3 on chip drivers/generic/max98357a register "hid" = ""MX98360A"" -- To view, visit https://review.coreboot.org/c/coreboot/+/55133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c8feedd6efc1a471304322a17480c836e22349e Gerrit-Change-Number: 55133 Gerrit-PatchSet: 7 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/pcie/rtd3/device: Add PCIe RTD3 driver
by Patrick Georgi (Code Review) 07 Jun '21

07 Jun '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54966 ) Change subject: drivers/pcie/rtd3/device: Add PCIe RTD3 driver ...................................................................... drivers/pcie/rtd3/device: Add PCIe RTD3 driver This driver was inspired from soc/intel/common/block/pci/rtd3. I decided to copy and modify it because the Intel driver has a lot of Intel specific code. This driver has been stripped down to only provide a power resource and set the StorageD3Enable property. This driver is SoC agnostic and does not handle suspending the actual PCIe root port. That should be implemented by an SoC specific driver. This is required for Guybrush to suspend/resume properly because the NVMe power is tied to the S0 power rails, so the kernel needs to place the device into D3. BUG=b:184617186 TEST=Guybrush is able to suspend/resume properly. Also see power resource get enabled / disabled. [ 56.075559] power-0416 __acpi_power_off : Power resource [RTD3] turned off [ 56.075562] device_pm-0279 device_set_power : Device [PXSX] transitioned to D3cold [ 56.075567] pci_pm_suspend_noirq: nvme 0000:02:00.0: PCI PM: Suspend power state: D3cold [ 56.075569] nvme 0000:02:00.0: pci_pm_suspend_noirq+0x0/0x413 returned 0 after 15978 usecs [ 123.464874] nvme 0000:02:00.0: calling pci_pm_resume_noirq+0x0/0x11d @ 7, parent: 0000:00:02.4 [ 123.464891] acpi_device_set_power: ACPI: \_SB_.PCI0.GP14.PXSX: Power state change: D3cold -> D0 [ 123.464982] power-0360 __acpi_power_on : Power resource [RTD3] turned on [ 123.464984] device_pm-0279 device_set_power : Device [PXSX] transitioned to D0 [ 123.465039] nvme 0000:02:00.0: pci_pm_resume_noirq+0x0/0x11d returned 0 after 158 usecs Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I2adfc925183ff7a19ab97e89212bc87c40d552d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54966 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- A src/drivers/pcie/rtd3/device/Kconfig A src/drivers/pcie/rtd3/device/Makefile.inc A src/drivers/pcie/rtd3/device/chip.c A src/drivers/pcie/rtd3/device/chip.h 4 files changed, 204 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/drivers/pcie/rtd3/device/Kconfig b/src/drivers/pcie/rtd3/device/Kconfig new file mode 100644 index 0000000..7fecd57 --- /dev/null +++ b/src/drivers/pcie/rtd3/device/Kconfig @@ -0,0 +1,6 @@ +config DRIVERS_PCIE_RTD3_DEVICE + bool + depends on HAVE_ACPI_TABLES + help + When enabled, this driver will add support for ACPI controlled + Runtime D3 using GPIOs for power/reset control of the PCIe device. diff --git a/src/drivers/pcie/rtd3/device/Makefile.inc b/src/drivers/pcie/rtd3/device/Makefile.inc new file mode 100644 index 0000000..df4aaf6 --- /dev/null +++ b/src/drivers/pcie/rtd3/device/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_PCIE_RTD3_DEVICE) += chip.c diff --git a/src/drivers/pcie/rtd3/device/chip.c b/src/drivers/pcie/rtd3/device/chip.c new file mode 100644 index 0000000..349dffd --- /dev/null +++ b/src/drivers/pcie/rtd3/device/chip.c @@ -0,0 +1,169 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi_device.h> +#include <acpi/acpigen.h> +#include <acpi/acpigen_pci.h> +#include <assert.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include "chip.h" + +/* + * This UUID and the resulting ACPI Device Property is defined by the + * Power Management for Storage Hardware Devices: + * + * https://docs.microsoft.com/en-us/windows-hardware/design/component-guidelin… + */ +#define PCIE_RTD3_STORAGE_UUID "5025030F-842F-4AB4-A561-99A5189762D0" +#define PCIE_RTD3_STORAGE_PROPERTY "StorageD3Enable" + +/* + * Writes the ACPI power resources for a PCI device so it can enter D3Cold. + * + * If the device is a storage class, then the StorageD3Enable _DSD will + * also be added. + * + * e.g., + * + * Scope (\_SB.PCI0.GP14) + * { + * Device (NVME) + * { + * Name (_PR0, Package (0x01) // _PR0: Power Resources for D0 + * { + * PRIC + * }) + * Name (_PR3, Package (0x01) // _PR3: Power Resources for D3hot + * { + * PRIC + * }) + * PowerResource (PRIC, 0x00, 0x0000) + * { + * Method (_STA, 0, NotSerialized) // _STA: Status + * { + * ... + * } + * + * Method (_ON, 0, Serialized) // _ON_: Power On + * { + * ... + * } + * + * Method (_OFF, 0, Serialized) // _OFF: Power Off + * { + * ... + * } + * } + * + * Name (_ADR, 0x0000000000000000) // _ADR: Address + * Method (_STA, 0, NotSerialized) // _STA: Status + * { + * Return (0x0F) + * } + * + * Name (_DSD, Package (0x02) // _DSD: Device-Specific Data + * { + * ToUUID ("5025030f-842f-4ab4-a561-99a5189762d0"), + * Package (0x01) + * { + * Package (0x02) + * { + * "StorageD3Enable", + * One + * } + * } + * }) + * } + * } + */ +static void pcie_rtd3_device_acpi_fill_ssdt(const struct device *dev) +{ + struct acpi_dp *dsd, *pkg; + const struct drivers_pcie_rtd3_device_config *config = config_of(dev); + /* Copy the GPIOs to avoid discards 'const' qualifier error */ + struct acpi_gpio reset_gpio = config->reset_gpio; + struct acpi_gpio enable_gpio = config->enable_gpio; + const struct acpi_power_res_params power_res_params = { + .reset_gpio = &reset_gpio, + .reset_delay_ms = config->reset_delay_ms, + .reset_off_delay_ms = config->reset_off_delay_ms, + .enable_gpio = &enable_gpio, + .enable_delay_ms = config->enable_delay_ms, + .enable_off_delay_ms = config->enable_off_delay_ms, + .use_gpio_for_status = true, + }; + const char *scope = acpi_device_scope(dev); + const char *name = acpi_device_name(dev); + + assert(name); + assert(scope); + + printk(BIOS_INFO, "%s.%s: Enable RTD3 for %s (%s)\n", scope, name, dev_path(dev), + dev->chip_ops->name); + + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + + acpi_device_add_power_res(&power_res_params); + + acpigen_write_ADR_pci_device(dev); + acpigen_write_STA(acpi_device_status(dev)); + + /* Storage devices won't enter D3 without this property */ + if ((dev->class >> 16) == PCI_BASE_CLASS_STORAGE) { + dsd = acpi_dp_new_table("_DSD"); + pkg = acpi_dp_new_table(PCIE_RTD3_STORAGE_UUID); + acpi_dp_add_integer(pkg, PCIE_RTD3_STORAGE_PROPERTY, 1); + acpi_dp_add_package(dsd, pkg); + acpi_dp_write(dsd); + + printk(BIOS_INFO, "%s.%s: Added StorageD3Enable property\n", scope, name); + } + + acpigen_write_device_end(); + acpigen_write_scope_end(); + + /* Call the default PCI acpi_fill_ssdt */ + pci_rom_ssdt(dev); +} + +static const char *pcie_rtd3_device_acpi_name(const struct device *dev) +{ + const struct drivers_pcie_rtd3_device_config *config = config_of(dev); + + return config->name; +} + +static struct device_operations pcie_rtd3_device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = pci_dev_init, + .ops_pci = &pci_dev_ops_pci, + .write_acpi_tables = pci_rom_write_acpi_tables, + .acpi_fill_ssdt = pcie_rtd3_device_acpi_fill_ssdt, + .acpi_name = pcie_rtd3_device_acpi_name, +}; + +static void pcie_rtd3_device_enable(struct device *dev) +{ + struct drivers_pcie_rtd3_device_config *config = dev ? dev->chip_info : NULL; + + if (!config) + return; + + if (dev->path.type != DEVICE_PATH_PCI) { + printk(BIOS_ERR, "%s: Invalid device type\n", dev_path(dev)); + return; + } + + dev->ops = &pcie_rtd3_device_ops; +} + +struct chip_operations drivers_pcie_rtd3_device_ops = { + CHIP_NAME("PCIe Device w/ Runtime D3") + .enable_dev = pcie_rtd3_device_enable +}; diff --git a/src/drivers/pcie/rtd3/device/chip.h b/src/drivers/pcie/rtd3/device/chip.h new file mode 100644 index 0000000..e1a8aa7 --- /dev/null +++ b/src/drivers/pcie/rtd3/device/chip.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __DRIVERS_PCIE_RTD3_DEVICE_CHIP_H__ +#define __DRIVERS_PCIE_RTD3_DEVICE_CHIP_H__ + +#include <acpi/acpi_device.h> + +/* Adds a GPIO controlled ACPI PowerResource for a PCIe device. */ +struct drivers_pcie_rtd3_device_config { + /* Name of ACPI node for the device */ + const char *name; + + /* GPIO used to enable device. */ + struct acpi_gpio enable_gpio; + /* Delay to be inserted after device is enabled. */ + unsigned int enable_delay_ms; + /* Delay to be inserted after device is disabled. */ + unsigned int enable_off_delay_ms; + + /* GPIO used to take device out of reset or to put it into reset. */ + struct acpi_gpio reset_gpio; + /* Delay to be inserted after device is taken out of reset. */ + unsigned int reset_delay_ms; + /* Delay to be inserted after device is put into reset. */ + unsigned int reset_off_delay_ms; +}; + +#endif /* __DRIVERS_PCIE_RTD3_DEVICE_CHIP_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/54966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2adfc925183ff7a19ab97e89212bc87c40d552d0 Gerrit-Change-Number: 54966 Gerrit-PatchSet: 7 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-CC: Mario Limonciello <mario.limonciello(a)amd.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel: Drop unused lpss functions
by Patrick Georgi (Code Review) 07 Jun '21

07 Jun '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55226 ) Change subject: soc/intel: Drop unused lpss functions ...................................................................... soc/intel: Drop unused lpss functions This change drops the following unused lpss functions and related code: * soc_lpss_controllers_list * is_dev_lpss These functions were added to determine if a controller is LPSS for performing IRQ configuration. But, these never got used and hence are being dropped. Change-Id: I27bdfbca7c199e823a0e4fdb277e3f22fb6bae7a Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55226 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/common/block/include/intelblocks/lpss.h M src/soc/intel/common/block/lpss/lpss.c M src/soc/intel/elkhartlake/fsp_params.c M src/soc/intel/icelake/fsp_params.c M src/soc/intel/jasperlake/fsp_params.c M src/soc/intel/tigerlake/fsp_params.c 8 files changed, 0 insertions(+), 148 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 8664fe6..22329f2 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -67,22 +67,6 @@ params->SerialIoUartMode[i] = config->SerialIoUartMode[i]; } -static const pci_devfn_t serial_io_dev[] = { - PCH_DEVFN_I2C0, - PCH_DEVFN_I2C1, - PCH_DEVFN_I2C2, - PCH_DEVFN_I2C3, - PCH_DEVFN_I2C4, - PCH_DEVFN_I2C5, - PCH_DEVFN_GSPI0, - PCH_DEVFN_GSPI1, - PCH_DEVFN_GSPI2, - PCH_DEVFN_GSPI3, - PCH_DEVFN_UART0, - PCH_DEVFN_UART1, - PCH_DEVFN_UART2 -}; - __weak void mainboard_update_soc_chip_config(struct soc_intel_alderlake_config *config) { /* Override settings per board. */ @@ -334,10 +318,3 @@ { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } - -/* Return list of SOC LPSS controllers */ -const pci_devfn_t *soc_lpss_controllers_list(size_t *size) -{ - *size = ARRAY_SIZE(serial_io_dev); - return serial_io_dev; -} diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index d7772f1..49b2669 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -572,13 +572,6 @@ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } -/* Return list of SOC LPSS controllers */ -const pci_devfn_t *soc_lpss_controllers_list(size_t *size) -{ - *size = ARRAY_SIZE(serial_io_dev); - return serial_io_dev; -} - /* Handle FSP logo params */ void soc_load_logo(FSPS_UPD *supd) { diff --git a/src/soc/intel/common/block/include/intelblocks/lpss.h b/src/soc/intel/common/block/include/intelblocks/lpss.h index 8d22e7a..5cfd5c5 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpss.h +++ b/src/soc/intel/common/block/include/intelblocks/lpss.h @@ -27,13 +27,4 @@ /* Set controller power state to D0 or D3*/ void lpss_set_power_state(pci_devfn_t devfn, enum lpss_pwr_state state); -/* - * Handler to get list of LPSS controllers. The SOC is expected to send out a - * list of pci devfn for all LPSS controllers supported by the SOC. - */ -const pci_devfn_t *soc_lpss_controllers_list(size_t *size); - -/* Check if the device is a LPSS controller */ -bool is_dev_lpss(const struct device *dev); - #endif /* SOC_INTEL_COMMON_BLOCK_LPSS_H */ diff --git a/src/soc/intel/common/block/lpss/lpss.c b/src/soc/intel/common/block/lpss/lpss.c index 6e33c0f..70a5934 100644 --- a/src/soc/intel/common/block/lpss/lpss.c +++ b/src/soc/intel/common/block/lpss/lpss.c @@ -72,21 +72,3 @@ reg8 |= state; pci_s_write_config8(devfn, PME_CTRL_STATUS, reg8); } - -bool is_dev_lpss(const struct device *dev) -{ - static size_t size; - static const pci_devfn_t *lpss_devices; - - if (dev->path.type != DEVICE_PATH_PCI) - return false; - - if (!lpss_devices) - lpss_devices = soc_lpss_controllers_list(&size); - - for (int i = 0; i < size; i++) { - if (lpss_devices[i] == dev->path.pci.devfn) - return true; - } - return false; -} diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index f02d20e..611d12b 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -41,23 +41,6 @@ return ctl - 1; } -static const pci_devfn_t serial_io_dev[] = { - PCH_DEVFN_I2C0, - PCH_DEVFN_I2C1, - PCH_DEVFN_I2C2, - PCH_DEVFN_I2C3, - PCH_DEVFN_I2C4, - PCH_DEVFN_I2C5, - PCH_DEVFN_I2C6, - PCH_DEVFN_I2C7, - PCH_DEVFN_GSPI0, - PCH_DEVFN_GSPI1, - PCH_DEVFN_GSPI2, - PCH_DEVFN_UART0, - PCH_DEVFN_UART1, - PCH_DEVFN_UART2 -}; - static void parse_devicetree(FSP_S_CONFIG *params) { const struct soc_intel_elkhartlake_config *config = config_of_soc(); @@ -287,10 +270,3 @@ { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } - -/* Return list of SOC LPSS controllers */ -const pci_devfn_t *soc_lpss_controllers_list(size_t *size) -{ - *size = ARRAY_SIZE(serial_io_dev); - return serial_io_dev; -} diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index 184b9d6..395bca8 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -33,21 +33,6 @@ params->SerialIoUartMode[i] = config->SerialIoUartMode[i]; } -static const pci_devfn_t serial_io_dev[] = { - PCH_DEVFN_I2C0, - PCH_DEVFN_I2C1, - PCH_DEVFN_I2C2, - PCH_DEVFN_I2C3, - PCH_DEVFN_I2C4, - PCH_DEVFN_I2C5, - PCH_DEVFN_GSPI0, - PCH_DEVFN_GSPI1, - PCH_DEVFN_GSPI2, - PCH_DEVFN_UART0, - PCH_DEVFN_UART1, - PCH_DEVFN_UART2 -}; - /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { @@ -223,10 +208,3 @@ { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } - -/* Return list of SOC LPSS controllers */ -const pci_devfn_t *soc_lpss_controllers_list(size_t *size) -{ - *size = ARRAY_SIZE(serial_io_dev); - return serial_io_dev; -} diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index eefbf6c..dcee306 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -28,21 +28,6 @@ EOP_DXE, } EndOfPost; -static const pci_devfn_t serial_io_dev[] = { - PCH_DEVFN_I2C0, - PCH_DEVFN_I2C1, - PCH_DEVFN_I2C2, - PCH_DEVFN_I2C3, - PCH_DEVFN_I2C4, - PCH_DEVFN_I2C5, - PCH_DEVFN_GSPI0, - PCH_DEVFN_GSPI1, - PCH_DEVFN_GSPI2, - PCH_DEVFN_UART0, - PCH_DEVFN_UART1, - PCH_DEVFN_UART2 -}; - static void parse_devicetree(FSP_S_CONFIG *params) { const struct soc_intel_jasperlake_config *config = config_of_soc(); @@ -266,10 +251,3 @@ { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } - -/* Return list of SOC LPSS controllers */ -const pci_devfn_t *soc_lpss_controllers_list(size_t *size) -{ - *size = ARRAY_SIZE(serial_io_dev); - return serial_io_dev; -} diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 7c9ab88..616daa0 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -132,22 +132,6 @@ params->SerialIoUartMode[i] = config->SerialIoUartMode[i]; } -static const pci_devfn_t serial_io_dev[] = { - PCH_DEVFN_I2C0, - PCH_DEVFN_I2C1, - PCH_DEVFN_I2C2, - PCH_DEVFN_I2C3, - PCH_DEVFN_I2C4, - PCH_DEVFN_I2C5, - PCH_DEVFN_GSPI0, - PCH_DEVFN_GSPI1, - PCH_DEVFN_GSPI2, - PCH_DEVFN_GSPI3, - PCH_DEVFN_UART0, - PCH_DEVFN_UART1, - PCH_DEVFN_UART2 -}; - __weak void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *config) { /* Override settings per board. */ @@ -483,10 +467,3 @@ { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } - -/* Return list of SOC LPSS controllers */ -const pci_devfn_t *soc_lpss_controllers_list(size_t *size) -{ - *size = ARRAY_SIZE(serial_io_dev); - return serial_io_dev; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/55226 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27bdfbca7c199e823a0e4fdb277e3f22fb6bae7a Gerrit-Change-Number: 55226 Gerrit-PatchSet: 3 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: payloads/tianocore: Fix orphaned reference to 'bootloader' variable
by Patrick Georgi (Code Review) 07 Jun '21

07 Jun '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55239 ) Change subject: payloads/tianocore: Fix orphaned reference to 'bootloader' variable ...................................................................... payloads/tianocore: Fix orphaned reference to 'bootloader' variable commit d3b49b4 [payloads/Tianocore: Update default build target, simplify build options] simplified the build string and removed the bootloader Makefile variable, but one reference was missed. Luckily the variable being empty didn't break things, but correct it regardless. Change-Id: If37b291dda59c20bfe4c6e5b9100fac52d11a2f4 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55239 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M payloads/external/tianocore/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile index e23d946..92a809a 100644 --- a/payloads/external/tianocore/Makefile +++ b/payloads/external/tianocore/Makefile @@ -94,7 +94,7 @@ cat ../tools_def.txt >> $(project_dir)/Conf/tools_def.txt; \ fi; \ build $(BUILD_STR); \ - mv $(project_dir)/Build/$(bootloader)*/*/FV/UEFIPAYLOAD.fd $(project_dir)/Build/UEFIPAYLOAD.fd; \ + mv $(project_dir)/Build/UefiPayloadPkg*/*/FV/UEFIPAYLOAD.fd $(project_dir)/Build/UEFIPAYLOAD.fd; \ git checkout MdeModulePkg/Logo/Logo.bmp > /dev/null 2>&1 || true clean: -- To view, visit https://review.coreboot.org/c/coreboot/+/55239 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If37b291dda59c20bfe4c6e5b9100fac52d11a2f4 Gerrit-Change-Number: 55239 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: sb/intel/bd82x6x: Add missing ID for PCI bridge
by James (Code Review) 07 Jun '21

07 Jun '21

James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41015 ) Change subject: sb/intel/bd82x6x: Add missing ID for PCI bridge ...................................................................... sb/intel/bd82x6x: Add missing ID for PCI bridge The PCI device ID 0x244e for the "Intel Corporation 82801 PCI Bridge" was missing. Change-Id: I22cdbcf518d86af7b93de7731d175088a81bbc1f Signed-off-by: James Ye <jye836(a)gmail.com> --- M src/southbridge/intel/bd82x6x/pci.c 1 file changed, 9 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/41015/1 diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c index 459ed46..757bdeb 100644 --- a/src/southbridge/intel/bd82x6x/pci.c +++ b/src/southbridge/intel/bd82x6x/pci.c @@ -58,8 +58,14 @@ .ops_pci = &pci_ops, }; +static const unsigned short pci_device_ids[] = { + 0x244e, /* Desktop */ + 0x2448, /* Mobile */ + 0 +}; + static const struct pci_driver pch_pci __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x2448, + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/41015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22cdbcf518d86af7b93de7731d175088a81bbc1f Gerrit-Change-Number: 41015 Gerrit-PatchSet: 1 Gerrit-Owner: James <jye836(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/bd82x6x: Use array for PCIe ASPM overrides
by Patrick Georgi (Code Review) 07 Jun '21

07 Jun '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55246 ) Change subject: sb/intel/bd82x6x: Use array for PCIe ASPM overrides ...................................................................... sb/intel/bd82x6x: Use array for PCIe ASPM overrides Using an array reduces the amount of boilerplate code. Change-Id: Ic6a48a01d3b96e69273dc28bdb6699ce7c0931b2 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55246 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/butterfly/devicetree.cb M src/mainboard/google/stout/devicetree.cb M src/southbridge/intel/bd82x6x/chip.h M src/southbridge/intel/bd82x6x/pcie.c 4 files changed, 4 insertions(+), 36 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Michael Niewöhner: Looks good to me, approved diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index 9dee30f..725cbd1 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -72,7 +72,7 @@ device pci 1c.1 on end # PCIe Port #2 (ETH0) device pci 1c.2 on end # PCIe Port #3 (Card Reader) #force ASPM for PCIe bridge to Card Reader - register "pcie_aspm_f2" = "0x3" + register "pcie_aspm[2]" = "0x3" device pci 1c.3 off end # PCIe Port #4 device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 1ec596e..914ab60 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -76,7 +76,7 @@ device pci 1c.0 on end # PCIe Port #1 device pci 1c.1 on end # PCIe Port #2 (WLAN) device pci 1c.2 on end # PCIe Port #3 (Card Reader) - register "pcie_aspm_f2" = "0x3" + register "pcie_aspm[2]" = "0x3" device pci 1c.3 off end # PCIe Port #4 device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 on end # PCIe Port #6 (LAN) diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 45f1226..ac29944 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -61,14 +61,7 @@ uint8_t pcie_port_coalesce; /* Override PCIe ASPM */ - uint8_t pcie_aspm_f0; - uint8_t pcie_aspm_f1; - uint8_t pcie_aspm_f2; - uint8_t pcie_aspm_f3; - uint8_t pcie_aspm_f4; - uint8_t pcie_aspm_f5; - uint8_t pcie_aspm_f6; - uint8_t pcie_aspm_f7; + uint8_t pcie_aspm[8]; int c2_latency; int docking_supported; diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 8513390..399c73a 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -162,32 +162,7 @@ pci_or_config32(dev, 0xd4, 1 << 1); /* Check for a rootport ASPM override */ - switch (PCI_FUNC(dev->path.pci.devfn)) { - case 0: - apmc = config->pcie_aspm_f0; - break; - case 1: - apmc = config->pcie_aspm_f1; - break; - case 2: - apmc = config->pcie_aspm_f2; - break; - case 3: - apmc = config->pcie_aspm_f3; - break; - case 4: - apmc = config->pcie_aspm_f4; - break; - case 5: - apmc = config->pcie_aspm_f5; - break; - case 6: - apmc = config->pcie_aspm_f6; - break; - case 7: - apmc = config->pcie_aspm_f7; - break; - } + apmc = config->pcie_aspm[PCI_FUNC(dev->path.pci.devfn)]; /* Setup the override or get the real ASPM setting */ if (apmc) { -- To view, visit https://review.coreboot.org/c/coreboot/+/55246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6a48a01d3b96e69273dc28bdb6699ce7c0931b2 Gerrit-Change-Number: 55246 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit June 2021