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Change in ...coreboot[master]: mb/lenovo/x131e: function key support
by James (Code Review) 07 Aug '23

07 Aug '23

James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31067 Change subject: mb/lenovo/x131e: function key support ...................................................................... mb/lenovo/x131e: function key support Enables function keys for X131e. The IT8518e EC of this board uses some different ACPI methods compared to the regular Lenovo H8. Add an option to use the alternative set of methods. Change-Id: Ib3a01f37a8b54889b55e92c501c9350e6c68bd57 Signed-off-by: James Ye <jye836(a)gmail.com> --- M src/ec/lenovo/h8/Kconfig M src/ec/lenovo/h8/acpi/ec.asl M src/mainboard/lenovo/x131e/Kconfig M src/mainboard/lenovo/x131e/Makefile.inc M src/mainboard/lenovo/x131e/devicetree.cb A src/mainboard/lenovo/x131e/ec.h M src/mainboard/lenovo/x131e/mainboard.c M src/mainboard/lenovo/x131e/romstage.c A src/mainboard/lenovo/x131e/smihandler.c 9 files changed, 146 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/31067/1 diff --git a/src/ec/lenovo/h8/Kconfig b/src/ec/lenovo/h8/Kconfig index f9b0b14..3dab615 100644 --- a/src/ec/lenovo/h8/Kconfig +++ b/src/ec/lenovo/h8/Kconfig @@ -28,6 +28,12 @@ Disable BDC detection and assume bluetooth is installed. Required for bluetooth on wifi cards, as it's not possible to detect it in coreboot. +config H8_ALT_EC_QUERY + bool "Alternate ACPI EC query methods" + default n + help + Use alternative EC query methods for X131e + endif config H8_DOCK_EARLY_INIT diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl index 327a2cf..7c96504 100644 --- a/src/ec/lenovo/h8/acpi/ec.asl +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -140,7 +140,11 @@ /* Sleep Button pressed */ Method(_Q13, 0, NotSerialized) { +#ifndef CONFIG_H8_ALT_EC_QUERY Notify(^SLPB, 0x80) +#else + ^HKEY.RHK(0x04) +#endif } /* Brightness up GPE */ @@ -217,9 +221,20 @@ Method (_Q17, 0, NotSerialized) { +#ifndef CONFIG_H8_ALT_EC_QUERY ^HKEY.RHK (0x08) +#else + BRIGHTNESS_DOWN() +#endif } +#ifdef CONFIG_H8_ALT_EC_QUERY + Method (_Q18, 0, NotSerialized) + { + BRIGHTNESS_UP() + } +#endif + Method (_Q66, 0, NotSerialized) { ^HKEY.RHK (0x0A) diff --git a/src/mainboard/lenovo/x131e/Kconfig b/src/mainboard/lenovo/x131e/Kconfig index 946b945..ee7a83f 100644 --- a/src/mainboard/lenovo/x131e/Kconfig +++ b/src/mainboard/lenovo/x131e/Kconfig @@ -8,6 +8,7 @@ select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_H8 + select H8_ALT_EC_QUERY select NO_UART_ON_SUPERIO select BOARD_ROMSIZE_KB_12288 select HAVE_ACPI_TABLES diff --git a/src/mainboard/lenovo/x131e/Makefile.inc b/src/mainboard/lenovo/x131e/Makefile.inc index 7a00cce..2dab950 100644 --- a/src/mainboard/lenovo/x131e/Makefile.inc +++ b/src/mainboard/lenovo/x131e/Makefile.inc @@ -13,6 +13,7 @@ ## GNU General Public License for more details. ## +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index 3d0148f..0a73010 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -47,7 +47,8 @@ chip southbridge/intel/bd82x6x # GPI routing - register "alt_gp_smi_en" = "0x0000" + register "alt_gp_smi_en" = "0x0002" + register "gpi1_routing" = "1" register "gpi6_routing" = "2" register "gpi13_routing" = "2" @@ -115,22 +116,10 @@ register "beepmask1" = "0x87" register "has_power_management_beeps" = "0" - register "event0_enable" = "0xff" - register "event1_enable" = "0xff" - register "event2_enable" = "0xff" - register "event3_enable" = "0xff" - register "event4_enable" = "0xff" - register "event5_enable" = "0xff" - register "event6_enable" = "0xff" - register "event7_enable" = "0xff" - register "event8_enable" = "0xff" - register "event9_enable" = "0xff" - register "eventa_enable" = "0xff" - register "eventb_enable" = "0xff" - register "eventc_enable" = "0xff" - register "eventd_enable" = "0xff" - register "evente_enable" = "0xff" - register "eventf_enable" = "0xff" + register "event2_enable" = "0xc8" # sleep, monitor, brightness down + register "event3_enable" = "0x01" # brightness up + register "eventc_enable" = "0x30" # airplane, camera + register "eventd_enable" = "0x04" # mic register "has_bdc_detection" = "0" diff --git a/src/mainboard/lenovo/x131e/ec.h b/src/mainboard/lenovo/x131e/ec.h new file mode 100644 index 0000000..4a731dc --- /dev/null +++ b/src/mainboard/lenovo/x131e/ec.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2019 James Ye <jye836(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef X131E_EC_H +#define X131E_EC_H + +#define GPE_EC_SCI 6 +#define GPE_EC_WAKE 13 + +#define EC_CMD_NOTIFY_ACPI_ENTER 0x86 +#define EC_CMD_NOTIFY_ACPI_EXIT 0x87 + +#endif // X131E_EC_H diff --git a/src/mainboard/lenovo/x131e/mainboard.c b/src/mainboard/lenovo/x131e/mainboard.c index 1342aca..9e6a7dd 100644 --- a/src/mainboard/lenovo/x131e/mainboard.c +++ b/src/mainboard/lenovo/x131e/mainboard.c @@ -13,9 +13,17 @@ * GNU General Public License for more details. */ +#include <arch/acpi.h> #include <device/device.h> #include <drivers/intel/gma/int15.h> +#include <ec/acpi/ec.h> #include <ec/lenovo/h8/h8.h> +#include "ec.h" + +void mainboard_suspend_resume(void) +{ + send_ec_command(EC_CMD_NOTIFY_ACPI_ENTER); +} static void mainboard_enable(struct device *dev) { diff --git a/src/mainboard/lenovo/x131e/romstage.c b/src/mainboard/lenovo/x131e/romstage.c index 43e0bd7..30df36f 100644 --- a/src/mainboard/lenovo/x131e/romstage.c +++ b/src/mainboard/lenovo/x131e/romstage.c @@ -26,11 +26,6 @@ /* Enable TPM, EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); - - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c1611); - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x00040069); - pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x000c0701); - pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x000c06a1); } void mainboard_rcba_config(void) diff --git a/src/mainboard/lenovo/x131e/smihandler.c b/src/mainboard/lenovo/x131e/smihandler.c new file mode 100644 index 0000000..a634359 --- /dev/null +++ b/src/mainboard/lenovo/x131e/smihandler.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2019 James Ye <jye836(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <ec/acpi/ec.h> +#include <ec/lenovo/h8/h8.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/pmutil.h> +#include "ec.h" + +static void mainboard_smi_handle_ec_sci(void) +{ + u8 status = ec_status(); + if (!(status & EC_SCI_EVT)) + return; + + u8 event = ec_query(); + printk(BIOS_DEBUG, "EC event %02x\n", event); +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << GPE_EC_SCI)) + mainboard_smi_handle_ec_sci(); +} + +int mainboard_smi_apmc(u8 data) +{ + switch (data) { + case APM_CNT_ACPI_ENABLE: + send_ec_command(EC_CMD_NOTIFY_ACPI_ENTER); + /* use 0x1600/0x1604 to prevent races with userspace */ + ec_set_ports(0x1604, 0x1600); + /* route EC_SCI to SCI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + case APM_CNT_ACPI_DISABLE: + send_ec_command(EC_CMD_NOTIFY_ACPI_EXIT); + /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't + provide a EC query function */ + ec_set_ports(EC_SC, EC_DATA); + /* route EC_SCI to SMI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + } + return 0; +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (slp_typ == 3) { + u8 ec_wake = ec_read(0x32); + /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ + if (ec_wake & 0x14) { + /* Redirect EC WAKE GPE to SCI. */ + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); + } + } + + //outb(0xe9, 0x64); // EC_KBD_CMD_MUTE + //ec_set_bit(0xbf, 4); // EC_WAKE_SRC_ENABLE, EC_LID_WAKE_ENABLE +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31067 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3a01f37a8b54889b55e92c501c9350e6c68bd57 Gerrit-Change-Number: 31067 Gerrit-PatchSet: 1 Gerrit-Owner: James <jye836(a)gmail.com> Gerrit-MessageType: newchange

5 14

Change in ...coreboot[master]: skylake: Force to use single channel
by Sumeet R Pawnikar (Code Review) 07 Aug '23

07 Aug '23

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31136 Change subject: skylake: Force to use single channel ...................................................................... skylake: Force to use single channel Change-Id: I5fea8bdb14922f57d05c1388025a458451035132 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h M src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspmUpd.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/31136/1 diff --git a/src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h index fddc168..cfb336b 100644 --- a/src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h +++ b/src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h @@ -38,7 +38,7 @@ #define MRC_MAX_RCOMP 3 #define MRC_MAX_RCOMP_TARGETS 5 -#define MAX_CHANNELS_NUM 2 +#define MAX_CHANNELS_NUM 1 #define MAX_DIMMS_NUM 2 typedef struct { diff --git a/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspmUpd.h index 3aa74a0..b4ba865 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspmUpd.h @@ -37,7 +37,7 @@ #pragma pack(1) -#define MAX_CH 2 /* Maximum Number of Memory Channels */ +#define MAX_CH 1 /* Maximum Number of Memory Channels */ #define MAX_DIMM 2 /* Maximum Number of DIMMs PER Memory Channel */ #define MAX_SPD_BYTES 512 /* Maximum Number of SPD bytes */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31136 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5fea8bdb14922f57d05c1388025a458451035132 Gerrit-Change-Number: 31136 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

6 8

Change in ...coreboot[master]: ec/quanta/it8518: Use ACPI EC code
by James (Code Review) 07 Aug '23

07 Aug '23

James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31382 Change subject: ec/quanta/it8518: Use ACPI EC code ...................................................................... ec/quanta/it8518: Use ACPI EC code ec/quanta/it8518 implements its own code for reading and writing the EC. As a result, it cannot be used with ec/acpi. ec/quanta/it8518 contains definitions that are useful for mb/thinkpad/x131e, however, x131e uses ec/acpi. This replaces functions and definitions in ec/quanta/it8518 with their equivalents in ec/acpi. TODO: test on google/stout Change-Id: I7bea7445f34817cef1602843bbded59230bb8d47 Signed-off-by: James Ye <jye836(a)gmail.com> --- M src/ec/quanta/it8518/Kconfig M src/ec/quanta/it8518/ec.c M src/ec/quanta/it8518/ec.h M src/mainboard/google/stout/chromeos.c M src/mainboard/google/stout/ec.c M src/mainboard/google/stout/mainboard.c M src/mainboard/google/stout/mainboard_smi.c M src/mainboard/google/stout/romstage.c 8 files changed, 17 insertions(+), 59 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/31382/1 diff --git a/src/ec/quanta/it8518/Kconfig b/src/ec/quanta/it8518/Kconfig index 24ac36f..caaccd5 100644 --- a/src/ec/quanta/it8518/Kconfig +++ b/src/ec/quanta/it8518/Kconfig @@ -1,4 +1,5 @@ config EC_QUANTA_IT8518 + select EC_ACPI bool help Interface to QUANTA IT8518 Embedded Controller. diff --git a/src/ec/quanta/it8518/ec.c b/src/ec/quanta/it8518/ec.c index e293f7c..a27e7b9 100644 --- a/src/ec/quanta/it8518/ec.c +++ b/src/ec/quanta/it8518/ec.c @@ -19,6 +19,7 @@ #include <delay.h> #include <device/device.h> #include <device/pnp.h> +#include <ec/acpi/ec.h> #include <pc80/keyboard.h> #include <stdlib.h> @@ -93,48 +94,16 @@ * These functions are for accessing the IT8518 device RAM space via 0x66/0x68 */ -u8 ec_read_ob(void) -{ - if (!output_buffer_full(EC_SC)) return 0; - return inb(EC_DATA); -} - -void ec_write_cmd(u8 cmd) -{ - if (!input_buffer_empty(EC_SC)) return; - outb(cmd, EC_SC); -} - -void ec_write_ib(u8 data) -{ - if (!input_buffer_empty(EC_SC)) return; - outb(data, EC_DATA); -} - -u8 ec_read(u16 addr) -{ - ec_write_cmd(RD_EC); - ec_write_ib(addr); - return ec_read_ob(); -} - -void ec_write(u16 addr, u8 data) -{ - ec_write_cmd(WR_EC); - ec_write_ib(addr); - ec_write_ib(data); -} - #ifndef __PRE_RAM__ u8 ec_it8518_get_event(void) { u8 cmd = 0; u8 status = inb(EC_SC); - if (status & SCI_EVT) { - ec_write_cmd(QR_EC); - cmd = ec_read_ob(); - } else if (status & SMI_EVT) { + if (status & EC_SCI_EVT) { + send_ec_command(QR_EC); + cmd = recv_ec_data(); + } else if (status & EC_SMI_EVT) { ec_kbc_write_cmd(EC_KBD_SMI_EVENT); cmd = ec_kbc_read_ob(); } diff --git a/src/ec/quanta/it8518/ec.h b/src/ec/quanta/it8518/ec.h index 6fca3b9..27f9137 100644 --- a/src/ec/quanta/it8518/ec.h +++ b/src/ec/quanta/it8518/ec.h @@ -43,17 +43,6 @@ void ec_kbc_write_cmd(u8 cmd); void ec_kbc_write_ib(u8 data); -// 62h/66h Command Interface -#define EC_DATA 0x62 -#define EC_SC 0x66 // Status & Control Register -#define SMI_EVT (1 << 6) // 1: SMI event was triggered -#define SCI_EVT (1 << 5) // 1: SCI event was triggered - -// EC Commands (defined in ec_function_spec v3.12) -#define RD_EC 0x80 -#define WR_EC 0x81 -#define QR_EC 0x84 - #define EC_CMD_EXIT_BOOT_BLOCK 0x85 #define EC_CMD_NOTIFY_ACPI_ENTER 0x86 #define EC_CMD_NOTIFY_ACPI_EXIT 0x87 @@ -63,13 +52,13 @@ #define EC_PERIPH_CNTL_3 0x0D #define EC_USB_S3_EN 0x26 #define EC_PERIPH_STAT_3 0x35 +#define EC_MBAT_STATUS 0x38 #define EC_THERM_0 0x78 #define EC_WAKE_SRC_ENABLE 0xBF #define EC_FW_VER 0xE8 // 2 Bytes #define EC_IF_MIN_VER 0xEB #define EC_STATUS_REG 0xEC #define EC_IF_MAJ_VER 0xEF -#define EC_MBAT_STATUS 0x0138 // EC 0.83b added status bits: @@ -81,12 +70,6 @@ // EC 0.86a added enable bit: #define EC_LID_WAKE_ENABLE 0x4 -u8 ec_read_ob(void); -void ec_write_cmd(u8 cmd); -void ec_write_ib(u8 data); - -u8 ec_read(u16 addr); -void ec_write(u16 addr, u8 data); u8 ec_it8518_get_event(void); void ec_it8518_enable_wake_events(void); diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 5301d30..f7f54c1 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -24,6 +24,7 @@ #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" +#include <ec/acpi/ec.h> #include <ec/quanta/it8518/ec.h> #ifndef __PRE_RAM__ diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c index 229f919..11cdc2a 100644 --- a/src/mainboard/google/stout/ec.c +++ b/src/mainboard/google/stout/ec.c @@ -18,6 +18,7 @@ #include <bootmode.h> #include <types.h> #include <console/console.h> +#include <ec/acpi/ec.h> #include <ec/quanta/it8518/ec.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c index b63083f..63cc67b 100644 --- a/src/mainboard/google/stout/mainboard.c +++ b/src/mainboard/google/stout/mainboard.c @@ -29,13 +29,14 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <smbios.h> #include <device/pci.h> +#include <ec/acpi/ec.h> #include <ec/quanta/it8518/ec.h> #include <vendorcode/google/chromeos/chromeos.h> void mainboard_suspend_resume(void) { /* Stout EC needs to be put back in ACPI mode */ - ec_write_cmd(EC_CMD_NOTIFY_ACPI_ENTER); + send_ec_command(EC_CMD_NOTIFY_ACPI_ENTER); } diff --git a/src/mainboard/google/stout/mainboard_smi.c b/src/mainboard/google/stout/mainboard_smi.c index 6a51645..27eae19 100644 --- a/src/mainboard/google/stout/mainboard_smi.c +++ b/src/mainboard/google/stout/mainboard_smi.c @@ -24,6 +24,7 @@ #include <cpu/intel/model_206ax/model_206ax.h> /* Include EC functions */ +#include <ec/acpi/ec.h> #include <ec/quanta/it8518/ec.h> #include "ec.h" @@ -96,13 +97,13 @@ /* * TODO(kimarie) Clear all pending events and enable SCI. */ - ec_write_cmd(EC_CMD_NOTIFY_ACPI_ENTER); + send_ec_command(EC_CMD_NOTIFY_ACPI_ENTER); break; case APMC_ACPI_DIS: /* * TODO(kimarie) Clear all pending events and enable SMI. */ - ec_write_cmd(EC_CMD_NOTIFY_ACPI_EXIT); + send_ec_command(EC_CMD_NOTIFY_ACPI_EXIT); break; } return 0; diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index d212951..66eb953 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -29,6 +29,7 @@ #include <southbridge/intel/common/gpio.h> #include <halt.h> #include <bootmode.h> +#include <ec/acpi/ec.h> #include <ec/quanta/it8518/ec.h> #include "ec.h" #include "onboard.h" @@ -121,12 +122,12 @@ * Tell EC to exit RO mode */ printk(BIOS_DEBUG, "EC will exit RO mode and boot normally\n"); - ec_write_cmd(EC_CMD_EXIT_BOOT_BLOCK); + send_ec_command(EC_CMD_EXIT_BOOT_BLOCK); die("wait for ec to reset"); } } else { printk(BIOS_DEBUG, "EC Warm Boot Detected\n"); - ec_write_cmd(EC_CMD_WARM_RESET); + send_ec_command(EC_CMD_WARM_RESET); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/31382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bea7445f34817cef1602843bbded59230bb8d47 Gerrit-Change-Number: 31382 Gerrit-PatchSet: 1 Gerrit-Owner: James <jye836(a)gmail.com> Gerrit-MessageType: newchange

4 9

Change in ...coreboot[master]: Patch SSDTs into qemu, and add VPD area to the fmap for q35 as a proo...
by John Looney (Code Review) 07 Aug '23

07 Aug '23

John Looney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32087 Change subject: Patch SSDTs into qemu, and add VPD area to the fmap for q35 as a proof of concept ...................................................................... Patch SSDTs into qemu, and add VPD area to the fmap for q35 as a proof of concept Signed-off-by: John Looney <john.looney(a)gmail.com> Change-Id: I4678b9adc8044a691c818527e2c16205f9b259e2 --- A src/mainboard/emulation/qemu-q35/board.fmd 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/32087/1 diff --git a/src/mainboard/emulation/qemu-q35/board.fmd b/src/mainboard/emulation/qemu-q35/board.fmd new file mode 100644 index 0000000..a97e218 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/board.fmd @@ -0,0 +1,16 @@ +# layout for firmware residing at top of 4GB address space +# +-------------+ <-- 4GB - ROM_SIZE / start of flash +# | unspecified | +# +-------------+ <-- 4GB - BIOS_SIZE +# | FMAP | +# +-------------+ <-- 4GB - BIOS_SIZE + FMAP_SIZE +# | CBFS | +# +-------------+ <-- 4GB / end of flash +FLASH@4278190080 0x1000000 { + BIOS@0 0x1000000 { + FMAP@0 0x200 + RO_VPD@0x200 0x10000 + RW_VPD@0x10200 0x1000 + COREBOOT(CBFS)@0x11200 + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4678b9adc8044a691c818527e2c16205f9b259e2 Gerrit-Change-Number: 32087 Gerrit-PatchSet: 1 Gerrit-Owner: John Looney <john.looney(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/arch: This is an upgrade of SMBIOS to latest version 3.2
by Francois Toguo Fotso (Code Review) 07 Aug '23

07 Aug '23

Francois Toguo Fotso has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32090 Change subject: src/arch: This is an upgrade of SMBIOS to latest version 3.2 ...................................................................... src/arch: This is an upgrade of SMBIOS to latest version 3.2 This is the second of 2 patches upgrading the SMBIOS interface to the latest 3.2 First patch is in mosys. Newer required fields are added to various types definitions BUG=NONE TEST=Boot to OS on GLK Sparky Change-Id: I1171c20ac85a2231d949d4ac1c3e3c544ba3e5ef Signed-off-by: Francois Toguo <francois.toguo.fotso(a)intel.com> --- M src/arch/x86/smbios.c M src/include/smbios.h 2 files changed, 71 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/32090/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 8cb59df..b82780d 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -328,6 +328,17 @@ t->handle = *handle; *handle += 1; t->length = sizeof(struct smbios_type17) - 2; + t->memory_technology = MEMORY_TECHNOLOGY_UNKNOWN; + t->operating_mode_capability = MEMORY_OPERATING_MODE_CAP_UNKNOWN; + t->fw_version = 0xff; + t->manufacturer_id = dimm->mod_id; + t->product_id = 0x0000; + t->sub_ctrl_manufacturer_id = 0x0000; + t->sub_ctrl_product_id = 0x0000; + t->non_volatile_size = 0xffffffffffffffff; + t->volatile_size = 0xffffffffffffffff; + t->cache_size = 0xffffffffffffffff; + t->logical_size = 0xffffffffffffffff; return t->length + smbios_string_table_len(t->eos); } @@ -547,9 +558,31 @@ return len; } +u16 __weak smbios_processor_core_thread_count(u16 level_type) +{ + u16 count = 0; + int ecx = 0; + + for (ecx = 0 ; ecx < 255 ; ecx++) { + struct cpuid_result leaf_b; + leaf_b = cpuid_ext(0xb, ecx); + if ((cpuid_eax(0) < 0xb) || + !(leaf_b.eax | leaf_b.ebx | leaf_b.ecx | leaf_b.edx)) + return (((cpuid(1).ebx) >> 16) & 0x00ff); + + if ((leaf_b.ecx & 0xff00) == level_type) { + count = leaf_b.ebx & 0xffff; + break; + } + } + + return count; +} + static int smbios_write_type4(unsigned long *current, int handle) { struct cpuid_result res; + u16 core_count = 0, thread_count = 0; struct smbios_type4 *t = (struct smbios_type4 *)*current; int len = sizeof(struct smbios_type4); @@ -570,7 +603,15 @@ t->processor_version = smbios_processor_name(t->eos); t->processor_family = (res.eax > 0) ? 0x0c : 0x6; t->processor_type = 3; /* System Processor */ - t->core_count = (res.ebx >> 16) & 0xff; + + core_count = smbios_processor_core_thread_count(PROC_CORE_TYPE); + thread_count = smbios_processor_core_thread_count(PROC_THREAD_TYPE); + t->core_count2 = core_count; + t->core_count = (core_count > BYTE_LIMIT) ? 0xff : core_count; + t->thread_count2 = thread_count; + t->thread_count = (thread_count > BYTE_LIMIT) ? 0xff : core_count; + t->core_enabled2 = core_count; + t->l1_cache_handle = 0xffff; t->l2_cache_handle = 0xffff; t->l3_cache_handle = 0xffff; diff --git a/src/include/smbios.h b/src/include/smbios.h index af83bfe..e1d71be 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -52,6 +52,10 @@ u8 smbios_mainboard_feature_flags(void); const char *smbios_mainboard_location_in_chassis(void); u8 smbios_mainboard_enclosure_type(void); +u16 smbios_processor_core_thread_count(u16 level_type); +#ifdef CONFIG_MAINBOARD_FAMILY +const char *smbios_mainboard_family(void); +#endif #define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7) #define BIOS_CHARACTERISTICS_PC_CARD (1 << 8) @@ -100,6 +104,11 @@ #define MEMORY_OPERATING_MODE_CAP_BYTE_ACCESS_PERSISTENT (1 << 4) #define MEMORY_OPERATING_MODE_CAP_BLOCK_ACCESS_PERSISTENT (1 << 5) +#define PROC_THREAD_TYPE 0x1 +#define PROC_CORE_TYPE 0x2 + +#define BYTE_LIMIT 255 + typedef enum { MEMORY_BUS_WIDTH_8 = 0, MEMORY_BUS_WIDTH_16 = 1, @@ -299,6 +308,7 @@ u8 location_in_chassis; u16 chassis_handle; u8 board_type; + u8 num_cont_obj_handles; u8 eos[2]; } __packed; @@ -390,6 +400,9 @@ u8 thread_count; u16 processor_characteristics; u16 processor_family2; + u16 core_count2; + u16 core_enabled2; + u16 thread_count2; u8 eos[2]; } __packed; @@ -401,6 +414,11 @@ u8 eos[2]; } __packed; +typedef struct { + u8 type; + u8 format_descriptor; +} log_type_descriptor; + struct smbios_type15 { u8 type; u8 length; @@ -471,6 +489,17 @@ u16 minimum_voltage; u16 maximum_voltage; u16 configured_voltage; + u8 memory_technology; + u16 operating_mode_capability; + u8 fw_version; + u16 manufacturer_id; + u16 product_id; + u16 sub_ctrl_manufacturer_id; + u16 sub_ctrl_product_id; + u64 non_volatile_size; + u64 volatile_size; + u64 cache_size; + u64 logical_size; u8 eos[2]; } __packed; -- To view, visit https://review.coreboot.org/c/coreboot/+/32090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1171c20ac85a2231d949d4ac1c3e3c544ba3e5ef Gerrit-Change-Number: 32090 Gerrit-PatchSet: 1 Gerrit-Owner: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-MessageType: newchange

8 52

Change in ...coreboot[master]: Documentation: Document PMH known registers
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32253 Change subject: Documentation: Document PMH known registers ...................................................................... Documentation: Document PMH known registers Document what is known of Lenovo's PMH. Change-Id: I1891a6370123d9ee29d9e37e4b7b78b677343aed Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/pmh.md 2 files changed, 70 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/32253/1 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index d94c23e..adfe877 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -54,6 +54,7 @@ - [Hardware Maintenance Manual of ThinkPads](lenovo/thinkpad_hmm.md) - [T4xx common](lenovo/t4xx_series.md) - [X2xx common](lenovo/x2xx_series.md) +- [PMH](lenovo/pmh.md) ### Sandy Bridge series diff --git a/Documentation/mainboard/lenovo/pmh.md b/Documentation/mainboard/lenovo/pmh.md new file mode 100644 index 0000000..06c595d --- /dev/null +++ b/Documentation/mainboard/lenovo/pmh.md @@ -0,0 +1,69 @@ +# Lenovo's Power Management Hub + +The *Power Management Hub* or *PMH* originally was a CPLD connected to the EC +to controll power rails and reset lines on the lenovo mainboard. +Starting with Ivy Bridge series, the CPLD was removed and an EC with higher +pincount does the same job. The IO space to configure the PMH is still +the same. + +## PMH access + +The PMH register can be accessed using the IO region: + + IO region address: 0x15e0 + IO region size: 16 + +The IO region has the following layout: + +```eval_rst ++-------------------+---------------------------------------+ +| Offset | Register function | ++-------------------+---------------------------------------+ +| 0xc | ADDR_L: Low address into PMH space | ++-------------------+---------------------------------------+ +| 0xd | ADDR_H: High address into PMH space | ++-------------------+---------------------------------------+ +| 0xe | DATA: The data to read/write in PMH | ++-------------------+---------------------------------------+ +``` + +The PMH register space allows to access 512bytes. +The following registers are known: + +```eval_rst ++-------------------+---------------------------------------+ +| Offset | Register function | ++-------------------+---------------------------------------+ +| 0x50 | BIT3: dGPU power enable | +| +---------------------------------------+ +| | BIT5: Backlight enable | +| +---------------------------------------+ +| | BIT7: dGPU !reset | ++-------------------+---------------------------------------+ +| 0x51 | BIT0: Trackpoint enable | +| +---------------------------------------+ +| | BIT2: Touchpad enable | ++-------------------+---------------------------------------+ +| 0x60 | BIT3: Dock event enable | ++-------------------+---------------------------------------+ +| 0x62 | BIT0: Ultrabay power enable | ++-------------------+---------------------------------------+ +| 0xc2 | ID: ID of PMH | ++-------------------+---------------------------------------+ +| 0xc3 | REV: Revision of PMH | ++-------------------+---------------------------------------+ +``` + +The revision at 0xc3 seems to increment over time: + +```eval_rst ++-------------------+---------------------------------------+ +| Revision | Mainboard generation | ++-------------------+---------------------------------------+ +| 4 | T520 and T420s | ++-------------------+---------------------------------------+ +| 5 | W530 | ++-------------------+---------------------------------------+ +| 6 | T470p | ++-------------------+---------------------------------------+ +``` -- To view, visit https://review.coreboot.org/c/coreboot/+/32253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1891a6370123d9ee29d9e37e4b7b78b677343aed Gerrit-Change-Number: 32253 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Supplement motherboard name for G41M-GS
by Pixie (Code Review) 07 Aug '23

07 Aug '23

Pixie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32372 Change subject: Supplement motherboard name for G41M-GS ...................................................................... Supplement motherboard name for G41M-GS A few months ago, Arthur Heymans rebased a few patches to add support for the G41M-GS to aid me in testing my G41M-S. The two boards are exact duplicates, save for the -GS having a gigabit LAN chip, and the G41M-S having a 100Mbit one. I did some scant testing, and it worked, but I had a lot of other projects ongoing. Now that I remembered thisagain, I'm here to commit the motherboard name. Signed-off-by: Cheetah Pixie <mayulithsv(a)gmail.com> Change-Id: I97f77ec2c8cbd9c2f13e6890257cb7c5b1c77311 --- M src/mainboard/asrock/g41c-gs/Kconfig.name 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/32372/1 diff --git a/src/mainboard/asrock/g41c-gs/Kconfig.name b/src/mainboard/asrock/g41c-gs/Kconfig.name index 86a41aa..1a090ff3 100644 --- a/src/mainboard/asrock/g41c-gs/Kconfig.name +++ b/src/mainboard/asrock/g41c-gs/Kconfig.name @@ -5,7 +5,7 @@ bool "G41C-GS / G41C-S" config BOARD_ASROCK_G41M_GS - bool "G41M-GS" + bool "G41M-GS / G41M-S" config BOARD_ASROCK_G41M_S3 bool "G41M-S3" -- To view, visit https://review.coreboot.org/c/coreboot/+/32372 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97f77ec2c8cbd9c2f13e6890257cb7c5b1c77311 Gerrit-Change-Number: 32372 Gerrit-PatchSet: 1 Gerrit-Owner: Pixie <mayulithsv(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: CML: Enable UPDs for PCH SLP_S0 for S0ix entry
by Sumeet R Pawnikar (Code Review) 07 Aug '23

07 Aug '23

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32668 Change subject: CML: Enable UPDs for PCH SLP_S0 for S0ix entry ...................................................................... CML: Enable UPDs for PCH SLP_S0 for S0ix entry Enable PCH SLP S0 UPDs for S0ix entry. BUG=None BRANCH=None TEST=Built and tested on Hatch Change-Id: I57a15746705a726b402431321a45b3257d837faa --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/32668/1 diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index cc01d10..796b717 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -177,9 +177,9 @@ params->PchLanEnable = dev->enabled; if (config->s0ix_enable) { params->SlpS0WithGbeSupport = 1; - params->PchPmSlpS0VmRuntimeControl = 0; - params->PchPmSlpS0Vm070VSupport = 0; - params->PchPmSlpS0Vm075VSupport = 0; + params->PchPmSlpS0VmRuntimeControl = 1; + params->PchPmSlpS0Vm070VSupport = 1; + params->PchPmSlpS0Vm075VSupport = 1; ignore_gbe_ltr(); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/32668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57a15746705a726b402431321a45b3257d837faa Gerrit-Change-Number: 32668 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

2 3

Change in ...coreboot[master]: WIP: google/flapjack: Add Panels support
by Jerry Han (Code Review) 07 Aug '23

07 Aug '23

Jerry Han has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32840 Change subject: WIP: google/flapjack: Add Panels support ...................................................................... WIP: google/flapjack: Add Panels support Add panel BOE_TV101WUM_NG0, BOE_TV080WUM_NG0, INX_OTA7290D10P, AUO_NT51021D8P for FLAPJACK. Change-Id: I3e50df59de3db9ed6efcccbd01b553c21f793a3f Signed-off-by: Jerry Han <hanxu5(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/kukui/Makefile.inc M src/mainboard/google/kukui/display.c M src/mainboard/google/kukui/display.h A src/mainboard/google/kukui/panel_flapjack.c 4 files changed, 1,112 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/32840/1 diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index 9576b7d..a91f91e7 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -25,6 +25,7 @@ ramstage-y += display.c ramstage-y += panel_kukui.c ramstage-y += panel_krane.c +ramstage-y += panel_flapjack.c ramstage-y += mainboard.c ramstage-y += memlayout.ld ramstage-y += reset.c diff --git a/src/mainboard/google/kukui/display.c b/src/mainboard/google/kukui/display.c index b0a5026..55e129b 100644 --- a/src/mainboard/google/kukui/display.c +++ b/src/mainboard/google/kukui/display.c @@ -99,6 +99,8 @@ return &kukui_display_intf; else if (CONFIG(BOARD_GOOGLE_KRANE)) return &krane_display_intf; + else if (CONFIG(BOARD_GOOGLE_FLAPJACK)) + return &flapjack_display_intf; else return NULL; } diff --git a/src/mainboard/google/kukui/display.h b/src/mainboard/google/kukui/display.h index 1b184af..bc26c69 100644 --- a/src/mainboard/google/kukui/display.h +++ b/src/mainboard/google/kukui/display.h @@ -41,10 +41,21 @@ PANEL_KRANE_UNINITIALIZED }; +enum flapjack_panel_id { + PANEL_FLAPJACK_FIRST = 0, + PANEL_FLAPJACK_BOE_TV101WUM_NG0, + PANEL_FLAPJACK_BOE_TV080WUM_NG0, + PANEL_FLAPJACK_INX_OTA7290D10P, + PANEL_FLAPJACK_AUO_NT51021D8P, + PANEL_FLAPJACK_UNKNOWN, + PANEL_FLAPJACK_COUNT, + PANEL_FLAPJACK_UNINITIALIZED +}; union panel_id { enum kukui_panel_id kukui_panel; enum krane_panel_id krane_panel; + enum flapjack_panel_id flapjack_panel; int value; }; @@ -100,5 +111,6 @@ */ extern struct board_display_intf kukui_display_intf; extern struct board_display_intf krane_display_intf; +extern struct board_display_intf flapjack_display_intf; #endif diff --git a/src/mainboard/google/kukui/panel_flapjack.c b/src/mainboard/google/kukui/panel_flapjack.c new file mode 100644 index 0000000..1b72e8a --- /dev/null +++ b/src/mainboard/google/kukui/panel_flapjack.c @@ -0,0 +1,1097 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Huaqin Telecom Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <edid.h> +#include <gpio.h> +#include <soc/auxadc.h> +#include <soc/ddp.h> +#include <soc/dsi.h> +#include <soc/gpio.h> +#include <boardid.h> + +#include "display.h" +#include "gpio.h" + +#define PP3300_LCM_EN GPIO(SIM2_SIO) +#define PP1800_LCM_EN GPIO(SIM2_SRST) + +#define FLAPJACK_PANEL_ADC_ID 2 +#define FLAPJACK_PANEL_ID_BIT_POSITION 16 + +const int tolerance = 30000; /* 30,000 uV */ + +static struct edid flapjack_boe_tv080wum_edid = { + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .name = "1200x1920@60Hz", + .pixel_clock = 159420, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 1200, .hbl = 164, .hso = 80, .hspw = 24, .hborder = 0, + .va = 1920, .vbl = 28, .vso = 10, .vspw = 4, .vborder = 0, + .phsync = '-', .pvsync = '-', + .x_mm = 107, .y_mm = 132, + }, +}; + +static struct lcm_init_table boe_tv080wum_lcm_init_cmd[] = { + {INIT_CMD, 1, {0x10} }, + {DELAY_CMD, 0x22, {} }, + {INIT_CMD, 2, {0xB0, 0x05} }, + {INIT_CMD, 2, {0xB1, 0xE5} }, + {INIT_CMD, 2, {0xB3, 0x52} }, + {INIT_CMD, 2, {0xB0, 0x00} }, + {INIT_CMD, 2, {0xB3, 0x88} }, + {INIT_CMD, 2, {0xB0, 0x04} }, + {INIT_CMD, 2, {0xB8, 0x00} }, + {INIT_CMD, 2, {0xB0, 0x00} }, + {INIT_CMD, 2, {0xB2, 0x50} }, + {INIT_CMD, 2, {0xB6, 0x03} }, + {INIT_CMD, 2, {0xBA, 0x8B} }, + {INIT_CMD, 2, {0xBF, 0x15} }, + {INIT_CMD, 2, {0xC0, 0x0F} }, + {INIT_CMD, 2, {0xC2, 0x0C} }, + {INIT_CMD, 2, {0xC3, 0x02} }, + {INIT_CMD, 2, {0xC4, 0x0C} }, + {INIT_CMD, 2, {0xC5, 0x02} }, + {INIT_CMD, 2, {0xB0, 0x01} }, + {INIT_CMD, 2, {0xE0, 0x26} }, + {INIT_CMD, 2, {0xE1, 0x26} }, + {INIT_CMD, 2, {0xDC, 0x00} }, + {INIT_CMD, 2, {0xDD, 0x00} }, + {INIT_CMD, 2, {0xCC, 0x26} }, + {INIT_CMD, 2, {0xCD, 0x26} }, + {INIT_CMD, 2, {0xC8, 0x00} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xD2, 0x04} }, + {INIT_CMD, 2, {0xD3, 0x04} }, + {INIT_CMD, 2, {0xE6, 0x03} }, + {INIT_CMD, 2, {0xE7, 0x03} }, + {INIT_CMD, 2, {0xC4, 0x08} }, + {INIT_CMD, 2, {0xC5, 0x08} }, + {INIT_CMD, 2, {0xD8, 0x07} }, + {INIT_CMD, 2, {0xD9, 0x07} }, + {INIT_CMD, 2, {0xC2, 0x06} }, + {INIT_CMD, 2, {0xC3, 0x06} }, + {INIT_CMD, 2, {0xD6, 0x05} }, + {INIT_CMD, 2, {0xD7, 0x05} }, + {INIT_CMD, 2, {0xC0, 0x0C} }, + {INIT_CMD, 2, {0xC1, 0x0C} }, + {INIT_CMD, 2, {0xD4, 0x0B} }, + {INIT_CMD, 2, {0xD5, 0x0B} }, + {INIT_CMD, 2, {0xCA, 0x0A} }, + {INIT_CMD, 2, {0xCB, 0x0A} }, + {INIT_CMD, 2, {0xDE, 0x09} }, + {INIT_CMD, 2, {0xDF, 0x09} }, + {INIT_CMD, 2, {0xC6, 0x26} }, + {INIT_CMD, 2, {0xC7, 0x26} }, + {INIT_CMD, 2, {0xCE, 0x00} }, + {INIT_CMD, 2, {0xCF, 0x00} }, + {INIT_CMD, 2, {0xDA, 0x26} }, + {INIT_CMD, 2, {0xDB, 0x26} }, + {INIT_CMD, 2, {0xE2, 0x00} }, + {INIT_CMD, 2, {0xE3, 0x00} }, + {INIT_CMD, 2, {0xB0, 0x02} }, + {INIT_CMD, 2, {0xC0, 0x00} }, + {INIT_CMD, 2, {0xC1, 0x07} }, + {INIT_CMD, 2, {0xC2, 0x0D} }, + {INIT_CMD, 2, {0xC3, 0x18} }, + {INIT_CMD, 2, {0xC4, 0x27} }, + {INIT_CMD, 2, {0xC5, 0x28} }, + {INIT_CMD, 2, {0xC6, 0x30} }, + {INIT_CMD, 2, {0xC7, 0x2E} }, + {INIT_CMD, 2, {0xC8, 0x2F} }, + {INIT_CMD, 2, {0xC9, 0x1A} }, + {INIT_CMD, 2, {0xCA, 0x20} }, + {INIT_CMD, 2, {0xCB, 0x29} }, + {INIT_CMD, 2, {0xCC, 0x26} }, + {INIT_CMD, 2, {0xCD, 0x32} }, + {INIT_CMD, 2, {0xCE, 0x33} }, + {INIT_CMD, 2, {0xCF, 0x31} }, + {INIT_CMD, 2, {0xD0, 0x06} }, + {INIT_CMD, 2, {0xD2, 0x00} }, + {INIT_CMD, 2, {0xD3, 0x07} }, + {INIT_CMD, 2, {0xD4, 0x12} }, + {INIT_CMD, 2, {0xD5, 0x26} }, + {INIT_CMD, 2, {0xD6, 0x3D} }, + {INIT_CMD, 2, {0xD7, 0x3F} }, + {INIT_CMD, 2, {0xD8, 0x3F} }, + {INIT_CMD, 2, {0xD9, 0x3F} }, + {INIT_CMD, 2, {0xDA, 0x3F} }, + {INIT_CMD, 2, {0xDB, 0x3F} }, + {INIT_CMD, 2, {0xDC, 0x3F} }, + {INIT_CMD, 2, {0xDD, 0x3F} }, + {INIT_CMD, 2, {0xDE, 0x3F} }, + {INIT_CMD, 2, {0xDF, 0x3A} }, + {INIT_CMD, 2, {0xE0, 0x37} }, + {INIT_CMD, 2, {0xE1, 0x35} }, + {INIT_CMD, 2, {0xE2, 0x07} }, + {INIT_CMD, 2, {0xB0, 0x03} }, + {INIT_CMD, 2, {0xC8, 0x0B} }, + {INIT_CMD, 2, {0xC9, 0x07} }, + {INIT_CMD, 2, {0xC3, 0x00} }, + {INIT_CMD, 2, {0xE7, 0x00} }, + {INIT_CMD, 2, {0xC5, 0x2A} }, + {INIT_CMD, 2, {0xDE, 0x2A} }, + {INIT_CMD, 2, {0xCA, 0x43} }, + {INIT_CMD, 2, {0xC9, 0x07} }, + {INIT_CMD, 2, {0xE4, 0xC0} }, + {INIT_CMD, 2, {0xE5, 0x0D} }, + {INIT_CMD, 2, {0xCB, 0x00} }, + {INIT_CMD, 2, {0xB0, 0x06} }, + {INIT_CMD, 2, {0xB8, 0xA5} }, + {INIT_CMD, 2, {0xC0, 0xA5} }, + {INIT_CMD, 2, {0xC7, 0x0F} }, + {INIT_CMD, 2, {0xD5, 0x32} }, + {INIT_CMD, 2, {0xB8, 0x00} }, + {INIT_CMD, 2, {0xC0, 0x00} }, + {INIT_CMD, 2, {0xBC, 0x00} }, + {INIT_CMD, 2, {0xB0, 0x07} }, + {INIT_CMD, 2, {0xB1, 0x00} }, + {INIT_CMD, 2, {0xB2, 0x09} }, + {INIT_CMD, 2, {0xB3, 0x19} }, + {INIT_CMD, 2, {0xB4, 0x2F} }, + {INIT_CMD, 2, {0xB5, 0x44} }, + {INIT_CMD, 2, {0xB6, 0x52} }, + {INIT_CMD, 2, {0xB7, 0x6A} }, + {INIT_CMD, 2, {0xB8, 0x8A} }, + {INIT_CMD, 2, {0xB9, 0xCA} }, + {INIT_CMD, 2, {0xBA, 0x0C} }, + {INIT_CMD, 2, {0xBB, 0x87} }, + {DELAY_CMD, 0x05, {} }, + {INIT_CMD, 2, {0xBC, 0x06} }, + {INIT_CMD, 2, {0xBD, 0x0A} }, + {INIT_CMD, 2, {0xBE, 0x9B} }, + {INIT_CMD, 2, {0xBF, 0x0C} }, + {INIT_CMD, 2, {0xC0, 0x3D} }, + {INIT_CMD, 2, {0xC1, 0x71} }, + {INIT_CMD, 2, {0xC2, 0x90} }, + {INIT_CMD, 2, {0xC3, 0xA0} }, + {INIT_CMD, 2, {0xC4, 0xA8} }, + {INIT_CMD, 2, {0xC5, 0xB1} }, + {INIT_CMD, 2, {0xC6, 0xBB} }, + {INIT_CMD, 2, {0xC7, 0xC0} }, + {INIT_CMD, 2, {0xC8, 0xC4} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xCA, 0x00} }, + {INIT_CMD, 2, {0xCB, 0x16} }, + {INIT_CMD, 2, {0xCC, 0xAF} }, + {INIT_CMD, 2, {0xCD, 0xFF} }, + {INIT_CMD, 2, {0xCE, 0xFF} }, + {INIT_CMD, 2, {0xB0, 0x08} }, + {INIT_CMD, 2, {0xB1, 0x04} }, + {INIT_CMD, 2, {0xB2, 0x08} }, + {INIT_CMD, 2, {0xB3, 0x19} }, + {INIT_CMD, 2, {0xB4, 0x31} }, + {INIT_CMD, 2, {0xB5, 0x46} }, + {INIT_CMD, 2, {0xB6, 0x55} }, + {INIT_CMD, 2, {0xB7, 0x6E} }, + {INIT_CMD, 2, {0xB8, 0x92} }, + {INIT_CMD, 2, {0xB9, 0xD4} }, + {INIT_CMD, 2, {0xBA, 0x1B} }, + {INIT_CMD, 2, {0xBB, 0x9B} }, + {DELAY_CMD, 0x05, {} }, + {INIT_CMD, 2, {0xBC, 0x28} }, + {INIT_CMD, 2, {0xBD, 0x2D} }, + {INIT_CMD, 2, {0xBE, 0xC3} }, + {INIT_CMD, 2, {0xBF, 0x2F} }, + {INIT_CMD, 2, {0xC0, 0x62} }, + {INIT_CMD, 2, {0xC1, 0x99} }, + {INIT_CMD, 2, {0xC2, 0xAB} }, + {INIT_CMD, 2, {0xC3, 0xBF} }, + {INIT_CMD, 2, {0xC4, 0xCF} }, + {INIT_CMD, 2, {0xC5, 0xDF} }, + {INIT_CMD, 2, {0xC6, 0xF0} }, + {INIT_CMD, 2, {0xC7, 0xF9} }, + {INIT_CMD, 2, {0xC8, 0xFC} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xCA, 0x00} }, + {INIT_CMD, 2, {0xCB, 0x16} }, + {INIT_CMD, 2, {0xCC, 0xAF} }, + {INIT_CMD, 2, {0xCD, 0xFF} }, + {INIT_CMD, 2, {0xCE, 0xFF} }, + {INIT_CMD, 2, {0xB0, 0x09} }, + {INIT_CMD, 2, {0xB1, 0x04} }, + {INIT_CMD, 2, {0xB2, 0x05} }, + {INIT_CMD, 2, {0xB3, 0x17} }, + {INIT_CMD, 2, {0xB4, 0x2E} }, + {INIT_CMD, 2, {0xB5, 0x42} }, + {INIT_CMD, 2, {0xB6, 0x51} }, + {INIT_CMD, 2, {0xB7, 0x69} }, + {INIT_CMD, 2, {0xB8, 0x88} }, + {INIT_CMD, 2, {0xB9, 0xC9} }, + {INIT_CMD, 2, {0xBA, 0x0C} }, + {INIT_CMD, 2, {0xBB, 0x86} }, + {DELAY_CMD, 0x05, {} }, + {INIT_CMD, 2, {0xBC, 0x03} }, + {INIT_CMD, 2, {0xBD, 0x08} }, + {INIT_CMD, 2, {0xBE, 0x95} }, + {INIT_CMD, 2, {0xBF, 0x05} }, + {INIT_CMD, 2, {0xC0, 0x35} }, + {INIT_CMD, 2, {0xC1, 0x62} }, + {INIT_CMD, 2, {0xC2, 0x81} }, + {INIT_CMD, 2, {0xC3, 0x96} }, + {INIT_CMD, 2, {0xC4, 0x9E} }, + {INIT_CMD, 2, {0xC5, 0xA5} }, + {INIT_CMD, 2, {0xC6, 0xAD} }, + {INIT_CMD, 2, {0xC7, 0xB1} }, + {INIT_CMD, 2, {0xC8, 0xB4} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xCA, 0x00} }, + {INIT_CMD, 2, {0xCB, 0x16} }, + {INIT_CMD, 2, {0xCC, 0xAF} }, + {INIT_CMD, 2, {0xCD, 0xFF} }, + {INIT_CMD, 2, {0xCE, 0xFF} }, + {INIT_CMD, 2, {0xB0, 0x0A} }, + {INIT_CMD, 2, {0xB1, 0x00} }, + {INIT_CMD, 2, {0xB2, 0x09} }, + {INIT_CMD, 2, {0xB3, 0x19} }, + {INIT_CMD, 2, {0xB4, 0x2F} }, + {INIT_CMD, 2, {0xB5, 0x44} }, + {INIT_CMD, 2, {0xB6, 0x52} }, + {INIT_CMD, 2, {0xB7, 0x6A} }, + {INIT_CMD, 2, {0xB8, 0x8A} }, + {INIT_CMD, 2, {0xB9, 0xCA} }, + {INIT_CMD, 2, {0xBA, 0x0C} }, + {INIT_CMD, 2, {0xBB, 0x87} }, + {DELAY_CMD, 0x05, {} }, + {INIT_CMD, 2, {0xBC, 0x06} }, + {INIT_CMD, 2, {0xBD, 0x0A} }, + {INIT_CMD, 2, {0xBE, 0x9B} }, + {INIT_CMD, 2, {0xBF, 0x0C} }, + {INIT_CMD, 2, {0xC0, 0x3D} }, + {INIT_CMD, 2, {0xC1, 0x71} }, + {INIT_CMD, 2, {0xC2, 0x90} }, + {INIT_CMD, 2, {0xC3, 0xA0} }, + {INIT_CMD, 2, {0xC4, 0xA8} }, + {INIT_CMD, 2, {0xC5, 0xB1} }, + {INIT_CMD, 2, {0xC6, 0xBB} }, + {INIT_CMD, 2, {0xC7, 0xC0} }, + {INIT_CMD, 2, {0xC8, 0xC4} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xCA, 0x00} }, + {INIT_CMD, 2, {0xCB, 0x16} }, + {INIT_CMD, 2, {0xCC, 0xAF} }, + {INIT_CMD, 2, {0xCD, 0xFF} }, + {INIT_CMD, 2, {0xCE, 0xFF} }, + {INIT_CMD, 2, {0xB0, 0x0B} }, + {INIT_CMD, 2, {0xB1, 0x04} }, + {INIT_CMD, 2, {0xB2, 0x08} }, + {INIT_CMD, 2, {0xB3, 0x19} }, + {INIT_CMD, 2, {0xB4, 0x31} }, + {INIT_CMD, 2, {0xB5, 0x46} }, + {INIT_CMD, 2, {0xB6, 0x55} }, + {INIT_CMD, 2, {0xB7, 0x6E} }, + {INIT_CMD, 2, {0xB8, 0x92} }, + {INIT_CMD, 2, {0xB9, 0xD4} }, + {INIT_CMD, 2, {0xBA, 0x1B} }, + {INIT_CMD, 2, {0xBB, 0x9B} }, + {DELAY_CMD, 0x05, {} }, + {INIT_CMD, 2, {0xBC, 0x28} }, + {INIT_CMD, 2, {0xBD, 0x2D} }, + {INIT_CMD, 2, {0xBE, 0xC3} }, + {INIT_CMD, 2, {0xBF, 0x2F} }, + {INIT_CMD, 2, {0xC0, 0x62} }, + {INIT_CMD, 2, {0xC1, 0x99} }, + {INIT_CMD, 2, {0xC2, 0xAB} }, + {INIT_CMD, 2, {0xC3, 0xBF} }, + {INIT_CMD, 2, {0xC4, 0xCF} }, + {INIT_CMD, 2, {0xC5, 0xDF} }, + {INIT_CMD, 2, {0xC6, 0xF0} }, + {INIT_CMD, 2, {0xC7, 0xF9} }, + {INIT_CMD, 2, {0xC8, 0xFC} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xCA, 0x00} }, + {INIT_CMD, 2, {0xCB, 0x16} }, + {INIT_CMD, 2, {0xCC, 0xAF} }, + {INIT_CMD, 2, {0xCD, 0xFF} }, + {INIT_CMD, 2, {0xCE, 0xFF} }, + {INIT_CMD, 2, {0xB0, 0x0C} }, + {INIT_CMD, 2, {0xB1, 0x04} }, + {INIT_CMD, 2, {0xB2, 0x05} }, + {INIT_CMD, 2, {0xB3, 0x17} }, + {INIT_CMD, 2, {0xB4, 0x2E} }, + {INIT_CMD, 2, {0xB5, 0x42} }, + {INIT_CMD, 2, {0xB6, 0x51} }, + {INIT_CMD, 2, {0xB7, 0x69} }, + {INIT_CMD, 2, {0xB8, 0x88} }, + {INIT_CMD, 2, {0xB9, 0xC9} }, + {INIT_CMD, 2, {0xBA, 0x0C} }, + {INIT_CMD, 2, {0xBB, 0x86} }, + {DELAY_CMD, 0x05, {} }, + {INIT_CMD, 2, {0xBC, 0x03} }, + {INIT_CMD, 2, {0xBD, 0x08} }, + {INIT_CMD, 2, {0xBE, 0x95} }, + {INIT_CMD, 2, {0xBF, 0x05} }, + {INIT_CMD, 2, {0xC0, 0x35} }, + {INIT_CMD, 2, {0xC1, 0x62} }, + {INIT_CMD, 2, {0xC2, 0x81} }, + {INIT_CMD, 2, {0xC3, 0x96} }, + {INIT_CMD, 2, {0xC4, 0x9E} }, + {INIT_CMD, 2, {0xC5, 0xA5} }, + {INIT_CMD, 2, {0xC6, 0xAD} }, + {INIT_CMD, 2, {0xC7, 0xB1} }, + {INIT_CMD, 2, {0xC8, 0xB4} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xCA, 0x00} }, + {INIT_CMD, 2, {0xCB, 0x16} }, + {INIT_CMD, 2, {0xCC, 0xAF} }, + {INIT_CMD, 2, {0xCD, 0xFF} }, + {INIT_CMD, 2, {0xCE, 0xFF} }, + {DELAY_CMD, 0x64, {} }, + {INIT_CMD, 2, {0xB0, 0x00} }, + {INIT_CMD, 2, {0xB3, 0x08} }, + {INIT_CMD, 2, {0xB0, 0x04} }, + {INIT_CMD, 2, {0xB8, 0x68} }, + {DELAY_CMD, 0x0A, {} }, + {INIT_CMD, 1, {0x11} }, + {DELAY_CMD, 0x78, {} }, + {INIT_CMD, 1, {0x29} }, + {DELAY_CMD, 0x14, {} }, + +}; + +/* flapjack C19 BOE tv101wum panel : PANEL_FLAPJACK_BOE_TV101WUM_NG0 */ +static struct edid flapjack_boe_tv101wum_edid = { + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .name = "1200x1920@60Hz", + .pixel_clock = 159420, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 1200, .hbl = 164, .hso = 80, .hspw = 24, .hborder = 0, + .va = 1920, .vbl = 28, .vso = 10, .vspw = 4, .vborder = 0, + .phsync = '-', .pvsync = '-', + .x_mm = 135, .y_mm = 216, + }, +}; + +static struct lcm_init_table boe_tv101wum_lcm_init_cmd[] = { + {INIT_CMD, 1, {0x10} }, + {DELAY_CMD, 0x22, {} }, + {INIT_CMD, 2, {0xB0, 0x05} }, + {INIT_CMD, 2, {0xB1, 0xE5} }, + {INIT_CMD, 2, {0xB3, 0x52} }, + {INIT_CMD, 2, {0xB0, 0x00} }, + {INIT_CMD, 2, {0xB3, 0x88} }, + {INIT_CMD, 2, {0xB0, 0x04} }, + {INIT_CMD, 2, {0xB8, 0x00} }, + {INIT_CMD, 2, {0xB0, 0x00} }, + {INIT_CMD, 2, {0xB2, 0x50} }, + {INIT_CMD, 2, {0xB6, 0x03} }, + {INIT_CMD, 2, {0xBA, 0x8B} }, + {INIT_CMD, 2, {0xBF, 0x15} }, + {INIT_CMD, 2, {0xC0, 0x0F} }, + {INIT_CMD, 2, {0xC2, 0x0C} }, + {INIT_CMD, 2, {0xC3, 0x02} }, + {INIT_CMD, 2, {0xC4, 0x0C} }, + {INIT_CMD, 2, {0xC5, 0x02} }, + {INIT_CMD, 2, {0xB0, 0x01} }, + {INIT_CMD, 2, {0xE0, 0x26} }, + {INIT_CMD, 2, {0xE1, 0x26} }, + {INIT_CMD, 2, {0xDC, 0x00} }, + {INIT_CMD, 2, {0xDD, 0x00} }, + {INIT_CMD, 2, {0xCC, 0x26} }, + {INIT_CMD, 2, {0xCD, 0x26} }, + {INIT_CMD, 2, {0xC8, 0x00} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xD2, 0x04} }, + {INIT_CMD, 2, {0xD3, 0x04} }, + {INIT_CMD, 2, {0xE6, 0x03} }, + {INIT_CMD, 2, {0xE7, 0x03} }, + {INIT_CMD, 2, {0xC4, 0x08} }, + {INIT_CMD, 2, {0xC5, 0x08} }, + {INIT_CMD, 2, {0xD8, 0x07} }, + {INIT_CMD, 2, {0xD9, 0x07} }, + {INIT_CMD, 2, {0xC2, 0x06} }, + {INIT_CMD, 2, {0xC3, 0x06} }, + {INIT_CMD, 2, {0xD6, 0x05} }, + {INIT_CMD, 2, {0xD7, 0x05} }, + {INIT_CMD, 2, {0xC0, 0x0C} }, + {INIT_CMD, 2, {0xC1, 0x0C} }, + {INIT_CMD, 2, {0xD4, 0x0B} }, + {INIT_CMD, 2, {0xD5, 0x0B} }, + {INIT_CMD, 2, {0xCA, 0x0A} }, + {INIT_CMD, 2, {0xCB, 0x0A} }, + {INIT_CMD, 2, {0xDE, 0x09} }, + {INIT_CMD, 2, {0xDF, 0x09} }, + {INIT_CMD, 2, {0xC6, 0x26} }, + {INIT_CMD, 2, {0xC7, 0x26} }, + {INIT_CMD, 2, {0xCE, 0x00} }, + {INIT_CMD, 2, {0xCF, 0x00} }, + {INIT_CMD, 2, {0xDA, 0x26} }, + {INIT_CMD, 2, {0xDB, 0x26} }, + {INIT_CMD, 2, {0xE2, 0x00} }, + {INIT_CMD, 2, {0xE3, 0x00} }, + {INIT_CMD, 2, {0xB0, 0x02} }, + {INIT_CMD, 2, {0xC0, 0x00} }, + {INIT_CMD, 2, {0xC1, 0x07} }, + {INIT_CMD, 2, {0xC2, 0x0D} }, + {INIT_CMD, 2, {0xC3, 0x18} }, + {INIT_CMD, 2, {0xC4, 0x27} }, + {INIT_CMD, 2, {0xC5, 0x28} }, + {INIT_CMD, 2, {0xC6, 0x30} }, + {INIT_CMD, 2, {0xC7, 0x2E} }, + {INIT_CMD, 2, {0xC8, 0x2F} }, + {INIT_CMD, 2, {0xC9, 0x1A} }, + {INIT_CMD, 2, {0xCA, 0x20} }, + {INIT_CMD, 2, {0xCB, 0x29} }, + {INIT_CMD, 2, {0xCC, 0x26} }, + {INIT_CMD, 2, {0xCD, 0x32} }, + {INIT_CMD, 2, {0xCE, 0x33} }, + {INIT_CMD, 2, {0xCF, 0x31} }, + {INIT_CMD, 2, {0xD0, 0x06} }, + {INIT_CMD, 2, {0xD2, 0x00} }, + {INIT_CMD, 2, {0xD3, 0x07} }, + {INIT_CMD, 2, {0xD4, 0x12} }, + {INIT_CMD, 2, {0xD5, 0x26} }, + {INIT_CMD, 2, {0xD6, 0x3D} }, + {INIT_CMD, 2, {0xD7, 0x3F} }, + {INIT_CMD, 2, {0xD8, 0x3F} }, + {INIT_CMD, 2, {0xD9, 0x3F} }, + {INIT_CMD, 2, {0xDA, 0x3F} }, + {INIT_CMD, 2, {0xDB, 0x3F} }, + {INIT_CMD, 2, {0xDC, 0x3F} }, + {INIT_CMD, 2, {0xDD, 0x3F} }, + {INIT_CMD, 2, {0xDE, 0x3F} }, + {INIT_CMD, 2, {0xDF, 0x3A} }, + {INIT_CMD, 2, {0xE0, 0x37} }, + {INIT_CMD, 2, {0xE1, 0x35} }, + {INIT_CMD, 2, {0xE2, 0x07} }, + {INIT_CMD, 2, {0xB0, 0x03} }, + {INIT_CMD, 2, {0xC8, 0x0B} }, + {INIT_CMD, 2, {0xC9, 0x07} }, + {INIT_CMD, 2, {0xC3, 0x00} }, + {INIT_CMD, 2, {0xE7, 0x00} }, + {INIT_CMD, 2, {0xC5, 0x2A} }, + {INIT_CMD, 2, {0xDE, 0x2A} }, + {INIT_CMD, 2, {0xCA, 0x43} }, + {INIT_CMD, 2, {0xC9, 0x07} }, + {INIT_CMD, 2, {0xE4, 0xC0} }, + {INIT_CMD, 2, {0xE5, 0x0D} }, + {INIT_CMD, 2, {0xCB, 0x00} }, + {INIT_CMD, 2, {0xB0, 0x06} }, + {INIT_CMD, 2, {0xB8, 0xA5} }, + {INIT_CMD, 2, {0xC0, 0xA5} }, + {INIT_CMD, 2, {0xC7, 0x0F} }, + {INIT_CMD, 2, {0xD5, 0x32} }, + {INIT_CMD, 2, {0xB8, 0x00} }, + {INIT_CMD, 2, {0xC0, 0x00} }, + {INIT_CMD, 2, {0xBC, 0x00} }, + {INIT_CMD, 2, {0xB0, 0x07} }, + {INIT_CMD, 2, {0xB1, 0x00} }, + {INIT_CMD, 2, {0xB2, 0x09} }, + {INIT_CMD, 2, {0xB3, 0x19} }, + {INIT_CMD, 2, {0xB4, 0x2F} }, + {INIT_CMD, 2, {0xB5, 0x44} }, + {INIT_CMD, 2, {0xB6, 0x52} }, + {INIT_CMD, 2, {0xB7, 0x6A} }, + {INIT_CMD, 2, {0xB8, 0x8A} }, + {INIT_CMD, 2, {0xB9, 0xCA} }, + {INIT_CMD, 2, {0xBA, 0x0C} }, + {INIT_CMD, 2, {0xBB, 0x87} }, + {DELAY_CMD, 0x05, {} }, + {INIT_CMD, 2, {0xBC, 0x06} }, + {INIT_CMD, 2, {0xBD, 0x0A} }, + {INIT_CMD, 2, {0xBE, 0x9B} }, + {INIT_CMD, 2, {0xBF, 0x0C} }, + {INIT_CMD, 2, {0xC0, 0x3D} }, + {INIT_CMD, 2, {0xC1, 0x71} }, + {INIT_CMD, 2, {0xC2, 0x90} }, + {INIT_CMD, 2, {0xC3, 0xA0} }, + {INIT_CMD, 2, {0xC4, 0xA8} }, + {INIT_CMD, 2, {0xC5, 0xB1} }, + {INIT_CMD, 2, {0xC6, 0xBB} }, + {INIT_CMD, 2, {0xC7, 0xC0} }, + {INIT_CMD, 2, {0xC8, 0xC4} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xCA, 0x00} }, + {INIT_CMD, 2, {0xCB, 0x16} }, + {INIT_CMD, 2, {0xCC, 0xAF} }, + {INIT_CMD, 2, {0xCD, 0xFF} }, + {INIT_CMD, 2, {0xCE, 0xFF} }, + {INIT_CMD, 2, {0xB0, 0x08} }, + {INIT_CMD, 2, {0xB1, 0x04} }, + {INIT_CMD, 2, {0xB2, 0x08} }, + {INIT_CMD, 2, {0xB3, 0x19} }, + {INIT_CMD, 2, {0xB4, 0x31} }, + {INIT_CMD, 2, {0xB5, 0x46} }, + {INIT_CMD, 2, {0xB6, 0x55} }, + {INIT_CMD, 2, {0xB7, 0x6E} }, + {INIT_CMD, 2, {0xB8, 0x92} }, + {INIT_CMD, 2, {0xB9, 0xD4} }, + {INIT_CMD, 2, {0xBA, 0x1B} }, + {INIT_CMD, 2, {0xBB, 0x9B} }, + {DELAY_CMD, 0x05, {} }, + {INIT_CMD, 2, {0xBC, 0x28} }, + {INIT_CMD, 2, {0xBD, 0x2D} }, + {INIT_CMD, 2, {0xBE, 0xC3} }, + {INIT_CMD, 2, {0xBF, 0x2F} }, + {INIT_CMD, 2, {0xC0, 0x62} }, + {INIT_CMD, 2, {0xC1, 0x99} }, + {INIT_CMD, 2, {0xC2, 0xAB} }, + {INIT_CMD, 2, {0xC3, 0xBF} }, + {INIT_CMD, 2, {0xC4, 0xCF} }, + {INIT_CMD, 2, {0xC5, 0xDF} }, + {INIT_CMD, 2, {0xC6, 0xF0} }, + {INIT_CMD, 2, {0xC7, 0xF9} }, + {INIT_CMD, 2, {0xC8, 0xFC} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xCA, 0x00} }, + {INIT_CMD, 2, {0xCB, 0x16} }, + {INIT_CMD, 2, {0xCC, 0xAF} }, + {INIT_CMD, 2, {0xCD, 0xFF} }, + {INIT_CMD, 2, {0xCE, 0xFF} }, + {INIT_CMD, 2, {0xB0, 0x09} }, + {INIT_CMD, 2, {0xB1, 0x04} }, + {INIT_CMD, 2, {0xB2, 0x05} }, + {INIT_CMD, 2, {0xB3, 0x17} }, + {INIT_CMD, 2, {0xB4, 0x2E} }, + {INIT_CMD, 2, {0xB5, 0x42} }, + {INIT_CMD, 2, {0xB6, 0x51} }, + {INIT_CMD, 2, {0xB7, 0x69} }, + {INIT_CMD, 2, {0xB8, 0x88} }, + {INIT_CMD, 2, {0xB9, 0xC9} }, + {INIT_CMD, 2, {0xBA, 0x0C} }, + {INIT_CMD, 2, {0xBB, 0x86} }, + {DELAY_CMD, 0x05, {} }, + {INIT_CMD, 2, {0xBC, 0x03} }, + {INIT_CMD, 2, {0xBD, 0x08} }, + {INIT_CMD, 2, {0xBE, 0x95} }, + {INIT_CMD, 2, {0xBF, 0x05} }, + {INIT_CMD, 2, {0xC0, 0x35} }, + {INIT_CMD, 2, {0xC1, 0x62} }, + {INIT_CMD, 2, {0xC2, 0x81} }, + {INIT_CMD, 2, {0xC3, 0x96} }, + {INIT_CMD, 2, {0xC4, 0x9E} }, + {INIT_CMD, 2, {0xC5, 0xA5} }, + {INIT_CMD, 2, {0xC6, 0xAD} }, + {INIT_CMD, 2, {0xC7, 0xB1} }, + {INIT_CMD, 2, {0xC8, 0xB4} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xCA, 0x00} }, + {INIT_CMD, 2, {0xCB, 0x16} }, + {INIT_CMD, 2, {0xCC, 0xAF} }, + {INIT_CMD, 2, {0xCD, 0xFF} }, + {INIT_CMD, 2, {0xCE, 0xFF} }, + {INIT_CMD, 2, {0xB0, 0x0A} }, + {INIT_CMD, 2, {0xB1, 0x00} }, + {INIT_CMD, 2, {0xB2, 0x09} }, + {INIT_CMD, 2, {0xB3, 0x19} }, + {INIT_CMD, 2, {0xB4, 0x2F} }, + {INIT_CMD, 2, {0xB5, 0x44} }, + {INIT_CMD, 2, {0xB6, 0x52} }, + {INIT_CMD, 2, {0xB7, 0x6A} }, + {INIT_CMD, 2, {0xB8, 0x8A} }, + {INIT_CMD, 2, {0xB9, 0xCA} }, + {INIT_CMD, 2, {0xBA, 0x0C} }, + {INIT_CMD, 2, {0xBB, 0x87} }, + {DELAY_CMD, 0x05, {} }, + {INIT_CMD, 2, {0xBC, 0x06} }, + {INIT_CMD, 2, {0xBD, 0x0A} }, + {INIT_CMD, 2, {0xBE, 0x9B} }, + {INIT_CMD, 2, {0xBF, 0x0C} }, + {INIT_CMD, 2, {0xC0, 0x3D} }, + {INIT_CMD, 2, {0xC1, 0x71} }, + {INIT_CMD, 2, {0xC2, 0x90} }, + {INIT_CMD, 2, {0xC3, 0xA0} }, + {INIT_CMD, 2, {0xC4, 0xA8} }, + {INIT_CMD, 2, {0xC5, 0xB1} }, + {INIT_CMD, 2, {0xC6, 0xBB} }, + {INIT_CMD, 2, {0xC7, 0xC0} }, + {INIT_CMD, 2, {0xC8, 0xC4} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xCA, 0x00} }, + {INIT_CMD, 2, {0xCB, 0x16} }, + {INIT_CMD, 2, {0xCC, 0xAF} }, + {INIT_CMD, 2, {0xCD, 0xFF} }, + {INIT_CMD, 2, {0xCE, 0xFF} }, + {INIT_CMD, 2, {0xB0, 0x0B} }, + {INIT_CMD, 2, {0xB1, 0x04} }, + {INIT_CMD, 2, {0xB2, 0x08} }, + {INIT_CMD, 2, {0xB3, 0x19} }, + {INIT_CMD, 2, {0xB4, 0x31} }, + {INIT_CMD, 2, {0xB5, 0x46} }, + {INIT_CMD, 2, {0xB6, 0x55} }, + {INIT_CMD, 2, {0xB7, 0x6E} }, + {INIT_CMD, 2, {0xB8, 0x92} }, + {INIT_CMD, 2, {0xB9, 0xD4} }, + {INIT_CMD, 2, {0xBA, 0x1B} }, + {INIT_CMD, 2, {0xBB, 0x9B} }, + {DELAY_CMD, 0x05, {} }, + {INIT_CMD, 2, {0xBC, 0x28} }, + {INIT_CMD, 2, {0xBD, 0x2D} }, + {INIT_CMD, 2, {0xBE, 0xC3} }, + {INIT_CMD, 2, {0xBF, 0x2F} }, + {INIT_CMD, 2, {0xC0, 0x62} }, + {INIT_CMD, 2, {0xC1, 0x99} }, + {INIT_CMD, 2, {0xC2, 0xAB} }, + {INIT_CMD, 2, {0xC3, 0xBF} }, + {INIT_CMD, 2, {0xC4, 0xCF} }, + {INIT_CMD, 2, {0xC5, 0xDF} }, + {INIT_CMD, 2, {0xC6, 0xF0} }, + {INIT_CMD, 2, {0xC7, 0xF9} }, + {INIT_CMD, 2, {0xC8, 0xFC} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xCA, 0x00} }, + {INIT_CMD, 2, {0xCB, 0x16} }, + {INIT_CMD, 2, {0xCC, 0xAF} }, + {INIT_CMD, 2, {0xCD, 0xFF} }, + {INIT_CMD, 2, {0xCE, 0xFF} }, + {INIT_CMD, 2, {0xB0, 0x0C} }, + {INIT_CMD, 2, {0xB1, 0x04} }, + {INIT_CMD, 2, {0xB2, 0x05} }, + {INIT_CMD, 2, {0xB3, 0x17} }, + {INIT_CMD, 2, {0xB4, 0x2E} }, + {INIT_CMD, 2, {0xB5, 0x42} }, + {INIT_CMD, 2, {0xB6, 0x51} }, + {INIT_CMD, 2, {0xB7, 0x69} }, + {INIT_CMD, 2, {0xB8, 0x88} }, + {INIT_CMD, 2, {0xB9, 0xC9} }, + {INIT_CMD, 2, {0xBA, 0x0C} }, + {INIT_CMD, 2, {0xBB, 0x86} }, + {DELAY_CMD, 0x05, {} }, + {INIT_CMD, 2, {0xBC, 0x03} }, + {INIT_CMD, 2, {0xBD, 0x08} }, + {INIT_CMD, 2, {0xBE, 0x95} }, + {INIT_CMD, 2, {0xBF, 0x05} }, + {INIT_CMD, 2, {0xC0, 0x35} }, + {INIT_CMD, 2, {0xC1, 0x62} }, + {INIT_CMD, 2, {0xC2, 0x81} }, + {INIT_CMD, 2, {0xC3, 0x96} }, + {INIT_CMD, 2, {0xC4, 0x9E} }, + {INIT_CMD, 2, {0xC5, 0xA5} }, + {INIT_CMD, 2, {0xC6, 0xAD} }, + {INIT_CMD, 2, {0xC7, 0xB1} }, + {INIT_CMD, 2, {0xC8, 0xB4} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xCA, 0x00} }, + {INIT_CMD, 2, {0xCB, 0x16} }, + {INIT_CMD, 2, {0xCC, 0xAF} }, + {INIT_CMD, 2, {0xCD, 0xFF} }, + {INIT_CMD, 2, {0xCE, 0xFF} }, + {DELAY_CMD, 0x64, {} }, + {INIT_CMD, 2, {0xB0, 0x00} }, + {INIT_CMD, 2, {0xB3, 0x08} }, + {INIT_CMD, 2, {0xB0, 0x04} }, + {INIT_CMD, 2, {0xB8, 0x68} }, + {DELAY_CMD, 0x0A, {} }, + {INIT_CMD, 1, {0x11} }, + {DELAY_CMD, 0x78, {} }, + {INIT_CMD, 1, {0x29} }, + {DELAY_CMD, 0x14, {} }, +}; + +/* flapjack C18 AUO NT51021 panel : PANEL_AUO_NT51021D8P */ +static struct edid flapjack_auo_nt51021d8p_edid = { + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .name = "1200x1920@60Hz", + .pixel_clock = 159420, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 1200, .hbl = 141, .hso = 80, .hspw = 1, .hborder = 0, + .va = 1920, .vbl = 61, .vso = 35, .vspw = 1, .vborder = 0, + .phsync = '-', .pvsync = '-', + .x_mm = 107, .y_mm = 132, + }, +}; + +static struct lcm_init_table auo_nt51021d8p_lcm_init_cmd[] = { + {INIT_CMD, 1, {0x11} }, + {DELAY_CMD, 0x78, {} }, + {INIT_CMD, 1, {0x29} }, + {DELAY_CMD, 0x14, {} }, +}; + +/* flapjack C19 INX OTA7290 panel : PANEL_INX_OTA7290D10P */ +static struct edid flapjack_inx_ota7290d10p_edid = { + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .name = "1200x1920@60Hz", + .pixel_clock = 159420, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 1200, .hbl = 141, .hso = 80, .hspw = 1, .hborder = 0, + .va = 1920, .vbl = 61, .vso = 35, .vspw = 1, .vborder = 0, + .phsync = '-', .pvsync = '-', + .x_mm = 135, .y_mm = 216, + }, +}; + +static struct lcm_init_table inx_ota7290d10p_lcm_init_cmd[] = { + {INIT_CMD, 2, { 0xB0, 0x5A} }, + {INIT_CMD, 2, { 0xB1, 0x00} }, + {INIT_CMD, 2, { 0x89, 0x01} }, + {INIT_CMD, 2, { 0x91, 0x17} }, + {INIT_CMD, 2, { 0xB1, 0x03} }, + {INIT_CMD, 2, { 0x2C, 0x28} }, + {INIT_CMD, 2, { 0x00, 0xF1} }, + {INIT_CMD, 2, { 0x01, 0x78} }, + {INIT_CMD, 2, { 0x02, 0x3C} }, + {INIT_CMD, 2, { 0x03, 0x1E} }, + {INIT_CMD, 2, { 0x04, 0x8F} }, + {INIT_CMD, 2, { 0x05, 0x01} }, + {INIT_CMD, 2, { 0x06, 0x00} }, + {INIT_CMD, 2, { 0x07, 0x00} }, + {INIT_CMD, 2, { 0x08, 0x00} }, + {INIT_CMD, 2, { 0x09, 0x00} }, + {INIT_CMD, 2, { 0x0A, 0x01} }, + {INIT_CMD, 2, { 0x0B, 0x3C} }, + {INIT_CMD, 2, { 0x0C, 0x00} }, + {INIT_CMD, 2, { 0x0D, 0x00} }, + {INIT_CMD, 2, { 0x0E, 0x24} }, + {INIT_CMD, 2, { 0x0F, 0x1C} }, + {INIT_CMD, 2, { 0x10, 0xC8} }, + {INIT_CMD, 2, { 0x11, 0x60} }, + {INIT_CMD, 2, { 0x12, 0x70} }, + {INIT_CMD, 2, { 0x13, 0x01} }, + {INIT_CMD, 2, { 0x14, 0xE3} }, + {INIT_CMD, 2, { 0x15, 0xFF} }, + {INIT_CMD, 2, { 0x16, 0x3D} }, + {INIT_CMD, 2, { 0x17, 0x0E} }, + {INIT_CMD, 2, { 0x18, 0x01} }, + {INIT_CMD, 2, { 0x19, 0x00} }, + {INIT_CMD, 2, { 0x1A, 0x00} }, + {INIT_CMD, 2, { 0x1B, 0xFC} }, + {INIT_CMD, 2, { 0x1C, 0x0B} }, + {INIT_CMD, 2, { 0x1D, 0xA0} }, + {INIT_CMD, 2, { 0x1E, 0x03} }, + {INIT_CMD, 2, { 0x1F, 0x04} }, + {INIT_CMD, 2, { 0x20, 0x0C} }, + {INIT_CMD, 2, { 0x21, 0x00} }, + {INIT_CMD, 2, { 0x22, 0x04} }, + {INIT_CMD, 2, { 0x23, 0x81} }, + {INIT_CMD, 2, { 0x24, 0x1F} }, + {INIT_CMD, 2, { 0x25, 0x10} }, + {INIT_CMD, 2, { 0x26, 0x9B} }, + {INIT_CMD, 2, { 0x2D, 0x01} }, + {INIT_CMD, 2, { 0x2E, 0x84} }, + {INIT_CMD, 2, { 0x2F, 0x00} }, + {INIT_CMD, 2, { 0x30, 0x02} }, + {INIT_CMD, 2, { 0x31, 0x08} }, + {INIT_CMD, 2, { 0x32, 0x01} }, + {INIT_CMD, 2, { 0x33, 0x1C} }, + {INIT_CMD, 2, { 0x34, 0x70} }, + {INIT_CMD, 2, { 0x35, 0xFF} }, + {INIT_CMD, 2, { 0x36, 0xFF} }, + {INIT_CMD, 2, { 0x37, 0xFF} }, + {INIT_CMD, 2, { 0x38, 0xFF} }, + {INIT_CMD, 2, { 0x39, 0xFF} }, + {INIT_CMD, 2, { 0x3A, 0x05} }, + {INIT_CMD, 2, { 0x3B, 0x00} }, + {INIT_CMD, 2, { 0x3C, 0x00} }, + {INIT_CMD, 2, { 0x3D, 0x00} }, + {INIT_CMD, 2, { 0x3E, 0x0F} }, + {INIT_CMD, 2, { 0x3F, 0xA4} }, + {INIT_CMD, 2, { 0x40, 0x28} }, + {INIT_CMD, 2, { 0x41, 0xFC} }, + {INIT_CMD, 2, { 0x42, 0x01} }, + {INIT_CMD, 2, { 0x43, 0x08} }, + {INIT_CMD, 2, { 0x44, 0x05} }, + {INIT_CMD, 2, { 0x45, 0xF0} }, + {INIT_CMD, 2, { 0x46, 0x01} }, + {INIT_CMD, 2, { 0x47, 0x02} }, + {INIT_CMD, 2, { 0x48, 0x00} }, + {INIT_CMD, 2, { 0x49, 0x58} }, + {INIT_CMD, 2, { 0x4A, 0x00} }, + {INIT_CMD, 2, { 0x4B, 0x05} }, + {INIT_CMD, 2, { 0x4C, 0x03} }, + {INIT_CMD, 2, { 0x4D, 0xD0} }, + {INIT_CMD, 2, { 0x4E, 0x13} }, + {INIT_CMD, 2, { 0x4F, 0xFF} }, + {INIT_CMD, 2, { 0x50, 0x0A} }, + {INIT_CMD, 2, { 0x51, 0x53} }, + {INIT_CMD, 2, { 0x52, 0x26} }, + {INIT_CMD, 2, { 0x53, 0x22} }, + {INIT_CMD, 2, { 0x54, 0x09} }, + {INIT_CMD, 2, { 0x55, 0x22} }, + {INIT_CMD, 2, { 0x56, 0x00} }, + {INIT_CMD, 2, { 0x57, 0x1C} }, + {INIT_CMD, 2, { 0x58, 0x03} }, + {INIT_CMD, 2, { 0x59, 0x3F} }, + {INIT_CMD, 2, { 0x5A, 0x28} }, + {INIT_CMD, 2, { 0x5B, 0x01} }, + {INIT_CMD, 2, { 0x5C, 0xCC} }, + {INIT_CMD, 2, { 0x5D, 0x21} }, + {INIT_CMD, 2, { 0x5E, 0x04} }, + {INIT_CMD, 2, { 0x5F, 0x13} }, + {INIT_CMD, 2, { 0x60, 0x42} }, + {INIT_CMD, 2, { 0x61, 0x08} }, + {INIT_CMD, 2, { 0x62, 0x64} }, + {INIT_CMD, 2, { 0x63, 0xEB} }, + {INIT_CMD, 2, { 0x64, 0x10} }, + {INIT_CMD, 2, { 0x65, 0xA8} }, + {INIT_CMD, 2, { 0x66, 0x84} }, + {INIT_CMD, 2, { 0x67, 0x8E} }, + {INIT_CMD, 2, { 0x68, 0x29} }, + {INIT_CMD, 2, { 0x69, 0x11} }, + {INIT_CMD, 2, { 0x6A, 0x42} }, + {INIT_CMD, 2, { 0x6B, 0x38} }, + {INIT_CMD, 2, { 0x6C, 0x21} }, + {INIT_CMD, 2, { 0x6D, 0x84} }, + {INIT_CMD, 2, { 0x6E, 0x50} }, + {INIT_CMD, 2, { 0x6F, 0xB6} }, + {INIT_CMD, 2, { 0x70, 0x0E} }, + {INIT_CMD, 2, { 0x71, 0xA1} }, + {INIT_CMD, 2, { 0x72, 0xCE} }, + {INIT_CMD, 2, { 0x73, 0xF8} }, + {INIT_CMD, 2, { 0x74, 0xDA} }, + {INIT_CMD, 2, { 0x75, 0x1A} }, + {INIT_CMD, 2, { 0x76, 0x00} }, + {INIT_CMD, 2, { 0x77, 0x00} }, + {INIT_CMD, 2, { 0x78, 0x5F} }, + {INIT_CMD, 2, { 0x79, 0xE0} }, + {INIT_CMD, 2, { 0x7A, 0x01} }, + {INIT_CMD, 2, { 0x7B, 0xFF} }, + {INIT_CMD, 2, { 0x7C, 0xFF} }, + {INIT_CMD, 2, { 0x7D, 0xFF} }, + {INIT_CMD, 2, { 0x7E, 0xFF} }, + {INIT_CMD, 2, { 0x7F, 0xFE} }, + {INIT_CMD, 2, { 0xB1, 0x02} }, + {INIT_CMD, 2, { 0x00, 0xFF} }, + {INIT_CMD, 2, { 0x01, 0x01} }, + {INIT_CMD, 2, { 0x02, 0x00} }, + {INIT_CMD, 2, { 0x03, 0x00} }, + {INIT_CMD, 2, { 0x04, 0x00} }, + {INIT_CMD, 2, { 0x05, 0x00} }, + {INIT_CMD, 2, { 0x06, 0x00} }, + {INIT_CMD, 2, { 0x07, 0x00} }, + {INIT_CMD, 2, { 0x08, 0xC0} }, + {INIT_CMD, 2, { 0x09, 0x00} }, + {INIT_CMD, 2, { 0x0A, 0x00} }, + {INIT_CMD, 2, { 0x0B, 0x04} }, + {INIT_CMD, 2, { 0x0C, 0xE6} }, + {INIT_CMD, 2, { 0x0D, 0x0D} }, + {INIT_CMD, 2, { 0x0F, 0x08} }, + {INIT_CMD, 2, { 0x10, 0xE5} }, + {INIT_CMD, 2, { 0x11, 0xA8} }, + {INIT_CMD, 2, { 0x12, 0xEC} }, + {INIT_CMD, 2, { 0x13, 0x54} }, + {INIT_CMD, 2, { 0x14, 0x5A} }, + {INIT_CMD, 2, { 0x15, 0xD5} }, + {INIT_CMD, 2, { 0x16, 0x23} }, + {INIT_CMD, 2, { 0x17, 0x11} }, + {INIT_CMD, 2, { 0x18, 0x2F} }, + {INIT_CMD, 2, { 0x19, 0x93} }, + {INIT_CMD, 2, { 0x1A, 0xA6} }, + {INIT_CMD, 2, { 0x1B, 0x0F} }, + {INIT_CMD, 2, { 0x1C, 0xFF} }, + {INIT_CMD, 2, { 0x1D, 0xFF} }, + {INIT_CMD, 2, { 0x1E, 0xFF} }, + {INIT_CMD, 2, { 0x1F, 0xFF} }, + {INIT_CMD, 2, { 0x20, 0xFF} }, + {INIT_CMD, 2, { 0x21, 0xFF} }, + {INIT_CMD, 2, { 0x22, 0xFF} }, + {INIT_CMD, 2, { 0x23, 0xFF} }, + {INIT_CMD, 2, { 0x24, 0xFF} }, + {INIT_CMD, 2, { 0x25, 0xFF} }, + {INIT_CMD, 2, { 0x26, 0xFF} }, + {INIT_CMD, 2, { 0x27, 0x1F} }, + {INIT_CMD, 2, { 0x28, 0xC8} }, + {INIT_CMD, 2, { 0x29, 0xFF} }, + {INIT_CMD, 2, { 0x2A, 0xFF} }, + {INIT_CMD, 2, { 0x2B, 0xFF} }, + {INIT_CMD, 2, { 0x2C, 0x07} }, + {INIT_CMD, 2, { 0x2D, 0x03} }, + {INIT_CMD, 2, { 0x33, 0x09} }, + {INIT_CMD, 2, { 0x35, 0x7F} }, + {INIT_CMD, 2, { 0x36, 0x0C} }, + {INIT_CMD, 2, { 0x38, 0x7F} }, + {INIT_CMD, 2, { 0x3A, 0x80} }, + {INIT_CMD, 2, { 0x3B, 0x55} }, + {INIT_CMD, 2, { 0x3C, 0xE2} }, + {INIT_CMD, 2, { 0x3D, 0x32} }, + {INIT_CMD, 2, { 0x3E, 0x00} }, + {INIT_CMD, 2, { 0x3F, 0x58} }, + {INIT_CMD, 2, { 0x40, 0x06} }, + {INIT_CMD, 2, { 0x41, 0x80} }, + {INIT_CMD, 2, { 0x42, 0xCB} }, + {INIT_CMD, 2, { 0x43, 0x2C} }, + {INIT_CMD, 2, { 0x44, 0x61} }, + {INIT_CMD, 2, { 0x45, 0x39} }, + {INIT_CMD, 2, { 0x46, 0x00} }, + {INIT_CMD, 2, { 0x47, 0x00} }, + {INIT_CMD, 2, { 0x48, 0x8B} }, + {INIT_CMD, 2, { 0x49, 0xD2} }, + {INIT_CMD, 2, { 0x4A, 0x01} }, + {INIT_CMD, 2, { 0x4B, 0x00} }, + {INIT_CMD, 2, { 0x4C, 0x10} }, + {INIT_CMD, 2, { 0x4D, 0xC0} }, + {INIT_CMD, 2, { 0x4E, 0x0F} }, + {INIT_CMD, 2, { 0x4F, 0xF1} }, + {INIT_CMD, 2, { 0x50, 0x78} }, + {INIT_CMD, 2, { 0x51, 0x7A} }, + {INIT_CMD, 2, { 0x52, 0x34} }, + {INIT_CMD, 2, { 0x53, 0x99} }, + {INIT_CMD, 2, { 0x54, 0xA2} }, + {INIT_CMD, 2, { 0x55, 0x03} }, + {INIT_CMD, 2, { 0x56, 0x6C} }, + {INIT_CMD, 2, { 0x57, 0x1A} }, + {INIT_CMD, 2, { 0x58, 0x05} }, + {INIT_CMD, 2, { 0x59, 0x30} }, + {INIT_CMD, 2, { 0x5A, 0x1E} }, + {INIT_CMD, 2, { 0x5B, 0x8F} }, + {INIT_CMD, 2, { 0x5C, 0xC7} }, + {INIT_CMD, 2, { 0x5D, 0xE3} }, + {INIT_CMD, 2, { 0x5E, 0xF1} }, + {INIT_CMD, 2, { 0x5F, 0x78} }, + {INIT_CMD, 2, { 0x60, 0x3C} }, + {INIT_CMD, 2, { 0x61, 0x36} }, + {INIT_CMD, 2, { 0x62, 0x1E} }, + {INIT_CMD, 2, { 0x63, 0x1B} }, + {INIT_CMD, 2, { 0x64, 0x8F} }, + {INIT_CMD, 2, { 0x65, 0xC7} }, + {INIT_CMD, 2, { 0x66, 0xE3} }, + {INIT_CMD, 2, { 0x67, 0x31} }, + {INIT_CMD, 2, { 0x68, 0x14} }, + {INIT_CMD, 2, { 0x69, 0x89} }, + {INIT_CMD, 2, { 0x6A, 0x70} }, + {INIT_CMD, 2, { 0x6B, 0x8C} }, + {INIT_CMD, 2, { 0x6C, 0x8D} }, + {INIT_CMD, 2, { 0x6D, 0x8D} }, + {INIT_CMD, 2, { 0x6E, 0x8D} }, + {INIT_CMD, 2, { 0x6F, 0x8D} }, + {INIT_CMD, 2, { 0x70, 0xC7} }, + {INIT_CMD, 2, { 0x71, 0xE3} }, + {INIT_CMD, 2, { 0x72, 0xF1} }, + {INIT_CMD, 2, { 0x73, 0xD8} }, + {INIT_CMD, 2, { 0x74, 0xD8} }, + {INIT_CMD, 2, { 0x75, 0xD8} }, + {INIT_CMD, 2, { 0x76, 0x18} }, + {INIT_CMD, 2, { 0x77, 0x00} }, + {INIT_CMD, 2, { 0x78, 0x00} }, + {INIT_CMD, 2, { 0x79, 0x00} }, + {INIT_CMD, 2, { 0x7A, 0xC6} }, + {INIT_CMD, 2, { 0x7B, 0xC6} }, + {INIT_CMD, 2, { 0x7C, 0xC6} }, + {INIT_CMD, 2, { 0x7D, 0xC6} }, + {INIT_CMD, 2, { 0x7E, 0xC6} }, + {INIT_CMD, 2, { 0x7F, 0xE3} }, + {INIT_CMD, 2, { 0x0B, 0x04} }, + {INIT_CMD, 2, { 0xB1, 0x03} }, + {INIT_CMD, 2, { 0x2C, 0x2C} }, + {INIT_CMD, 2, { 0xB1, 0x00} }, + {INIT_CMD, 2, { 0x89, 0x03} }, + {INIT_CMD, 1, {0x11} }, + {DELAY_CMD, 0x78, {} }, + {INIT_CMD, 1, {0x29} }, + {DELAY_CMD, 0x14, {} }, +}; + +struct panel_info flapjack_panel_info[] = { + PANEL(PANEL_FLAPJACK_BOE_TV101WUM_NG0, + 74000, + flapjack_boe_tv101wum_edid, + boe_tv101wum_lcm_init_cmd), + PANEL(PANEL_FLAPJACK_BOE_TV080WUM_NG0, + 212000, + flapjack_boe_tv080wum_edid, + boe_tv080wum_lcm_init_cmd), + PANEL(PANEL_FLAPJACK_INX_OTA7290D10P, + 1191000, + flapjack_inx_ota7290d10p_edid, + inx_ota7290d10p_lcm_init_cmd), + PANEL(PANEL_FLAPJACK_AUO_NT51021D8P, + 1027000, + flapjack_auo_nt51021d8p_edid, + auo_nt51021d8p_lcm_init_cmd), + {{PANEL_FLAPJACK_UNKNOWN}, "PANEL_FLAPJACK_UNKNOWN", + 0, NULL, NULL, 0}, +}; + +static union panel_id get_panel_id_from_adc(int channel, + struct board_display_intf *intf) +{ + uint32_t ver = board_id(); + + if (ver == BOARD_ID_UNKNOWN || ver < 3) { + int id; + int value = auxadc_get_voltage(channel); + + for (id = 0; id < intf->all_panel_info_size; id++) { + if (ABS(value - intf->all_panel_info[id].voltage) < tolerance) + return intf->all_panel_info[id].disp_id; + } + + return (union panel_id)PANEL_FLAPJACK_UNKNOWN; + } else + return (union panel_id)((sku_id() >> FLAPJACK_PANEL_ID_BIT_POSITION) & 0xf); +} + + +static union panel_id flapjack_get_panel_id(struct board_display_intf *intf) +{ + union panel_id id; + + id = get_panel_id_from_adc(FLAPJACK_PANEL_ADC_ID, + intf); + return id; +}; + +static bool flapjack_is_panel_id_valid(union panel_id id) +{ + if (id.value < PANEL_FLAPJACK_UNKNOWN) + return true; + return false; +}; + +static int flapjack_backlight(struct board_display_intf *intf) +{ + configure_backlight(); + return 0; +}; + +static int flapjack_power(struct board_display_intf *intf) +{ + int result = 0; + switch (intf->cur_panel_info->disp_id.value) { + case PANEL_FLAPJACK_BOE_HIMAX8279D10P: + case PANEL_FLAPJACK_BOE_HIMAX8279D8P: + case PANEL_FLAPJACK_INX_OTA7290D10P: + case PANEL_FLAPJACK_AUO_NT51021D8P: + gpio_output(PP3300_LCM_EN, 1); + gpio_output(PP1800_LCM_EN, 1); + + gpio_output(GPIO(LCM_RST), 0); + mdelay(20); + gpio_output(GPIO(LCM_RST), 1); + mdelay(10); + break; + case PANEL_FLAPJACK_UNKNOWN: + default: + result = ERR; + break; + } + return result; +}; + +struct board_display_intf flapjack_display_intf = { + .board = "flapjack", + .all_panel_info = flapjack_panel_info, + .all_panel_info_size = ARRAY_SIZE(flapjack_panel_info), + .cur_panel_info = NULL, + .get_panel_id = &flapjack_get_panel_id, + .is_panel_id_valid = &flapjack_is_panel_id_valid, + .backlight = &flapjack_backlight, + .power = &flapjack_power, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/32840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e50df59de3db9ed6efcccbd01b553c21f793a3f Gerrit-Change-Number: 32840 Gerrit-PatchSet: 1 Gerrit-Owner: Jerry Han <hanxu5(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/braswell: select SOUTHBRIDGE_INTEL_COMMON
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33204 Change subject: soc/intel/braswell: select SOUTHBRIDGE_INTEL_COMMON ...................................................................... soc/intel/braswell: select SOUTHBRIDGE_INTEL_COMMON Use the sb/intel/common/reset.c implementation. Change-Id: I9342f16c947d5e5eb768e426c5ab95c372f95c76 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/braswell/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/33204/1 diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index ed5c972..b2702f0 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -33,7 +33,6 @@ select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_HDA - select SOC_INTEL_COMMON_RESET select SMM_TSEG select SMP select SPI_FLASH @@ -50,6 +49,7 @@ select INTEL_GMA_ACPI select INTEL_GMA_SWSMISCI select CPU_INTEL_COMMON + select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS config VBOOT -- To view, visit https://review.coreboot.org/c/coreboot/+/33204 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9342f16c947d5e5eb768e426c5ab95c372f95c76 Gerrit-Change-Number: 33204 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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