coreboot-gerrit May 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: nb/amd/pi/00730F01/northbridge.c: Use generic allocation functions
by Michał Żygowski (Code Review) 06 May '21

06 May '21

Attention is currently required from: Nico Huber, Krystian Hebel, Kyösti Mälkki, Felix Held. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52926 ) Change subject: nb/amd/pi/00730F01/northbridge.c: Use generic allocation functions ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > OMG 100% coverage :) I always thought there was another mainboard with this northbridge... […] BTW family14 is in the same topic. Trinity and Kabini should follow soon. -- To view, visit https://review.coreboot.org/c/coreboot/+/52926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8dd5e40bce513c5ba7f1d42a06e7ab0846666942 Gerrit-Change-Number: 52926 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 06 May 2021 09:28:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: nb/amd/pi/00730F01/northbridge.c: Use generic allocation functions
by Michał Żygowski (Code Review) 06 May '21

06 May '21

Attention is currently required from: Nico Huber, Krystian Hebel, Kyösti Mälkki, Felix Held. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52926 ) Change subject: nb/amd/pi/00730F01/northbridge.c: Use generic allocation functions ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > had a look and pcengines/apu2 is the only mainboard that uses this northbridge, so i'd say you have […] OMG 100% coverage :) I always thought there was another mainboard with this northbridge... Well, good for me. Thanks Felix for looking into it. -- To view, visit https://review.coreboot.org/c/coreboot/+/52926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8dd5e40bce513c5ba7f1d42a06e7ab0846666942 Gerrit-Change-Number: 52926 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 06 May 2021 09:27:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: Revert "soc/intel/xeon_sp: Fix devices list in the DMAR DRHD structure"
by Arthur Heymans (Code Review) 06 May '21

06 May '21

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52898 ) Change subject: Revert "soc/intel/xeon_sp: Fix devices list in the DMAR DRHD structure" ...................................................................... Revert "soc/intel/xeon_sp: Fix devices list in the DMAR DRHD structure" This reverts commit 8122b3f6123158024ed2844af17289a9abb98036. This broke DMAR. DRHD defines the scope of the device entries below. Change-Id: Iac4858f774fa3811da43f7697a9392daba4b4fba Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52898 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/xeon_sp/nb_acpi.c 1 file changed, 13 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c index 3b2fba9..19c3921 100644 --- a/src/soc/intel/xeon_sp/nb_acpi.c +++ b/src/soc/intel/xeon_sp/nb_acpi.c @@ -198,6 +198,19 @@ if (!reg_base) return current; + // Add DRHD Hardware Unit + if (socket == 0 && stack == CSTACK) { + printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " + "Register Base Address: 0x%x\n", + DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base); + current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, + pcie_seg, reg_base); + } else { + printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " + "Register Base Address: 0x%x\n", 0, pcie_seg, reg_base); + current += acpi_create_dmar_drhd(current, 0, pcie_seg, reg_base); + } + // Add PCH IOAPIC if (socket == 0 && stack == CSTACK) { union p2sb_bdf ioapic_bdf = p2sb_get_ioapic_bdf(); @@ -263,19 +276,6 @@ } } - // Add DRHD Hardware Unit - if (socket == 0 && stack == CSTACK) { - printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " - "Register Base Address: 0x%x\n", - DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base); - current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, - pcie_seg, reg_base); - } else { - printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " - "Register Base Address: 0x%x\n", 0, pcie_seg, reg_base); - current += acpi_create_dmar_drhd(current, 0, pcie_seg, reg_base); - } - acpi_dmar_drhd_fixup(tmp, current); return current; -- To view, visit https://review.coreboot.org/c/coreboot/+/52898 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac4858f774fa3811da43f7697a9392daba4b4fba Gerrit-Change-Number: 52898 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Revert "soc/intel/xeon_sp: Fix devices list in the DMAR DRHD structure"
by Arthur Heymans (Code Review) 06 May '21

06 May '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Morgan Jang. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52898 ) Change subject: Revert "soc/intel/xeon_sp: Fix devices list in the DMAR DRHD structure" ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52898/comment/78376075_1f1eaa43 PS1, Line 10: This broke DMAR. DRHD defines the scope of the device entries below. > Could you please add the error messages that the broken DMAR caused? Nothing too useful I fear: "One of DRHD structure fields has incorrect value: type, flags, length or address of configuration registers differs from value of programmed into VTD_GSTS base address register" from the CBnT SINIT ACM. -- To view, visit https://review.coreboot.org/c/coreboot/+/52898 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac4858f774fa3811da43f7697a9392daba4b4fba Gerrit-Change-Number: 52898 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Comment-Date: Thu, 06 May 2021 09:10:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: tests: Enable config override for tests
by Jakub Czapiga (Code Review) 06 May '21

06 May '21

Attention is currently required from: Paul Fagerburg, Julius Werner, Jan Dabros. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52937 ) Change subject: tests: Enable config override for tests ...................................................................... Patch Set 2: (4 comments) File tests/Makefile.inc: https://review.coreboot.org/c/coreboot/+/52937/comment/9f0f41ac_6e92a994 PS1, Line 88: $(eval $(1)-config-file := $(obj)/$(1)/config.h) > I'm confused why this needs to be an eval? I think you can just do […] Oh, eval is not required. It is here, because I had problems with this assignment at the beginning. :) https://review.coreboot.org/c/coreboot/+/52937/comment/5687ca75_2dac5d7a PS1, Line 89: $($(1)-config-file): $(TEST_KCONFIG_AUTOHEADER) > nit: Doesn't really need to be a separate line on its own. Done https://review.coreboot.org/c/coreboot/+/52937/comment/99b80a8b_99624789 PS1, Line 97: printf '#ifdef %s\n' "$$$$key" >> $$@; \ > nit: don't really need the #ifdef wrapper around the #undef For some reason I was convinced that compiler will report errors when I will use #undef on non-existent symbol. Fixed https://review.coreboot.org/c/coreboot/+/52937/comment/9605aff1_09eac097 PS1, Line 107: $(TEST_KCONFIG_AUTOHEADER) > Just replace this with $(1)-config-file, then you don't need the extra line above Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1aeb78362c2609fbefbfd91c0f58ec19ed258ee1 Gerrit-Change-Number: 52937 Gerrit-PatchSet: 2 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Comment-Date: Thu, 06 May 2021 09:05:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: cezanne/psp_verstage: populate a/b firmware
by Arthur Heymans (Code Review) 06 May '21

06 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Kangheui Won, Felix Held. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52961 ) Change subject: cezanne/psp_verstage: populate a/b firmware ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/guybrush/Kconfig: https://review.coreboot.org/c/coreboot/+/52961/comment/dce2ce76_d37a0a91 PS1, Line 74: config CEZANNE_FW_A_POSITION : hex : default 0xFF012040 : depends on VBOOT_SLOTS_RW_AB : help : Location of the AMD firmware in the RW_A region. This is the : start of the RW-A region + 64 bytes for the cbfs header. : : config CEZANNE_FW_B_POSITION : hex : default 0xFF312040 : depends on VBOOT_SLOTS_RW_AB : help : Location of the AMD firmware in the RW_B region. This is the : start of the RW-A region + 64 bytes for the cbfs header. Please parse $(obj)/fmap_config.h to figure this out instead of hardcoding it in Kconfig which has to be manually maintained to match the fmap. -- To view, visit https://review.coreboot.org/c/coreboot/+/52961 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb31afa7a513f01593b2af75515a170dfca8d360 Gerrit-Change-Number: 52961 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 06 May 2021 08:59:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: acpi: Add function to create DRTM table
by Michał Żygowski (Code Review) 06 May '21

06 May '21

Attention is currently required from: Lance Zhao. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51580 ) Change subject: acpi: Add function to create DRTM table ...................................................................... Patch Set 3: (1 comment) File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/51580/comment/9252469f_b3c0d740 PS3, Line 441: return > Do need to clear size as well to zero? The size will still be zero due to memset in line 485. No need to zero it. -- To view, visit https://review.coreboot.org/c/coreboot/+/51580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I025fc13ca2aad977b87399e2c3183872ea291120 Gerrit-Change-Number: 51580 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao Gerrit-Comment-Date: Thu, 06 May 2021 08:57:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Lance Zhao Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Program CPU PCIE RP GPIOs in early GPIO
by Rizwan Qureshi (Code Review) 06 May '21

06 May '21

Attention is currently required from: Bora Guvendik, Anil Kumar K, Furquan Shaikh, Maulik V Vaghela, Sugnan Prabhu S, Bernardo Perez Priego, Ronak Kanabar. Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52270 ) Change subject: mb/intel/adlrvp: Program CPU PCIE RP GPIOs in early GPIO ...................................................................... Patch Set 12: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieda6b6c31ce5bd5e84e4efe544bfc659283ce6f1 Gerrit-Change-Number: 52270 Gerrit-PatchSet: 12 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Thu, 06 May 2021 08:56:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: acpi: Add DRTM table definition
by Michał Żygowski (Code Review) 06 May '21

06 May '21

Attention is currently required from: Lance Zhao. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51578 ) Change subject: acpi: Add DRTM table definition ...................................................................... Patch Set 2: (3 comments) File src/include/acpi/acpi.h: https://review.coreboot.org/c/coreboot/+/51578/comment/9a586336_f82fd393 PS2, Line 75: DRTM > Original people have those names in order from A~Z, but that seems breaked by ECDT and LPIT. Okay, I will arrange them A~Z https://review.coreboot.org/c/coreboot/+/51578/comment/29b0b1c6_4db99311 PS2, Line 577: /* drtm_validated_tables_list_t : drtm_resources_t : drtm_dps_t */ > For future or anything else? Please list the reason here or in commit. These are the contents of DRTM ACPI table, however due to multiple undefined length tables along the way (and not at the end of the table), we cannot put it inside the structure. https://review.coreboot.org/c/coreboot/+/51578/comment/42d0b4ff_0f3022bf PS2, Line 600: u64 dps_supported[2] > shall that be […] According to https://trustedcomputinggroup.org/wp-content/uploads/TCG_D-RTM_Architecture… section 4.6.3.5 these fields are 64 bit long. -- To view, visit https://review.coreboot.org/c/coreboot/+/51578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I995ac60677d6f3fcc2979e65ecd06c0c7a1b8c10 Gerrit-Change-Number: 51578 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao Gerrit-Comment-Date: Thu, 06 May 2021 08:53:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Lance Zhao Gerrit-MessageType: comment

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Change in coreboot[master]: mb/dell: Add OptiPlex 3010
by Michał Żygowski (Code Review) 06 May '21

06 May '21

Attention is currently required from: Martin Roth, Paul Menzel, Angel Pons, Marty E. Plummer. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51087 ) Change subject: mb/dell: Add OptiPlex 3010 ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > coreboot-4.13-2425-gd5c8a15d74 Tue Mar 2 23:14:06 UTC 2021 bootblock starting (log level: 7)... […] The assertion is related to the fact that EMI base address is not yet set. Are you sure you are calling sch5545_early_init before attempting any SCH5545 EC configuration? Look at my optiplex 9010 port and see what is the order of function calls. -- To view, visit https://review.coreboot.org/c/coreboot/+/51087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a75ea7867ae054497ade269709a3dc19c778ce5 Gerrit-Change-Number: 51087 Gerrit-PatchSet: 1 Gerrit-Owner: Marty E. Plummer <hanetzer(a)startmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Marty E. Plummer <hanetzer(a)startmail.com> Gerrit-Comment-Date: Thu, 06 May 2021 08:47:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Marty E. Plummer <hanetzer(a)startmail.com> Gerrit-MessageType: comment

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coreboot-gerrit May 2021