coreboot-gerrit May 2021

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Change in coreboot[master]: Documentation: Add suggestion to document flag days
by Piotr Król (Code Review) 06 May '21

06 May '21

Attention is currently required from: Martin Roth, Julius Werner, Felix Held. Piotr Król has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52576 ) Change subject: Documentation: Add suggestion to document flag days ...................................................................... Patch Set 1: (1 comment) File Documentation/getting_started/gerrit_guidelines.md: https://review.coreboot.org/c/coreboot/+/52576/comment/7f4095a0_803164ef PS1, Line 332: requires a change in all mainboards using it) needs to be documented. > I think this is your real problem tbh, and it's one of your own making. Why isn't your code upstream? Google had a downstream fork of coreboot for years, and we suffered immensely under the constant back and forward porting effort just like you describe here, until we eventually learned our lesson forced everything to be landed upstream first before we would ship it. I don't think that this is any "10k+ employees vs small company" difference, the effort is still the same, and the answer is just that working directly upstream is the only way to prevent all that churn. (Google may have 10k+ employees but they're not all working on coreboot, btw. It's more like 20 or so.) We can try to upstream things, but some customers requirements are bizarre. To count few: 1. Sign of life - certain string showing as early as possible on platform boot 2. sortbootorder as payload - would payload supporting only one vendor will be merged to coreboot? 3. Custom SeaBIOS features which SeaBIOS upstream won't accept - this is general pattern related to other payloads (memtest, ipxe), including customization and configuration of those payloads 4. Experimental uCode inclusion 5. ACPI difference, mentioned in email thread, required for OS compatibility 6. Runtime configuration 7. CI/CD related stuff etc. I don't think upstream is the place for any customer requirement. As you said before there should be fork on certain point to provide stability and working always with upstream and doing "stable" releases on upstream seem to be against that argument. There are also features which simply pending upstream, there are things which are under review. We trying to be as close to upstream as possible using resources we have. Difference in budget between small player and huge player is significant. Maybe we should be clear about saying that coreboot is too expensive for small OEM/ODM, they should go to IBVs. -- To view, visit https://review.coreboot.org/c/coreboot/+/52576 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7c01a0f1008821ebbda43a426ba1e3d6410e861 Gerrit-Change-Number: 52576 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 06 May 2021 11:41:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/magolor: Select touchscreen panel size based on ...
by David Wu (Code Review) 06 May '21

06 May '21

Attention is currently required from: David Wu, Henry Sun. Hello build bot (Jenkins), Henry Sun, Marco Chen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52851 to look at the new patch set (#5). Change subject: mb/google/dedede/var/magolor: Select touchscreen panel size based on SSFC value ...................................................................... mb/google/dedede/var/magolor: Select touchscreen panel size based on SSFC value Select tocuhscreen panel size for 11" and 14", based on the value set in the SSFC_CONFIG. BUG=b:186609348 TEST=build and boot to OS. Change-Id: I087ea677a8865fc8c5b3f7c9773bd7f97924dbb3 Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/magolor/overridetree.cb 1 file changed, 30 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/52851/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/52851 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I087ea677a8865fc8c5b3f7c9773bd7f97924dbb3 Gerrit-Change-Number: 52851 Gerrit-PatchSet: 5 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: UPDATE 3rdparty/intel-sec-tools
by Christian Walter (Code Review) 06 May '21

06 May '21

Attention is currently required from: Arthur Heymans. Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52971 ) Change subject: UPDATE 3rdparty/intel-sec-tools ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52971 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20379e9723fa18e0ebfb0622c050524d4e6d2717 Gerrit-Change-Number: 52971 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 06 May 2021 11:05:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: UPDATE 3rdparty/intel-sec-tools
by Arthur Heymans (Code Review) 06 May '21

06 May '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52971 ) Change subject: UPDATE 3rdparty/intel-sec-tools ...................................................................... UPDATE 3rdparty/intel-sec-tools Some changes: - bg-prov got renamed to cbnt-prov - cbfs support was added which means that providing IBB.Base/Size separatly is not required anymore. Also fspt.bin gets added as an IBB to secure the root of trust. Change-Id: I20379e9723fa18e0ebfb0622c050524d4e6d2717 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M 3rdparty/intel-sec-tools M src/security/intel/cbnt/Makefile.inc 2 files changed, 4 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/52971/1 diff --git a/3rdparty/intel-sec-tools b/3rdparty/intel-sec-tools index 2b028cc..875763e 160000 --- a/3rdparty/intel-sec-tools +++ b/3rdparty/intel-sec-tools @@ -1 +1 @@ -Subproject commit 2b028cc0e3cdaf1aa3110b6367eb232e9ec9d9c8 +Subproject commit 875763e421ed3a76ec0e0f51c4ed93c6a0038771 diff --git a/src/security/intel/cbnt/Makefile.inc b/src/security/intel/cbnt/Makefile.inc index 93c2aff..c20a3dd 100644 --- a/src/security/intel/cbnt/Makefile.inc +++ b/src/security/intel/cbnt/Makefile.inc @@ -28,7 +28,7 @@ cd 3rdparty/intel-sec-tools; \ GO111MODULE=on go mod download; \ GO111MODULE=on go mod verify; \ - GO111MODULE=on go build -o $(top)/$@ cmd/bg-prov/*.go + GO111MODULE=on go build -o $(top)/$@ cmd/cbnt-prov/*.go $(CBNT_CFG): $(call strip_quotes, $(CONFIG_INTEL_CBNT_CBNT_PROV_CFG_FILE)) cp $(CONFIG_INTEL_CBNT_CBNT_PROV_CFG_FILE) $@ @@ -50,10 +50,8 @@ --ibbflags=$(CONFIG_INTEL_CBNT_IBB_FLAGS) \ --entrypoint=$(shell printf "%d" 0xfffffff0) \ --ibbhash=11,4,12 \ - --ibbsegbase=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_C_ENV_BOOTBLOCK_SIZE)) 1) \ - --ibbsegsize=$(shell printf "%d" $(CONFIG_C_ENV_BOOTBLOCK_SIZE)) \ - --ibbsegflag=0 \ - --sintmin=$(CONFIG_INTEL_CBNT_SINIT_SVN) \ + --coreboot \ + --sinitmin=$(CONFIG_INTEL_CBNT_SINIT_SVN) \ --txtflags=0 \ --powerdowninterval=$(CONFIG_INTEL_CBNT_PD_INTERVAL) \ --acpibaseoffset=$(shell printf "%d" $(CONFIG_INTEL_ACPI_BASE_ADDRESS)) \ -- To view, visit https://review.coreboot.org/c/coreboot/+/52971 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20379e9723fa18e0ebfb0622c050524d4e6d2717 Gerrit-Change-Number: 52971 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: security/intel/cbnt: Rename bg-prov to cbnt-prov
by Arthur Heymans (Code Review) 06 May '21

06 May '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52970 ) Change subject: security/intel/cbnt: Rename bg-prov to cbnt-prov ...................................................................... security/intel/cbnt: Rename bg-prov to cbnt-prov This prepares for updating the intel-sec-tools submodule pointer. In that submodule bg-prov got renamed to cbnt-prov as Intel Bootguard uses different structures and will require a different tool. Change-Id: I54a9f458e124d355d50b5edd8694dee39657bc0d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/security/intel/cbnt/Kconfig M src/security/intel/cbnt/Makefile.inc 2 files changed, 34 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/52970/1 diff --git a/src/security/intel/cbnt/Kconfig b/src/security/intel/cbnt/Kconfig index 9208ab4..a602cca 100644 --- a/src/security/intel/cbnt/Kconfig +++ b/src/security/intel/cbnt/Kconfig @@ -22,7 +22,7 @@ default y select INTEL_CBNT_NEED_KM_PUB_KEY select INTEL_CBNT_NEED_KM_PRIV_KEY if !INTEL_CBNT_KM_ONLY_UNSIGNED - select INTEL_CBNT_NEED_BPM_PUB_KEY if !INTEL_CBNT_BG_PROV_KM_USE_CFG_FILE + select INTEL_CBNT_NEED_BPM_PUB_KEY if !INTEL_CBNT_CBNT_PROV_KM_USE_CFG_FILE help Select y to generate the Key Manifest (KM). Select n to include a KM binary. @@ -40,7 +40,7 @@ "$ ifittool -r COREBOOT -a -n key_manifest.bin -t 11 -s 12 -f build/coreboot.rom" '-s 12' where 12 is CONFIG_CPU_INTEL_NUM_FIT_ENTRIES. -config INTEL_CBNT_BG_PROV_KM_USE_CFG_FILE +config INTEL_CBNT_CBNT_PROV_KM_USE_CFG_FILE bool "KM: use a CBnT json config file" depends on INTEL_CBNT_GENERATE_KM default y @@ -69,7 +69,7 @@ "$ ifittool -r COREBOOT -a -n boot_policy_manifest.bin -t 12 -s 12 -f build/coreboot.rom" '-s 12' where 12 is CONFIG_CPU_INTEL_NUM_FIT_ENTRIES. -config INTEL_CBNT_BG_PROV_BPM_USE_CFG_FILE +config INTEL_CBNT_CBNT_PROV_BPM_USE_CFG_FILE bool "BPM: use a CBnT json config file" depends on INTEL_CBNT_GENERATE_BPM default y @@ -77,9 +77,9 @@ Select y to generate BPM from a json config file. Select n to generate BPM from Kconfig options -config INTEL_CBNT_BG_PROV_CFG_FILE +config INTEL_CBNT_CBNT_PROV_CFG_FILE string "CBnT json config file" - depends on INTEL_CBNT_BG_PROV_KM_USE_CFG_FILE || INTEL_CBNT_BG_PROV_BPM_USE_CFG_FILE + depends on INTEL_CBNT_CBNT_PROV_KM_USE_CFG_FILE || INTEL_CBNT_CBNT_PROV_BPM_USE_CFG_FILE help Location of the bg-prov json config file. Either get a sample JSON config file: @@ -123,7 +123,7 @@ help Location of the boot policy manifest (BPM) private key file in .pem format. -if !INTEL_CBNT_BG_PROV_KM_USE_CFG_FILE && INTEL_CBNT_GENERATE_KM +if !INTEL_CBNT_CBNT_PROV_KM_USE_CFG_FILE && INTEL_CBNT_GENERATE_KM menu "KM options" @@ -160,9 +160,9 @@ endmenu -endif # !INTEL_CBNT_BG_PROV_KM_USE_CFG_FILE +endif # !INTEL_CBNT_CBNT_PROV_KM_USE_CFG_FILE -if !INTEL_CBNT_BG_PROV_BPM_USE_CFG_FILE && INTEL_CBNT_GENERATE_BPM +if !INTEL_CBNT_CBNT_PROV_BPM_USE_CFG_FILE && INTEL_CBNT_GENERATE_BPM menu "BPM options" config INTEL_CBNT_BPM_REVISION @@ -221,7 +221,7 @@ endmenu -endif # !INTEL_CBNT_BG_PROV_BPM_USE_CFG_FILE +endif # !INTEL_CBNT_CBNT_PROV_BPM_USE_CFG_FILE config INTEL_CBNT_KEY_MANIFEST_BINARY string "KM (Key Manifest) binary location" diff --git a/src/security/intel/cbnt/Makefile.inc b/src/security/intel/cbnt/Makefile.inc index 0eea0a7..93c2aff 100644 --- a/src/security/intel/cbnt/Makefile.inc +++ b/src/security/intel/cbnt/Makefile.inc @@ -20,29 +20,29 @@ cp $< $@ endif -BG_PROV:=$(obj)/bg-prov +CBNT_PROV:=$(obj)/cbnt-prov CBNT_CFG:=$(obj)/cbnt.json -$(BG_PROV): - printf " BG_PROV building tool\n" +$(CBNT_PROV): + printf " CBNT_PROV building tool\n" cd 3rdparty/intel-sec-tools; \ GO111MODULE=on go mod download; \ GO111MODULE=on go mod verify; \ GO111MODULE=on go build -o $(top)/$@ cmd/bg-prov/*.go -$(CBNT_CFG): $(call strip_quotes, $(CONFIG_INTEL_CBNT_BG_PROV_CFG_FILE)) - cp $(CONFIG_INTEL_CBNT_BG_PROV_CFG_FILE) $@ +$(CBNT_CFG): $(call strip_quotes, $(CONFIG_INTEL_CBNT_CBNT_PROV_CFG_FILE)) + cp $(CONFIG_INTEL_CBNT_CBNT_PROV_CFG_FILE) $@ ifeq ($(CONFIG_INTEL_CBNT_GENERATE_BPM),y) -ifeq ($(CONFIG_INTEL_CBNT_BG_PROV_BPM_USE_CFG_FILE),y) -$(obj)/bpm_unsigned.bin: $(obj)/coreboot.rom $(BG_PROV) $(CBNT_CFG) - printf " BG_PROV creating unsigned BPM using config file\n" - $(BG_PROV) bpm-gen $@ $< --config=$(CBNT_CFG) --cut +ifeq ($(CONFIG_INTEL_CBNT_CBNT_PROV_BPM_USE_CFG_FILE),y) +$(obj)/bpm_unsigned.bin: $(obj)/coreboot.rom $(CBNT_PROV) $(CBNT_CFG) + printf " CBNT_PROV creating unsigned BPM using config file\n" + $(CBNT_PROV) bpm-gen $@ $< --config=$(CBNT_CFG) --cut else -$(obj)/bpm_unsigned.bin: $(obj)/coreboot.rom $(BG_PROV) - printf " BG_PROV creating unsigned BPM\n" +$(obj)/bpm_unsigned.bin: $(obj)/coreboot.rom $(CBNT_PROV) + printf " CBNT_PROV creating unsigned BPM\n" # SHA256, SHA1, SHA384 for digest - $(BG_PROV) bpm-gen $@ $< --revision=$(CONFIG_INTEL_CBNT_BPM_REVISION) \ + $(CBNT_PROV) bpm-gen $@ $< --revision=$(CONFIG_INTEL_CBNT_BPM_REVISION) \ --svn=$(CONFIG_INTEL_CBNT_BPM_SVN) \ --acmsvn=$(CONFIG_INTEL_CBNT_ACM_SVN) \ --nems=$(CONFIG_INTEL_CBNT_NUM_NEM_PAGES) \ @@ -73,9 +73,9 @@ @printf "$$ cbfstool build/coreboot.rom add -f bpm.bin -n boot_policy_manifest.bin -t raw -a 16\n" @printf "$$ ifittool -r COREBOOT -a -n boot_policy_manifest.bin -t 12 -s 12 -f build/coreboot.rom\n" else -$(obj)/bpm.bin: $(obj)/bpm_unsigned.bin $(BG_PROV) $(call strip_quotes, $(CONFIG_INTEL_CBNT_BPM_PRIV_KEY_FILE)) - printf " BG_PROV signing real BPM\n" - $(BG_PROV) bpm-sign $< $@ $(CONFIG_INTEL_CBNT_BPM_PRIV_KEY_FILE) "" +$(obj)/bpm.bin: $(obj)/bpm_unsigned.bin $(CBNT_PROV) $(call strip_quotes, $(CONFIG_INTEL_CBNT_BPM_PRIV_KEY_FILE)) + printf " CBNT_PROV signing real BPM\n" + $(CBNT_PROV) bpm-sign $< $@ $(CONFIG_INTEL_CBNT_BPM_PRIV_KEY_FILE) "" # Add BPM at the end of the build when all files have been added files_added:: $(obj)/bpm.bin @@ -100,15 +100,15 @@ endif # CONFIG_INTEL_CBNT_GENERATE_BPM ifeq ($(CONFIG_INTEL_CBNT_GENERATE_KM),y) -ifeq ($(CONFIG_INTEL_CBNT_BG_PROV_KM_USE_CFG_FILE),y) -$(obj)/km_unsigned.bin: $(obj)/km_pub.pem $(BG_PROV) $(CBNT_CFG) - printf " BG_PROV creating unsigned KM using config file\n" - $(BG_PROV) km-gen $@ $< --config=$(CBNT_CFG) +ifeq ($(CONFIG_INTEL_CBNT_CBNT_PROV_KM_USE_CFG_FILE),y) +$(obj)/km_unsigned.bin: $(obj)/km_pub.pem $(CBNT_PROV) $(CBNT_CFG) + printf " CBNT_PROV creating unsigned KM using config file\n" + $(CBNT_PROV) km-gen $@ $< --config=$(CBNT_CFG) else PK_HASH_ALG_SHA256:=11 # Hardcode as no other options are available for CBnT -$(obj)/km_unsigned.bin: $(obj)/km_pub.pem $(obj)/bpm_pub.pem $(BG_PROV) - printf " BG_PROV creating unsigned KM\n" - $(BG_PROV) km-gen $@ $< --revision=$(CONFIG_INTEL_CBNT_KM_REVISION) \ +$(obj)/km_unsigned.bin: $(obj)/km_pub.pem $(obj)/bpm_pub.pem $(CBNT_PROV) + printf " CBNT_PROV creating unsigned KM\n" + $(CBNT_PROV) km-gen $@ $< --revision=$(CONFIG_INTEL_CBNT_KM_REVISION) \ --svn=$(CONFIG_INTEL_CBNT_KM_SVN) \ --id=$(CONFIG_INTEL_CBNT_KM_ID) \ --pkhashalg=$(PK_HASH_ALG_SHA256) \ @@ -117,9 +117,9 @@ --out=$(obj)/km_cfg.json endif -$(obj)/km.bin: $(obj)/km_unsigned.bin $(BG_PROV) $(call strip_quotes, $(CONFIG_INTEL_CBNT_KM_PRIV_KEY_FILE)) - printf " BG_PROV signing KM\n" - $(BG_PROV) km-sign $< $@ $(CONFIG_INTEL_CBNT_KM_PRIV_KEY_FILE) "" +$(obj)/km.bin: $(obj)/km_unsigned.bin $(CBNT_PROV) $(call strip_quotes, $(CONFIG_INTEL_CBNT_KM_PRIV_KEY_FILE)) + printf " CBNT_PROV signing KM\n" + $(CBNT_PROV) km-sign $< $@ $(CONFIG_INTEL_CBNT_KM_PRIV_KEY_FILE) "" KM_FILE=$(obj)/km.bin else -- To view, visit https://review.coreboot.org/c/coreboot/+/52970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54a9f458e124d355d50b5edd8694dee39657bc0d Gerrit-Change-Number: 52970 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/cherry: configure GPIOs
by Rex-BC Chen (Code Review) 06 May '21

06 May '21

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yu-Ping Wu, Yidi Lin. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52924 ) Change subject: mb/google/cherry: configure GPIOs ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52924/comment/334b1d78_ca0513e2 PS2, Line 9: GPIO. : Including GPIO_EC_AP_INT, GPIO_SD_CD, GPIO_EC_IN_RW, : GPIO_GSC_AP_INT and GPIO_EN_SPK. > GPIOs, including EC_AP_INT, SD_CD, EC_IN_RW, GSC_AP_INT and EN_SPK. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id553f632412af440d21a3b51e017cb74cc27fd22 Gerrit-Change-Number: 52924 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Comment-Date: Thu, 06 May 2021 10:12:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure as L2 cache
by Rex-BC Chen (Code Review) 06 May '21

06 May '21

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yu-Ping Wu, Yidi Lin. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, Yidi Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52925 to look at the new patch set (#4). Change subject: soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure as L2 cache ...................................................................... soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure as L2 cache Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready. After DRAM is ready, we should invoke disable_l2c_sram to reconfigure the L2C SRAM as L2 cache. Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Change-Id: I8777b0c8471fe17ffffdcb6ad5b7c00fb1d35db1 --- M src/soc/mediatek/mt8195/Makefile.inc A src/soc/mediatek/mt8195/mmu_operations.c M src/soc/mediatek/mt8195/soc.c 3 files changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/52925/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/52925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8777b0c8471fe17ffffdcb6ad5b7c00fb1d35db1 Gerrit-Change-Number: 52925 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: DO-NOT-SUBMIT: MT8195 Cherry review ToT
by Rex-BC Chen (Code Review) 06 May '21

06 May '21

Attention is currently required from: Rex-BC Chen, Yidi Lin. Rex-BC Chen has uploaded a new patch set (#56) to the change originally created by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/52260 ) Change subject: DO-NOT-SUBMIT: MT8195 Cherry review ToT ...................................................................... DO-NOT-SUBMIT: MT8195 Cherry review ToT Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Change-Id: I3ed96b245bbb52501e9b7d6b89ed42468f505ab0 --- M 3rdparty/amd_blobs M 3rdparty/blobs M 3rdparty/intel-microcode M 3rdparty/qc_blobs M README.md 5 files changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/52260/56 -- To view, visit https://review.coreboot.org/c/coreboot/+/52260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ed96b245bbb52501e9b7d6b89ed42468f505ab0 Gerrit-Change-Number: 52260 Gerrit-PatchSet: 56 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: Joel Kitching <kitching(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/cherry: configure GPIOs
by Rex-BC Chen (Code Review) 06 May '21

06 May '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Paul Menzel, Yidi Lin. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, Yidi Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52924 to look at the new patch set (#3). Change subject: mb/google/cherry: configure GPIOs ...................................................................... mb/google/cherry: configure GPIOs Configure Chromebook specific GPIOs, including EC_AP_INT, SD_CD, EC_IN_RW, GSC_AP_INT and EN_SPK. Change-Id: Id553f632412af440d21a3b51e017cb74cc27fd22 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> --- M src/mainboard/google/cherry/bootblock.c M src/mainboard/google/cherry/chromeos.c A src/mainboard/google/cherry/gpio.h 3 files changed, 43 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/52924/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/52924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id553f632412af440d21a3b51e017cb74cc27fd22 Gerrit-Change-Number: 52924 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure as L2 cache
by Rex-BC Chen (Code Review) 06 May '21

06 May '21

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yu-Ping Wu, Yidi Lin. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52925 ) Change subject: soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure as L2 cache ...................................................................... Patch Set 3: (1 comment) File src/soc/mediatek/mt8195/mmu_operations.c: PS3: > This file looks exactly the same as mt8192. […] mtk_soc_after_dram() is different for 8173/8183/8192. Register also different for 8195 and 8192. -- To view, visit https://review.coreboot.org/c/coreboot/+/52925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8777b0c8471fe17ffffdcb6ad5b7c00fb1d35db1 Gerrit-Change-Number: 52925 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Comment-Date: Thu, 06 May 2021 10:10:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit May 2021