coreboot-gerrit May 2021

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Change in coreboot[master]: treewide: Kconfig: replace `def_bool n` by `bool`
by Michael Niewöhner (Code Review) 06 May '21

06 May '21

Michael Niewöhner has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/52809 ) Change subject: treewide: Kconfig: replace `def_bool n` by `bool` ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/52809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27e89c66d18b7b3a5ac425eacea10df8c013814f Gerrit-Change-Number: 52809 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: src/vendorcode/amd/fsp/cezanne/FspmUpd.h: match amd-fsp
by Julian Schroeder (Code Review) 06 May '21

06 May '21

Attention is currently required from: Raul Rangel, Martin Roth, Marshall Dawson, Felix Held. Julian Schroeder has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52909 ) Change subject: src/vendorcode/amd/fsp/cezanne/FspmUpd.h: match amd-fsp ...................................................................... Patch Set 1: (2 comments) File src/vendorcode/amd/fsp/cezanne/FspmUpd.h: https://review.coreboot.org/c/coreboot/+/52909/comment/3fd51736_5541e832 PS1, Line 110: sh_oem > What does the sh_oem stand for? shasta IP, OEM=OriginalEquipment... https://review.coreboot.org/c/coreboot/+/52909/comment/f9dceced_9051016b PS1, Line 110: /** Offset 0x04D7**/ uint8_t sh_oem_usb_config[100]; > hm, there are already some usb-related upds above The AGESA people changed the whole USB setup plumbing. I'll replace the 100 bytes thingy in the next patch when I hook up Coreboot to FSP for USB settings. This just the first step. -- To view, visit https://review.coreboot.org/c/coreboot/+/52909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib40c30e18878db5604ed1104e1e876986212e67d Gerrit-Change-Number: 52909 Gerrit-PatchSet: 1 Gerrit-Owner: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 06 May 2021 15:01:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/pc80/rtc/option.c: Constrain API to integer values
by Felix Held (Code Review) 06 May '21

06 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52637 ) Change subject: drivers/pc80/rtc/option.c: Constrain API to integer values ...................................................................... drivers/pc80/rtc/option.c: Constrain API to integer values None of the options accessed within coreboot is a string, and there are no guarantees that the code works as intended with them. Given that the current option API only supports integers for now, do not try to access options whose type is 's' (string). Change-Id: Ib67b126d972c6d55b77ea5ecfb862b4e9c766fe5 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52637 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/drivers/pc80/rtc/option.c M src/include/option.h 2 files changed, 15 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Patrick Rudolph: Looks good to me, approved diff --git a/src/drivers/pc80/rtc/option.c b/src/drivers/pc80/rtc/option.c index 5cc5ea5..cc4138b 100644 --- a/src/drivers/pc80/rtc/option.c +++ b/src/drivers/pc80/rtc/option.c @@ -84,7 +84,7 @@ return NULL; } -enum cb_err cmos_get_option(void *dest, const char *name) +enum cb_err cmos_get_uint_option(unsigned int *dest, const char *name) { struct cmos_option_table *ct; struct cmos_entries *ce; @@ -99,6 +99,11 @@ return CB_CMOS_OPTION_NOT_FOUND; } + if (ce->config != 'e' && ce->config != 'h') { + printk(BIOS_ERR, "ERROR: CMOS option '%s' is not of integer type.\n", name); + return CB_ERR_ARG; + } + if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC)) return CB_CMOS_CHECKSUM_INVALID; @@ -149,11 +154,10 @@ return CB_SUCCESS; } -enum cb_err cmos_set_option(const char *name, void *value) +enum cb_err cmos_set_uint_option(const char *name, unsigned int *value) { struct cmos_option_table *ct; struct cmos_entries *ce; - unsigned long length; ct = get_cmos_layout(); if (!ct) @@ -165,16 +169,12 @@ return CB_CMOS_OPTION_NOT_FOUND; } - length = ce->length; - if (ce->config == 's') { - length = MAX(strlen((const char *)value) * 8, ce->length - 8); - /* make sure the string is null terminated */ - if (set_cmos_value(ce->bit + ce->length - 8, 8, &(u8[]){0}) - != CB_SUCCESS) - return CB_CMOS_ACCESS_ERROR; + if (ce->config != 'e' && ce->config != 'h') { + printk(BIOS_ERR, "ERROR: CMOS option '%s' is not of integer type.\n", name); + return CB_ERR_ARG; } - if (set_cmos_value(ce->bit, length, value) != CB_SUCCESS) + if (set_cmos_value(ce->bit, ce->length, value) != CB_SUCCESS) return CB_CMOS_ACCESS_ERROR; return CB_SUCCESS; diff --git a/src/include/option.h b/src/include/option.h index e7db02e..8316bd8 100644 --- a/src/include/option.h +++ b/src/include/option.h @@ -7,13 +7,13 @@ void sanitize_cmos(void); -enum cb_err cmos_set_option(const char *name, void *val); -enum cb_err cmos_get_option(void *dest, const char *name); +enum cb_err cmos_set_uint_option(const char *name, unsigned int *value); +enum cb_err cmos_get_uint_option(unsigned int *dest, const char *name); static inline enum cb_err set_uint_option(const char *name, unsigned int value) { if (CONFIG(USE_OPTION_TABLE)) - return cmos_set_option(name, &value); + return cmos_set_uint_option(name, &value); return CB_CMOS_OTABLE_DISABLED; } @@ -22,7 +22,7 @@ { if (CONFIG(USE_OPTION_TABLE)) { unsigned int value = 0; - if (cmos_get_option(&value, name) == CB_SUCCESS) + if (cmos_get_uint_option(&value, name) == CB_SUCCESS) return value; } return fallback; -- To view, visit https://review.coreboot.org/c/coreboot/+/52637 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib67b126d972c6d55b77ea5ecfb862b4e9c766fe5 Gerrit-Change-Number: 52637 Gerrit-PatchSet: 7 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: src: Retype option API to use unsigned integers
by Felix Held (Code Review) 06 May '21

06 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52672 ) Change subject: src: Retype option API to use unsigned integers ...................................................................... src: Retype option API to use unsigned integers The CMOS option system does not support negative integers. Thus, retype and rename the option API functions to reflect this. Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52672 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M src/console/init.c M src/cpu/intel/hyperthreading/intel_sibling.c M src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c M src/drivers/lenovo/hybrid_graphics/romstage.c M src/ec/kontron/it8516e/ec.c M src/ec/lenovo/h8/bluetooth.c M src/ec/lenovo/h8/h8.c M src/ec/lenovo/h8/wwan.c M src/ec/lenovo/pmh7/pmh7.c M src/include/option.h M src/mainboard/asus/am1i-a/BiosCallOuts.c M src/mainboard/asus/p8z77-m_pro/early_init.c M src/mainboard/dell/optiplex_9010/sch5545_ec.c M src/mainboard/getac/p470/early_init.c M src/mainboard/ibase/mb899/superio_hwm.c M src/mainboard/kontron/986lcd-m/early_init.c M src/mainboard/kontron/986lcd-m/mainboard.c M src/mainboard/kontron/bsl6/romstage.c M src/mainboard/kontron/bsl6/variants/boxer26/romstage.c M src/mainboard/kontron/ktqm77/mainboard.c M src/mainboard/lenovo/t430s/variants/t430s/romstage.c M src/mainboard/lenovo/t440p/romstage.c M src/mainboard/lenovo/x60/smihandler.c M src/mainboard/roda/rk886ex/early_init.c M src/mainboard/siemens/chili/romstage.c M src/mainboard/siemens/chili/variants/chili/romstage.c M src/mainboard/supermicro/x10slm-f/mainboard.c M src/northbridge/intel/gm45/igd.c M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/gma.c M src/northbridge/intel/ironlake/raminit.c M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/x4x/early_init.c M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/broadwell/pch/smihandler.c M src/soc/intel/common/block/pmc/pmclib.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/sata.c M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/i82801dx/lpc.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801ix/sata.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/i82801jx/sata.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/sata.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/smihandler.c M src/superio/ite/it8720f/superio.c M src/superio/nuvoton/nct5572d/superio.c M src/superio/nuvoton/npcd378/superio.c M src/superio/winbond/w83627ehg/superio.c M src/superio/winbond/w83627hf/superio.c M src/superio/winbond/w83667hg-a/superio.c 58 files changed, 113 insertions(+), 113 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Patrick Rudolph: Looks good to me, approved Felix Singer: Looks good to me, approved diff --git a/src/console/init.c b/src/console/init.c index fdc1467..a2ceb58 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -26,7 +26,7 @@ console_loglevel = get_console_loglevel(); if (!FIRST_CONSOLE) - console_loglevel = get_int_option("debug_level", console_loglevel); + console_loglevel = get_uint_option("debug_level", console_loglevel); } int console_log_level(int msg_level) diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index 888a2fd..38f6efc 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -21,7 +21,7 @@ /* On the bootstrap processor see if I want sibling cpus enabled */ if (first_time) { first_time = 0; - disable_siblings = get_int_option("hyper_threading", disable_siblings); + disable_siblings = get_uint_option("hyper_threading", disable_siblings); } result = cpuid(1); /* Is hyperthreading supported */ diff --git a/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c b/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c index bae8a54..7a5e20d 100644 --- a/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c +++ b/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c @@ -25,7 +25,7 @@ return; } - mode = get_int_option("hybrid_graphics_mode", HYBRID_GRAPHICS_DEFAULT_GPU); + mode = get_uint_option("hybrid_graphics_mode", HYBRID_GRAPHICS_DEFAULT_GPU); if (mode == HYBRID_GRAPHICS_DISCRETE) { printk(BIOS_DEBUG, "Hybrid graphics:" diff --git a/src/drivers/lenovo/hybrid_graphics/romstage.c b/src/drivers/lenovo/hybrid_graphics/romstage.c index 747c9b7..7cc1610 100644 --- a/src/drivers/lenovo/hybrid_graphics/romstage.c +++ b/src/drivers/lenovo/hybrid_graphics/romstage.c @@ -39,7 +39,7 @@ return; } - mode = get_int_option("hybrid_graphics_mode", HYBRID_GRAPHICS_DEFAULT_GPU); + mode = get_uint_option("hybrid_graphics_mode", HYBRID_GRAPHICS_DEFAULT_GPU); if (mode == HYBRID_GRAPHICS_DISCRETE) { printk(BIOS_DEBUG, "Hybrid graphics:" diff --git a/src/ec/kontron/it8516e/ec.c b/src/ec/kontron/it8516e/ec.c index 0b0e3ac..5288976 100644 --- a/src/ec/kontron/it8516e/ec.c +++ b/src/ec/kontron/it8516e/ec.c @@ -133,13 +133,13 @@ u8 fan_max = config->default_fan_max[fan_idx]; fanX_mode[3] = '1' + fan_idx; - fan_mode = get_int_option(fanX_mode, fan_mode); + fan_mode = get_uint_option(fanX_mode, fan_mode); if (!fan_mode) fan_mode = IT8516E_MODE_AUTO; it8516e_set_fan_mode(fan_idx, fan_mode); fanX_target[3] = '1' + fan_idx; - fan_target = get_int_option(fanX_target, fan_target); + fan_target = get_uint_option(fanX_target, fan_target); switch (fan_mode) { case IT8516E_MODE_AUTO: printk(BIOS_DEBUG, @@ -173,8 +173,8 @@ fanX_min[3] = '1' + fan_idx; fanX_max[3] = '1' + fan_idx; - fan_min = get_int_option(fanX_min, fan_min); - fan_max = get_int_option(fanX_max, fan_max); + fan_min = get_uint_option(fanX_min, fan_min); + fan_max = get_uint_option(fanX_max, fan_max); if (!fan_max || fan_max > 100) /* Constrain fan_max to 100% */ fan_max = 100; @@ -202,7 +202,7 @@ ec_set_ports(find_resource(dev, PNP_IDX_IO1)->base, find_resource(dev, PNP_IDX_IO0)->base); - u8 systemp_type = get_int_option("systemp_type", config->default_systemp); + u8 systemp_type = get_uint_option("systemp_type", config->default_systemp); if (systemp_type >= IT8516E_SYSTEMP_LASTPLUSONE) systemp_type = IT8516E_SYSTEMP_NONE; it8516e_set_systemp_type(systemp_type); diff --git a/src/ec/lenovo/h8/bluetooth.c b/src/ec/lenovo/h8/bluetooth.c index 463e0e3..16fc8dc 100644 --- a/src/ec/lenovo/h8/bluetooth.c +++ b/src/ec/lenovo/h8/bluetooth.c @@ -48,5 +48,5 @@ */ bool h8_bluetooth_nv_enable(void) { - return get_int_option("bluetooth", true); + return get_uint_option("bluetooth", true); } diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index e17f0fb..b081ec8 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -243,7 +243,7 @@ reg8 = conf->config1; if (conf->has_keyboard_backlight) { /* Default to both backlights */ - reg8 = (reg8 & 0xf3) | ((get_int_option("backlight", 0) & 0x3) << 2); + reg8 = (reg8 & 0xf3) | ((get_uint_option("backlight", 0) & 0x3) << 2); } ec_write(H8_CONFIG1, reg8); ec_write(H8_CONFIG2, conf->config2); @@ -253,14 +253,14 @@ beepmask1 = conf->beepmask1; if (conf->has_power_management_beeps) { - if (get_int_option("power_management_beeps", 1) == 0) { + if (get_uint_option("power_management_beeps", 1) == 0) { beepmask0 = 0x00; beepmask1 = 0x00; } } if (conf->has_power_management_beeps) { - if (get_int_option("low_battery_beep", 1)) + if (get_uint_option("low_battery_beep", 1)) beepmask0 |= 2; else beepmask0 &= ~2; @@ -292,14 +292,14 @@ ec_write(H8_FAN_CONTROL, H8_FAN_CONTROL_AUTO); - h8_usb_always_on_enable(get_int_option("usb_always_on", 0)); + h8_usb_always_on_enable(get_uint_option("usb_always_on", 0)); - h8_wlan_enable(get_int_option("wlan", 1)); + h8_wlan_enable(get_uint_option("wlan", 1)); h8_trackpoint_enable(1); h8_usb_power_enable(1); - unsigned int volume = get_int_option("volume", ~0); + unsigned int volume = get_uint_option("volume", ~0); if (volume <= 0xff && !acpi_is_wakeup_s3()) ec_write(H8_VOLUME_CONTROL, volume); @@ -311,16 +311,16 @@ h8_wwan_enable(val); if (conf->has_uwb) - h8_uwb_enable(get_int_option("uwb", 1)); + h8_uwb_enable(get_uint_option("uwb", 1)); - h8_fn_ctrl_swap(get_int_option("fn_ctrl_swap", 0)); + h8_fn_ctrl_swap(get_uint_option("fn_ctrl_swap", 0)); - h8_sticky_fn(get_int_option("sticky_fn", 0)); + h8_sticky_fn(get_uint_option("sticky_fn", 0)); if (CONFIG(H8_HAS_PRIMARY_FN_KEYS)) - f1_to_f12_as_primary(get_int_option("f1_to_f12_as_primary", 1)); + f1_to_f12_as_primary(get_uint_option("f1_to_f12_as_primary", 1)); - h8_charge_priority(get_int_option("first_battery", PRIMARY_BATTERY)); + h8_charge_priority(get_uint_option("first_battery", PRIMARY_BATTERY)); h8_set_audio_mute(0); h8_mb_init(); diff --git a/src/ec/lenovo/h8/wwan.c b/src/ec/lenovo/h8/wwan.c index 90f6b47..685886f 100644 --- a/src/ec/lenovo/h8/wwan.c +++ b/src/ec/lenovo/h8/wwan.c @@ -46,5 +46,5 @@ */ bool h8_wwan_nv_enable(void) { - return get_int_option("wwan", true); + return get_uint_option("wwan", true); } diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index f32c9f1..ebcbcde 100644 --- a/src/ec/lenovo/pmh7/pmh7.c +++ b/src/ec/lenovo/pmh7/pmh7.c @@ -117,9 +117,9 @@ pmh7_backlight_enable(conf->backlight_enable); pmh7_dock_event_enable(conf->dock_event_enable); - pmh7_touchpad_enable(get_int_option("touchpad", 1)); + pmh7_touchpad_enable(get_uint_option("touchpad", 1)); - pmh7_trackpoint_enable(get_int_option("trackpoint", 1)); + pmh7_trackpoint_enable(get_uint_option("trackpoint", 1)); printk(BIOS_INFO, "PMH7: ID %02x Revision %02x\n", pmh7_register_read(EC_LENOVO_PMH7_REG_ID), diff --git a/src/include/option.h b/src/include/option.h index 4de032b..e7db02e 100644 --- a/src/include/option.h +++ b/src/include/option.h @@ -10,7 +10,7 @@ enum cb_err cmos_set_option(const char *name, void *val); enum cb_err cmos_get_option(void *dest, const char *name); -static inline enum cb_err set_int_option(const char *name, int value) +static inline enum cb_err set_uint_option(const char *name, unsigned int value) { if (CONFIG(USE_OPTION_TABLE)) return cmos_set_option(name, &value); @@ -18,10 +18,10 @@ return CB_CMOS_OTABLE_DISABLED; } -static inline int get_int_option(const char *name, const int fallback) +static inline int get_uint_option(const char *name, const unsigned int fallback) { if (CONFIG(USE_OPTION_TABLE)) { - int value = 0; + unsigned int value = 0; if (cmos_get_option(&value, name) == CB_SUCCESS) return value; } diff --git a/src/mainboard/asus/am1i-a/BiosCallOuts.c b/src/mainboard/asus/am1i-a/BiosCallOuts.c index e20f4f4..1e91906 100644 --- a/src/mainboard/asus/am1i-a/BiosCallOuts.c +++ b/src/mainboard/asus/am1i-a/BiosCallOuts.c @@ -87,7 +87,7 @@ FchParams_reset->Mode = 6; /* Read SATA speed setting from CMOS */ - FchParams_reset->SataSetMaxGen2 = get_int_option("sata_speed", 0); + FchParams_reset->SataSetMaxGen2 = get_uint_option("sata_speed", 0); printk(BIOS_DEBUG, "Force SATA 3Gbps mode = %x\n", FchParams_reset->SataSetMaxGen2); } @@ -102,7 +102,7 @@ FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */ /* Read SATA controller mode from CMOS */ - FchParams_env->Sata.SataClass = get_int_option("sata_mode", 0); + FchParams_env->Sata.SataClass = get_uint_option("sata_mode", 0); switch ((SATA_CLASS)FchParams_env->Sata.SataClass) { case SataLegacyIde: diff --git a/src/mainboard/asus/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8z77-m_pro/early_init.c index d7125d6..78ad877 100644 --- a/src/mainboard/asus/p8z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8z77-m_pro/early_init.c @@ -69,15 +69,15 @@ * 3 = Smart Auto : same than Auto, but if OS loads USB3 driver * and reboots, it will keep the USB3.0 speed */ - int usb3_mode = get_int_option("usb3_mode", 1); + unsigned int usb3_mode = get_uint_option("usb3_mode", 1); usb3_mode &= 0x3; /* ensure it's 0/1/2/3 only */ /* Load USB3 pre-OS xHCI driver */ - int usb3_drv = get_int_option("usb3_drv", 1); + unsigned int usb3_drv = get_uint_option("usb3_drv", 1); usb3_drv &= 0x1; /* ensure it's 0/1 only */ /* Use USB3 xHCI streams */ - int usb3_streams = get_int_option("usb3_streams", 1); + unsigned int usb3_streams = get_uint_option("usb3_streams", 1); usb3_streams &= 0x1; /* ensure it's 0/1 only */ struct pei_data pd = { diff --git a/src/mainboard/dell/optiplex_9010/sch5545_ec.c b/src/mainboard/dell/optiplex_9010/sch5545_ec.c index 9e25f18..60cde7d 100644 --- a/src/mainboard/dell/optiplex_9010/sch5545_ec.c +++ b/src/mainboard/dell/optiplex_9010/sch5545_ec.c @@ -656,7 +656,7 @@ ec_read_write_reg(EC_HWM_LDN, 0x02fc, &val_2fc, WRITE_OP); - unsigned int fan_speed_full = get_int_option("fan_full_speed", 0); + unsigned int fan_speed_full = get_uint_option("fan_full_speed", 0); if (fan_speed_full) { printk(BIOS_INFO, "Will set up fans to run at full speed\n"); ec_read_write_reg(EC_HWM_LDN, 0x0080, &val, READ_OP); diff --git a/src/mainboard/getac/p470/early_init.c b/src/mainboard/getac/p470/early_init.c index 1ca9b79..c28d602 100644 --- a/src/mainboard/getac/p470/early_init.c +++ b/src/mainboard/getac/p470/early_init.c @@ -35,7 +35,7 @@ { int lpt_en = 0; - if (get_int_option("lpt", 0)) + if (get_uint_option("lpt", 0)) lpt_en = LPT_LPC_EN; /* enable LPT */ // decode range diff --git a/src/mainboard/ibase/mb899/superio_hwm.c b/src/mainboard/ibase/mb899/superio_hwm.c index e1189a5..f2c313e 100644 --- a/src/mainboard/ibase/mb899/superio_hwm.c +++ b/src/mainboard/ibase/mb899/superio_hwm.c @@ -48,17 +48,17 @@ void hwm_setup(void) { - int cpufan_control = 0, sysfan_control = 0; - int cpufan_speed = 0, sysfan_speed = 0; - int cpufan_temperature = 0, sysfan_temperature = 0; + unsigned int cpufan_control = 0, sysfan_control = 0; + unsigned int cpufan_speed = 0, sysfan_speed = 0; + unsigned int cpufan_temperature = 0, sysfan_temperature = 0; - cpufan_control = get_int_option("cpufan_cruise_control", FAN_CRUISE_CONTROL_DISABLED); - cpufan_speed = get_int_option("cpufan_speed", FAN_SPEED_5625); - //cpufan_temperature = get_int_option("cpufan_temperature", FAN_TEMPERATURE_30DEGC); + cpufan_control = get_uint_option("cpufan_cruise_control", FAN_CRUISE_CONTROL_DISABLED); + cpufan_speed = get_uint_option("cpufan_speed", FAN_SPEED_5625); + //cpufan_temperature = get_uint_option("cpufan_temperature", FAN_TEMPERATURE_30DEGC); - sysfan_control = get_int_option("sysfan_cruise_control", FAN_CRUISE_CONTROL_DISABLED); - sysfan_speed = get_int_option("sysfan_speed", FAN_SPEED_5625); - //sysfan_temperature = get_int_option("sysfan_temperature", FAN_TEMPERATURE_30DEGC); + sysfan_control = get_uint_option("sysfan_cruise_control", FAN_CRUISE_CONTROL_DISABLED); + sysfan_speed = get_uint_option("sysfan_speed", FAN_SPEED_5625); + //sysfan_temperature = get_uint_option("sysfan_temperature", FAN_TEMPERATURE_30DEGC); // pnp_write_hwm5_index(HWM_BASE, 0x31, 0x20); // AVCC high limit // pnp_write_hwm5_index(HWM_BASE, 0x34, 0x06); // VIN2 low limit diff --git a/src/mainboard/kontron/986lcd-m/early_init.c b/src/mainboard/kontron/986lcd-m/early_init.c index ff3babb..5bed24b 100644 --- a/src/mainboard/kontron/986lcd-m/early_init.c +++ b/src/mainboard/kontron/986lcd-m/early_init.c @@ -15,7 +15,7 @@ { int lpt_en = 0; - if (get_int_option("lpt", 0)) + if (get_uint_option("lpt", 0)) lpt_en = LPT_LPC_EN; /* enable LPT */ pci_update_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, ~LPT_LPC_EN, lpt_en); diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index f13731b..f621f9b 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -46,15 +46,15 @@ static void hwm_setup(void) { - int cpufan_control = 0, sysfan_control = 0; - int cpufan_speed = 0, sysfan_speed = 0; - int cpufan_temperature = 0, sysfan_temperature = 0; + unsigned int cpufan_control = 0, sysfan_control = 0; + unsigned int cpufan_speed = 0, sysfan_speed = 0; + unsigned int cpufan_temperature = 0, sysfan_temperature = 0; - cpufan_control = get_int_option("cpufan_cruise_control", FAN_CRUISE_CONTROL_DISABLED); - cpufan_speed = get_int_option("cpufan_speed", FAN_SPEED_5625); + cpufan_control = get_uint_option("cpufan_cruise_control", FAN_CRUISE_CONTROL_DISABLED); + cpufan_speed = get_uint_option("cpufan_speed", FAN_SPEED_5625); - sysfan_control = get_int_option("sysfan_cruise_control", FAN_CRUISE_CONTROL_DISABLED); - sysfan_speed = get_int_option("sysfan_speed", FAN_SPEED_5625); + sysfan_control = get_uint_option("sysfan_cruise_control", FAN_CRUISE_CONTROL_DISABLED); + sysfan_speed = get_uint_option("sysfan_speed", FAN_SPEED_5625); nuvoton_hwm_select_bank(hwm_base, 0); pnp_write_hwm5_index(hwm_base, 0x59, 0x20); /* Diode Selection */ @@ -139,7 +139,7 @@ char cmos_option_name[] = "ethernetx"; snprintf(cmos_option_name, sizeof(cmos_option_name), "ethernet%01d", i); - int ethernet_disable = get_int_option(cmos_option_name, 0); + unsigned int ethernet_disable = get_uint_option(cmos_option_name, 0); if (!ethernet_disable) continue; printk(BIOS_DEBUG, "Disabling Ethernet NIC #%d\n", i); diff --git a/src/mainboard/kontron/bsl6/romstage.c b/src/mainboard/kontron/bsl6/romstage.c index c5cba4d..f38734c 100644 --- a/src/mainboard/kontron/bsl6/romstage.c +++ b/src/mainboard/kontron/bsl6/romstage.c @@ -38,7 +38,7 @@ memory_params->DqPinsInterleaved = true; - const uint8_t ht = get_int_option("hyper_threading", memory_params->HyperThreading); + const uint8_t ht = get_uint_option("hyper_threading", memory_params->HyperThreading); memory_params->HyperThreading = ht; variant_memory_init_params(mupd); diff --git a/src/mainboard/kontron/bsl6/variants/boxer26/romstage.c b/src/mainboard/kontron/bsl6/variants/boxer26/romstage.c index d352522..1985d4e 100644 --- a/src/mainboard/kontron/bsl6/variants/boxer26/romstage.c +++ b/src/mainboard/kontron/bsl6/variants/boxer26/romstage.c @@ -14,7 +14,7 @@ for (i = 0; i < 3; ++i) { nvram_var[sizeof(nvram_var) - 2] = '1' + i; - u8 eth_enable = get_int_option(nvram_var, 1); + u8 eth_enable = get_uint_option(nvram_var, 1); if (!eth_enable) { printk(BIOS_INFO, "Disabling ethernet%u.\n", 1 + i); mupd->FspmConfig.PcieRpEnableMask &= ~(1 << (i + 8)); diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c index 2d5063a..f8ef5383 100644 --- a/src/mainboard/kontron/ktqm77/mainboard.c +++ b/src/mainboard/kontron/ktqm77/mainboard.c @@ -149,7 +149,7 @@ /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); #endif - unsigned int disable = get_int_option("ethernet1", 0); + unsigned int disable = get_uint_option("ethernet1", 0); if (disable) { struct device *nic = pcidev_on_root(0x1c, 2); if (nic) { @@ -157,7 +157,7 @@ nic->enabled = 0; } } - disable = get_int_option("ethernet2", 0); + disable = get_uint_option("ethernet2", 0); if (disable) { struct device *nic = pcidev_on_root(0x1c, 3); if (nic) { diff --git a/src/mainboard/lenovo/t430s/variants/t430s/romstage.c b/src/mainboard/lenovo/t430s/variants/t430s/romstage.c index ff041e7..efcd315 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/romstage.c +++ b/src/mainboard/lenovo/t430s/variants/t430s/romstage.c @@ -33,7 +33,7 @@ void mainboard_early_init(int s3resume) { - u8 enable_peg = get_int_option("enable_dual_graphics", 0); + u8 enable_peg = get_uint_option("enable_dual_graphics", 0); bool power_en = pmh7_dgpu_power_state(); diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c index 817797f..e605453 100644 --- a/src/mainboard/lenovo/t440p/romstage.c +++ b/src/mainboard/lenovo/t440p/romstage.c @@ -22,7 +22,7 @@ void mb_late_romstage_setup(void) { - u8 enable_peg = get_int_option("enable_dual_graphics", 0); + u8 enable_peg = get_uint_option("enable_dual_graphics", 0); bool power_en = pmh7_dgpu_power_state(); diff --git a/src/mainboard/lenovo/x60/smihandler.c b/src/mainboard/lenovo/x60/smihandler.c index 20ca060..e1a97f5 100644 --- a/src/mainboard/lenovo/x60/smihandler.c +++ b/src/mainboard/lenovo/x60/smihandler.c @@ -22,8 +22,8 @@ tmp70 = inb(0x70); tmp72 = inb(0x72); - set_int_option("tft_brightness", pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)); - set_int_option("volume", ec_read(H8_VOLUME_CONTROL)); + set_uint_option("tft_brightness", pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)); + set_uint_option("volume", ec_read(H8_VOLUME_CONTROL)); outb(tmp70, 0x70); outb(tmp72, 0x72); diff --git a/src/mainboard/roda/rk886ex/early_init.c b/src/mainboard/roda/rk886ex/early_init.c index 8f6cedd..76471eb 100644 --- a/src/mainboard/roda/rk886ex/early_init.c +++ b/src/mainboard/roda/rk886ex/early_init.c @@ -17,7 +17,7 @@ { int lpt_en = 0; - if (get_int_option("lpt", 0)) + if (get_uint_option("lpt", 0)) lpt_en = LPT_LPC_EN; /* enable LPT */ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007); diff --git a/src/mainboard/siemens/chili/romstage.c b/src/mainboard/siemens/chili/romstage.c index 330d8afd..ddcc2cc 100644 --- a/src/mainboard/siemens/chili/romstage.c +++ b/src/mainboard/siemens/chili/romstage.c @@ -24,9 +24,9 @@ memupd->FspmConfig.EccSupport = 1; memupd->FspmConfig.UserBd = BOARD_TYPE_MOBILE; - const uint8_t vtd = get_int_option("vtd", 1); + const uint8_t vtd = get_uint_option("vtd", 1); memupd->FspmTestConfig.VtdDisable = !vtd; - const uint8_t ht = get_int_option("hyper_threading", memupd->FspmConfig.HyperThreading); + const uint8_t ht = get_uint_option("hyper_threading", memupd->FspmConfig.HyperThreading); memupd->FspmConfig.HyperThreading = ht; variant_romstage_params(memupd); diff --git a/src/mainboard/siemens/chili/variants/chili/romstage.c b/src/mainboard/siemens/chili/variants/chili/romstage.c index fadd2b7..d88301e 100644 --- a/src/mainboard/siemens/chili/variants/chili/romstage.c +++ b/src/mainboard/siemens/chili/variants/chili/romstage.c @@ -7,7 +7,7 @@ void variant_romstage_params(FSPM_UPD *const mupd) { - const uint8_t eth_enable = get_int_option("ethernet1", 1); + const uint8_t eth_enable = get_uint_option("ethernet1", 1); if (!eth_enable) { printk(BIOS_DEBUG, "Disabling ethernet1.\n"); diff --git a/src/mainboard/supermicro/x10slm-f/mainboard.c b/src/mainboard/supermicro/x10slm-f/mainboard.c index b584e9b..98548e3 100644 --- a/src/mainboard/supermicro/x10slm-f/mainboard.c +++ b/src/mainboard/supermicro/x10slm-f/mainboard.c @@ -30,7 +30,7 @@ static void mainboard_enable(struct device *dev) { - if (get_int_option("hide_ast2400", false)) + if (get_uint_option("hide_ast2400", false)) hide_ast2400(); } diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c index f7bdb28..7b0b1e5 100644 --- a/src/northbridge/intel/gm45/igd.c +++ b/src/northbridge/intel/gm45/igd.c @@ -116,7 +116,7 @@ sysinfo->ggc = 0x0002; else { /* 4 for 32MB, default if not set in CMOS */ - u8 gfxsize = get_int_option("gfx_uma_size", 4); + u8 gfxsize = get_uint_option("gfx_uma_size", 4); /* Graphics Stolen Memory: 2MB GTT (0x0300) when VT-d disabled, 2MB GTT + 2MB shadow GTT (0x0b00) else. */ diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index b9c9441..d730b2e 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -149,7 +149,7 @@ pci_write_config32(HOST_BRIDGE, X60BAR, DEFAULT_X60BAR | 1); /* vram size from CMOS option */ - gfxsize = get_int_option("gfx_uma_size", 2); /* 2 for 8MB */ + gfxsize = get_uint_option("gfx_uma_size", 2); /* 2 for 8MB */ /* make sure no invalid setting is used */ if (gfxsize > 6) gfxsize = 2; diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 8aa722c..0d014fb 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -710,7 +710,7 @@ if (!CONFIG(NO_GFX_INIT)) pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); - pci_write_config8(dev, 0xf4, get_int_option("tft_brightness", 0xff)); + pci_write_config8(dev, 0xf4, get_uint_option("tft_brightness", 0xff)); } static void gma_generate_ssdt(const struct device *device) diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index d8e72b9..72c3028 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -3102,7 +3102,7 @@ mchbar_write16(0x1170, 0xb880); mchbar_clrsetbits8(0x1210, ~0, 0x84); - gfxsize = get_int_option("gfx_uma_size", 0); /* 0 for 32MB */ + gfxsize = get_uint_option("gfx_uma_size", 0); /* 0 for 32MB */ ggc = 0xb00 | ((gfxsize + 5) << 4); diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index df7dcb3..ae27d85 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -25,7 +25,7 @@ pci_write_config8(HOST_BRIDGE, DEVEN, BOARD_DEVEN); /* Fetch VRAM size from CMOS option */ - reg8 = get_int_option("gfx_uma_size", 0); /* 0 for 8MB */ + reg8 = get_uint_option("gfx_uma_size", 0); /* 0 for 8MB */ /* Ensure the setting is valid */ if (reg8 > 6) diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 51b8512..7acc5af 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -87,7 +87,7 @@ printk(BIOS_DEBUG, "Initializing Graphics...\n"); /* Fall back to 32 MiB for IGD memory by setting GGC[7:3] = 1 */ - gfxsize = get_int_option("gfx_uma_size", 0); + gfxsize = get_uint_option("gfx_uma_size", 0); reg16 = pci_read_config16(HOST_BRIDGE, GGC); reg16 &= ~0x00f8; diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index 1de9e28..410653d 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -39,7 +39,7 @@ pci_write_config32(HOST_BRIDGE, D0F0_DEVEN, BOARD_DEVEN); /* Set preallocated IGD size from CMOS, or default to 64 MiB */ - u8 gfxsize = get_int_option("gfx_uma_size", 6); + u8 gfxsize = get_uint_option("gfx_uma_size", 6); if (gfxsize > 12) gfxsize = 6; /* Need at least 4M for cbmem_top alignment */ diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index 9981624..f7835db 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -132,7 +132,7 @@ * * If the option is not existent (Laptops), use Kconfig setting. */ - const int pwr_on = get_int_option("power_on_after_fail", + const unsigned int pwr_on = get_uint_option("power_on_after_fail", CONFIG_MAINBOARD_POWER_FAILURE_STATE); reg16 = pci_read_config16(dev, GEN_PMCON_3); diff --git a/src/soc/intel/broadwell/pch/smihandler.c b/src/soc/intel/broadwell/pch/smihandler.c index 262ed47..a8e2067 100644 --- a/src/soc/intel/broadwell/pch/smihandler.c +++ b/src/soc/intel/broadwell/pch/smihandler.c @@ -131,7 +131,7 @@ u8 tmp70, tmp72; tmp70 = inb(0x70); tmp72 = inb(0x72); - const int s5pwr = get_int_option("power_on_after_fail", + const unsigned int s5pwr = get_uint_option("power_on_after_fail", CONFIG_MAINBOARD_POWER_FAILURE_STATE); outb(tmp70, 0x70); outb(tmp72, 0x72); diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 935dd0c..aa5b362 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -583,7 +583,7 @@ { bool on; - const int state = get_int_option("power_on_after_fail", + const unsigned int state = get_uint_option("power_on_after_fail", CONFIG_MAINBOARD_POWER_FAILURE_STATE); switch (state) { diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 43d0e04..c6b42ea 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -169,7 +169,7 @@ * * If the option is not existent (Laptops), use Kconfig setting. */ - const int pwr_on = get_int_option("power_on_after_fail", + const unsigned int pwr_on = get_uint_option("power_on_after_fail", CONFIG_MAINBOARD_POWER_FAILURE_STATE); reg16 = pci_read_config16(dev, GEN_PMCON_3); @@ -211,7 +211,7 @@ outb(reg8, 0x61); reg8 = inb(0x70); - const int nmi_option = get_int_option("nmi", NMI_OFF); + const unsigned int nmi_option = get_uint_option("nmi", NMI_OFF); if (nmi_option) { printk(BIOS_INFO, "NMI sources enabled.\n"); reg8 &= ~(1 << 7); /* Set NMI. */ diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 7ffef42..0148905 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -184,8 +184,8 @@ /* Do initial setup and determine the BIOS path */ printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_get_bios_path_string(path)); - u8 me_state = get_int_option("me_state", 0); - u8 me_state_prev = get_int_option("me_state_prev", 0); + u8 me_state = get_uint_option("me_state", 0); + u8 me_state_prev = get_uint_option("me_state_prev", 0); printk(BIOS_DEBUG, "ME: me_state=%u, me_state_prev=%u\n", me_state, me_state_prev); @@ -268,7 +268,7 @@ set the 'changed' bit here. */ if (me_state != CMOS_ME_STATE(me_state_prev) || need_reset) { u8 new_state = me_state | CMOS_ME_STATE_CHANGED; - set_int_option("me_state_prev", new_state); + set_uint_option("me_state_prev", new_state); } if (need_reset) { diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 3c5fcd1..6ad4cc2 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -182,8 +182,8 @@ /* Do initial setup and determine the BIOS path */ printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_get_bios_path_string(path)); - u8 me_state = get_int_option("me_state", 0); - u8 me_state_prev = get_int_option("me_state_prev", 0); + u8 me_state = get_uint_option("me_state", 0); + u8 me_state_prev = get_uint_option("me_state_prev", 0); printk(BIOS_DEBUG, "ME: me_state=%u, me_state_prev=%u\n", me_state, me_state_prev); @@ -267,7 +267,7 @@ set the 'changed' bit here. */ if (me_state != CMOS_ME_STATE(me_state_prev) || need_reset) { u8 new_state = me_state | CMOS_ME_STATE_CHANGED; - set_int_option("me_state_prev", new_state); + set_uint_option("me_state_prev", new_state); } if (need_reset) { diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 43ef9be..c9bc14c 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -35,7 +35,7 @@ /* Assign fixed resources for IDE legacy mode */ - u8 sata_mode = get_int_option("sata_mode", 0); + u8 sata_mode = get_uint_option("sata_mode", 0); if (sata_mode != 2) return; @@ -71,7 +71,7 @@ static void sata_set_resources(struct device *dev) { /* work around bug in pci_dev_set_resources(), it bails out on FIXED */ - u8 sata_mode = get_int_option("sata_mode", 0); + u8 sata_mode = get_uint_option("sata_mode", 0); if (sata_mode == 2) { unsigned int i; for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_3; i += 4) { @@ -99,7 +99,7 @@ } /* Default to AHCI */ - u8 sata_mode = get_int_option("sata_mode", 0); + u8 sata_mode = get_uint_option("sata_mode", 0); /* SATA configuration */ @@ -230,7 +230,7 @@ if (!config) return; - u8 sata_mode = get_int_option("sata_mode", 0); + u8 sata_mode = get_uint_option("sata_mode", 0); /* * Set SATA controller mode early so the resource allocator can diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index db034fc..798f2f1 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -99,7 +99,7 @@ u8 tmp70, tmp72; tmp70 = inb(0x70); tmp72 = inb(0x72); - const int s5pwr = get_int_option("power_on_after_fail", + const unsigned int s5pwr = get_uint_option("power_on_after_fail", CONFIG_MAINBOARD_POWER_FAILURE_STATE); outb(tmp70, 0x70); outb(tmp72, 0x72); diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 098af83..f6c04a5 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -94,7 +94,7 @@ * * If the option is not existent (Laptops), use MAINBOARD_POWER_ON. */ - const int pwr_on = get_int_option("power_on_after_fail", MAINBOARD_POWER_ON); + const unsigned int pwr_on = get_uint_option("power_on_after_fail", MAINBOARD_POWER_ON); reg8 = pci_read_config8(dev, GEN_PMCON_3); reg8 &= 0xfe; @@ -129,7 +129,7 @@ outb(reg8, 0x61); reg8 = inb(0x70); - const int nmi_option = get_int_option("nmi", NMI_OFF); + const unsigned int nmi_option = get_uint_option("nmi", NMI_OFF); if (nmi_option) { printk(BIOS_INFO, "NMI sources enabled.\n"); reg8 &= ~(1 << 7); /* Set NMI. */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 9c3b0e9..9eabf02 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -157,7 +157,7 @@ * * If the option is not existent (Laptops), use MAINBOARD_POWER_ON. */ - const int pwr_on = get_int_option("power_on_after_fail", MAINBOARD_POWER_ON); + const unsigned int pwr_on = get_uint_option("power_on_after_fail", MAINBOARD_POWER_ON); reg8 = pci_read_config8(dev, GEN_PMCON_3); reg8 &= 0xfe; @@ -193,7 +193,7 @@ outb(reg8, 0x61); reg8 = inb(0x70); - const int nmi_option = get_int_option("nmi", NMI_OFF); + const unsigned int nmi_option = get_uint_option("nmi", NMI_OFF); if (nmi_option) { printk(BIOS_INFO, "NMI sources enabled.\n"); reg8 &= ~(1 << 7); /* Set NMI. */ diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 32d4efc..866ede9 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -162,7 +162,7 @@ * * If the option is not existent (Laptops), use MAINBOARD_POWER_ON. */ - const int pwr_on = get_int_option("power_on_after_fail", MAINBOARD_POWER_ON); + const unsigned int pwr_on = get_uint_option("power_on_after_fail", MAINBOARD_POWER_ON); reg8 = pci_read_config8(dev, D31F0_GEN_PMCON_3); reg8 &= 0xfe; @@ -198,7 +198,7 @@ outb(reg8, 0x61); reg8 = inb(0x74); /* Read from 0x74 as 0x70 is write only. */ - const int nmi_option = get_int_option("nmi", NMI_OFF); + const unsigned int nmi_option = get_uint_option("nmi", NMI_OFF); if (nmi_option) { printk(BIOS_INFO, "NMI sources enabled.\n"); reg8 &= ~(1 << 7); /* Set NMI. */ diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index d2bee88..df74123 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -152,7 +152,7 @@ } /* Default to AHCI */ - u8 sata_mode = get_int_option("sata_mode", 0); + u8 sata_mode = get_uint_option("sata_mode", 0); /* * TODO: In contrast to ICH7 and PCH code we don't set @@ -227,7 +227,7 @@ if (!config) return; - u8 sata_mode = get_int_option("sata_mode", 0); + u8 sata_mode = get_uint_option("sata_mode", 0); /* * Set SATA controller mode early so the resource allocator can diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 55b4746..69990ab 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -164,7 +164,7 @@ * * If the option is not existent (Laptops), use MAINBOARD_POWER_ON. */ - const int pwr_on = get_int_option("power_on_after_fail", MAINBOARD_POWER_ON); + const unsigned int pwr_on = get_uint_option("power_on_after_fail", MAINBOARD_POWER_ON); reg8 = pci_read_config8(dev, D31F0_GEN_PMCON_3); reg8 &= 0xfe; @@ -200,7 +200,7 @@ outb(reg8, 0x61); reg8 = inb(0x74); /* Read from 0x74 as 0x70 is write only. */ - const int nmi_option = get_int_option("nmi", NMI_OFF); + const unsigned int nmi_option = get_uint_option("nmi", NMI_OFF); if (nmi_option) { printk(BIOS_INFO, "NMI sources enabled.\n"); reg8 &= ~(1 << 7); /* Set NMI. */ diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c index 4d83388..c21c115 100644 --- a/src/southbridge/intel/i82801jx/sata.c +++ b/src/southbridge/intel/i82801jx/sata.c @@ -139,7 +139,7 @@ } /* Default to AHCI */ - u8 sata_mode = get_int_option("sata_mode", 0); + u8 sata_mode = get_uint_option("sata_mode", 0); /* * TODO: In contrast to ICH7 and PCH code we don't set @@ -205,7 +205,7 @@ return; /* Default to AHCI */ - u8 sata_mode = get_int_option("sata_mode", 0); + u8 sata_mode = get_uint_option("sata_mode", 0); /* * Set SATA controller mode early so the resource allocator can diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 6fe44c6..6092347 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -162,7 +162,7 @@ * * If the option is not existent (Laptops), use Kconfig setting. */ - const int pwr_on = get_int_option("power_on_after_fail", + const unsigned int pwr_on = get_uint_option("power_on_after_fail", CONFIG_MAINBOARD_POWER_FAILURE_STATE); reg16 = pci_read_config16(dev, GEN_PMCON_3); @@ -204,7 +204,7 @@ outb(reg8, 0x61); reg8 = inb(0x70); - const int nmi_option = get_int_option("nmi", NMI_OFF); + const unsigned int nmi_option = get_uint_option("nmi", NMI_OFF); if (nmi_option) { printk(BIOS_INFO, "NMI sources enabled.\n"); reg8 &= ~(1 << 7); /* Set NMI. */ diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index dc3f1ff..171057e 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -42,7 +42,7 @@ } /* Default to AHCI */ - u8 sata_mode = get_int_option("sata_mode", 0); + u8 sata_mode = get_uint_option("sata_mode", 0); /* SATA configuration */ @@ -174,7 +174,7 @@ if (!config) return; - u8 sata_mode = get_int_option("sata_mode", 0); + u8 sata_mode = get_uint_option("sata_mode", 0); /* * Set SATA controller mode early so the resource allocator can diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 8d9b451..fc287b0 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -193,7 +193,7 @@ * * If the option is not existent (Laptops), use Kconfig setting. */ - const int pwr_on = get_int_option("power_on_after_fail", + const unsigned int pwr_on = get_uint_option("power_on_after_fail", CONFIG_MAINBOARD_POWER_FAILURE_STATE); reg16 = pci_read_config16(dev, GEN_PMCON_3); @@ -235,7 +235,7 @@ outb(reg8, 0x61); reg8 = inb(0x70); - const int nmi_option = get_int_option("nmi", NMI_OFF); + const unsigned int nmi_option = get_uint_option("nmi", NMI_OFF); if (nmi_option) { printk(BIOS_INFO, "NMI sources enabled.\n"); reg8 &= ~(1 << 7); /* Set NMI. */ diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 2c89a95..769cacb 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -82,7 +82,7 @@ u8 tmp70, tmp72; tmp70 = inb(0x70); tmp72 = inb(0x72); - const int s5pwr = get_int_option("power_on_after_fail", + const unsigned int s5pwr = get_uint_option("power_on_after_fail", CONFIG_MAINBOARD_POWER_FAILURE_STATE); outb(tmp70, 0x70); outb(tmp72, 0x72); diff --git a/src/superio/ite/it8720f/superio.c b/src/superio/ite/it8720f/superio.c index 0ecbddc..c63fa9a 100644 --- a/src/superio/ite/it8720f/superio.c +++ b/src/superio/ite/it8720f/superio.c @@ -17,7 +17,7 @@ static void power_control_init(struct device *dev) { - int power_on = get_int_option("power_on_after_fail", MAINBOARD_POWER_OFF); + unsigned int power_on = get_uint_option("power_on_after_fail", MAINBOARD_POWER_OFF); u8 value; pnp_enter_conf_mode(dev); diff --git a/src/superio/nuvoton/nct5572d/superio.c b/src/superio/nuvoton/nct5572d/superio.c index b26954d..b0e00fb 100644 --- a/src/superio/nuvoton/nct5572d/superio.c +++ b/src/superio/nuvoton/nct5572d/superio.c @@ -47,7 +47,7 @@ break; case NCT5572D_ACPI: /* Set power state after power fail */ - power_status = get_int_option("power_on_after_fail", + power_status = get_uint_option("power_on_after_fail", CONFIG_MAINBOARD_POWER_FAILURE_STATE); pnp_enter_conf_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/nuvoton/npcd378/superio.c b/src/superio/nuvoton/npcd378/superio.c index 3645832..9889980 100644 --- a/src/superio/nuvoton/npcd378/superio.c +++ b/src/superio/nuvoton/npcd378/superio.c @@ -68,7 +68,7 @@ npcd378_hwm_write_start(res->base); - unsigned int fan_lvl = get_int_option("psu_fan_lvl", 3); + unsigned int fan_lvl = get_uint_option("psu_fan_lvl", 3); if (fan_lvl > 7) fan_lvl = 3; diff --git a/src/superio/winbond/w83627ehg/superio.c b/src/superio/winbond/w83627ehg/superio.c index 2f0a3a4..1e36048 100644 --- a/src/superio/winbond/w83627ehg/superio.c +++ b/src/superio/winbond/w83627ehg/superio.c @@ -23,7 +23,7 @@ static void init_acpi(struct device *dev) { u8 value; - int power_on = get_int_option("power_on_after_fail", 1); + unsigned int power_on = get_uint_option("power_on_after_fail", 1); pnp_enter_conf_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/winbond/w83627hf/superio.c b/src/superio/winbond/w83627hf/superio.c index 5af2d37..de2a0c6 100644 --- a/src/superio/winbond/w83627hf/superio.c +++ b/src/superio/winbond/w83627hf/superio.c @@ -23,7 +23,7 @@ static void init_acpi(struct device *dev) { u8 value; - int power_on = get_int_option("power_on_after_fail", 1); + unsigned int power_on = get_uint_option("power_on_after_fail", 1); pnp_enter_conf_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/winbond/w83667hg-a/superio.c b/src/superio/winbond/w83667hg-a/superio.c index 5f96832..0a06898 100644 --- a/src/superio/winbond/w83667hg-a/superio.c +++ b/src/superio/winbond/w83667hg-a/superio.c @@ -47,7 +47,7 @@ break; case W83667HG_A_ACPI: /* Set power state after power fail */ - power_status = get_int_option("power_on_after_fail", + power_status = get_uint_option("power_on_after_fail", CONFIG_MAINBOARD_POWER_FAILURE_STATE); pnp_enter_conf_mode(dev); pnp_set_logical_device(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/52672 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3 Gerrit-Change-Number: 52672 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: include/console: Align ramstage Boot State Machine postcodes
by Patrick Georgi (Code Review) 06 May '21

06 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52893 ) Change subject: include/console: Align ramstage Boot State Machine postcodes ...................................................................... include/console: Align ramstage Boot State Machine postcodes This patch ensures all boot state machine postcodes are in right order. Move POST_ENTRY_RAMSTAGE macro definition after POST_BS_PAYLOAD_BOOT. Change-Id: I9e03159fdf07a73f5f8eec1bbf32fcb47dd4af84 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52893 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/include/console/post_codes.h 1 file changed, 8 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index ee74dcb..677cd36 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -182,14 +182,6 @@ #define POST_PRE_HARDWAREMAIN 0x79 /** - * \brief Entry into coreboot in RAM stage main() - * - * This is the first call in hardwaremain.c. If this code is POSTed, then - * ramstage has successfully loaded and started executing. - */ -#define POST_ENTRY_RAMSTAGE 0x80 - -/** * \brief Load Payload * * Boot State Machine: bs_payload_load() @@ -204,6 +196,14 @@ #define POST_BS_PAYLOAD_BOOT 0x7b /** + * \brief Entry into coreboot in RAM stage main() + * + * This is the first call in hardwaremain.c. If this code is POSTed, then + * ramstage has successfully loaded and started executing. + */ +#define POST_ENTRY_RAMSTAGE 0x80 + +/** * \brief Before calling FSP Notify before End of Firmware * * Going to call into FSP binary for Notify phase -- To view, visit https://review.coreboot.org/c/coreboot/+/52893 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e03159fdf07a73f5f8eec1bbf32fcb47dd4af84 Gerrit-Change-Number: 52893 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: nb/amd/{agesa,pi}: Avoid overflows during DRAM calculation
by Patrick Georgi (Code Review) 06 May '21

06 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52922 ) Change subject: nb/amd/{agesa,pi}: Avoid overflows during DRAM calculation ...................................................................... nb/amd/{agesa,pi}: Avoid overflows during DRAM calculation Do not use get_dram_base_mask to calculate system DRAM limits. Shift operation around values operating on base and mask were causing overflows and thus incorrect system DRAM limit. Another function returning base and limit in KiB has been developed to avoid data loss. Keep DRAM high base and limit in calculations only for Trinity where the physical CPU address bits is 48. Although it is almost impossible to have a non-zero value there, the platform would have to support nearly 256GB of RAM. TEST=boot PC Engines apu1 2GB, apu2 4GB and apu3 2GB and boot Debian with Linux 4.14 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I3b5c1df96c308ff50c8de104e213219a98f25e10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52922 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/amd/agesa/family14/northbridge.c M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c 4 files changed, 142 insertions(+), 155 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 020c9c6..4aed96b 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -26,29 +26,6 @@ static struct device *__f4_dev[FX_DEVS]; static unsigned int fx_devs = 0; -struct dram_base_mask_t { - u32 base; //[47:27] at [28:8] - u32 mask; //[47:27] at [28:8] and enable at bit 0 -}; - -static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) -{ - struct device *dev; - struct dram_base_mask_t d; - dev = __f1_dev[0]; - - u32 temp; - temp = pci_read_config32(dev, 0x44); //[39:24] at [31:16] - d.mask = (temp & 0xffff0000); // mask out DramMask [26:24] too - - temp = pci_read_config32(dev, 0x40); //[35:24] at [27:16] - d.mask |= (temp & 1); // read enable bit - - d.base = (temp & 0x0fff0000); // mask out DramBase [26:24) too - - return d; -} - static u32 get_io_addr_index(u32 nodeid, u32 linkn) { return 0; @@ -127,6 +104,33 @@ } } +static int get_dram_base_limit(u32 nodeid, resource_t *basek, resource_t *limitk) +{ + u32 temp; + + if (fx_devs == 0) + get_fx_devs(); + + + temp = pci_read_config32(__f1_dev[nodeid], 0x40 + (nodeid << 3)); //[39:24] at [31:16] + if (!(temp & 1)) + return 0; // this memory range is not enabled + /* + * BKDG: {DramBase[35:24], 00_0000h} <= address[35:0] so shift left by 8 bits + * for physical address and the convert to KiB by shifting 10 bits left + */ + *basek = ((temp & 0x0fff0000)) >> (10 - 8); + /* + * BKDG address[35:0] <= {DramLimit[35:24], FF_FFFFh} converted as above but + * ORed with 0xffff to get real limit before shifting. + */ + temp = pci_read_config32(__f1_dev[nodeid], 0x44 + (nodeid << 3)); //[39:24] at [31:16] + *limitk = ((temp & 0x0fff0000) | 0xffff) >> (10 - 8); + *limitk += 1; // round up last byte + + return 1; +} + static u32 amdfam14_nodeid(struct device *dev) { return (dev->path.pci.devfn >> 3) - DEV_CDB; @@ -305,10 +309,10 @@ mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; mem_hole.node_id = -1; - struct dram_base_mask_t d; + resource_t basek, limitk; u32 hole; - d = get_dram_base_mask(0); - if (d.mask & 1) { + + if (get_dram_base_limit(0, &basek, &limitk)) { hole = pci_read_config32(__f1_dev[0], 0xf0); if (hole & 1) { // we find the hole mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; @@ -542,27 +546,13 @@ #endif idx = 0x10; - - struct dram_base_mask_t d; resource_t basek, limitk, sizek; // 4 1T - d = get_dram_base_mask(0); + if (get_dram_base_limit(0, &basek, &limitk)) { + sizek = limitk - basek; - if (d.mask & 1) { - basek = ((resource_t) ((u64) d.base)) << 8; - limitk = (resource_t) (((u64) d.mask << 8) | 0xFFFFFF); - printk(BIOS_DEBUG, - "adsr: (before) basek = %llx, limitk = %llx.\n", basek, - limitk); - - /* Convert these values to multiples of 1K for ease of math. */ - basek >>= 10; - limitk >>= 10; - sizek = limitk - basek + 1; - - printk(BIOS_DEBUG, - "adsr: (after) basek = %llx, limitk = %llx, sizek = %llx.\n", - basek, limitk, sizek); + printk(BIOS_DEBUG, "adsr: basek = %llx, limitk = %llx, sizek = %llx.\n", + basek, limitk, sizek); /* see if we need a hole from 0xa0000 to 0xbffff */ if ((basek < 640) && (sizek > 768)) { diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index e345b50..fe56736 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -24,11 +24,6 @@ #define MAX_NODE_NUMS MAX_NODES -typedef struct dram_base_mask { - u32 base; //[47:27] at [28:8] - u32 mask; //[47:27] at [28:8] and enable at bit 0 -} dram_base_mask_t; - static unsigned int node_nums; static unsigned int sblink; static struct device *__f0_dev[MAX_NODE_NUMS]; @@ -37,24 +32,6 @@ static struct device *__f4_dev[MAX_NODE_NUMS]; static unsigned int fx_devs = 0; -static dram_base_mask_t get_dram_base_mask(u32 nodeid) -{ - struct device *dev; - dram_base_mask_t d; - dev = __f1_dev[0]; - u32 temp; - temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] - d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too - temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.mask |= temp << 21; - temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] - d.mask |= (temp & 1); // enable bit - d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too - temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.base |= temp << 21; - return d; -} - static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { @@ -125,6 +102,39 @@ } } +static int get_dram_base_limit(u32 nodeid, resource_t *basek, resource_t *limitk) +{ + u32 temp; + + if (fx_devs == 0) + get_fx_devs(); + + + temp = pci_read_config32(__f1_dev[nodeid], 0x40 + (nodeid << 3)); //[39:24] at [31:16] + if (!(temp & 1)) + return 0; // this memory range is not enabled + /* + * BKDG: {DramBase[47:24], 00_0000h} <= address[47:0] so shift left by 8 bits + * for physical address and the convert to KiB by shifting 10 bits left + */ + *basek = ((temp & 0xffff0000)) >> (10 - 8); + /* Now high bits [47:40] */ + temp = pci_read_config32(__f1_dev[nodeid], 0x140 + (nodeid << 3)); //[47:40] at [7:0] + *basek = *basek | ((resource_t)temp << (40 - 10)); + /* + * BKDG address[39:0] <= {DramLimit[47:24], FF_FFFFh} converted as above but + * ORed with 0xffff to get real limit before shifting. + */ + temp = pci_read_config32(__f1_dev[nodeid], 0x44 + (nodeid << 3)); //[39:24] at [31:16] + *limitk = ((temp & 0xffff0000) | 0xffff) >> (10 - 8); + /* Now high bits [47:40] */ + temp = pci_read_config32(__f1_dev[nodeid], 0x144 + (nodeid << 3)); //[47:40] at [7:0] + *limitk = *limitk | ((resource_t)temp << (40 - 10)); + *limitk += 1; // round up last byte + + return 1; +} + static u32 amdfam15_nodeid(struct device *dev) { return (dev->path.pci.devfn >> 3) - DEV_CDB; @@ -616,10 +626,10 @@ mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; mem_hole.node_id = -1; for (i = 0; i < node_nums; i++) { - dram_base_mask_t d; + resource_t basek, limitk; u32 hole; - d = get_dram_base_mask(i); - if (!(d.mask & 1)) continue; // no memory on this node + if (!get_dram_base_limit(i, &basek, &limitk)) + continue; // no memory on this node hole = pci_read_config32(__f1_dev[i], 0xf0); if (hole & 1) { // we find the hole mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; @@ -634,18 +644,15 @@ if (mem_hole.node_id == -1) { resource_t limitk_pri = 0; for (i = 0; i < node_nums; i++) { - dram_base_mask_t d; resource_t base_k, limit_k; - d = get_dram_base_mask(i); - if (!(d.base & 1)) continue; - base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; + if (!get_dram_base_limit(i, &base_k, &limit_k)) + continue; // no memory on this node if (base_k > 4 *1024 * 1024) break; // don't need to go to check if (limitk_pri != base_k) { // we find the hole mem_hole.hole_startk = (unsigned int)limitk_pri; // must beblow 4G mem_hole.node_id = i; break; //only one hole } - limit_k = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; limitk_pri = limit_k; } } @@ -698,14 +705,10 @@ idx = 0x10; for (i = 0; i < node_nums; i++) { - dram_base_mask_t d; resource_t basek, limitk, sizek; // 4 1T - d = get_dram_base_mask(i); - - if (!(d.mask & 1)) continue; - basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here - limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; + if (!get_dram_base_limit(i, &basek, &limitk)) + continue; // no memory on this node sizek = limitk - basek; diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index b600bc9..21b4d69 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -24,11 +24,6 @@ #define MAX_NODE_NUMS MAX_NODES -typedef struct dram_base_mask { - u32 base; //[47:27] at [28:8] - u32 mask; //[47:27] at [28:8] and enable at bit 0 -} dram_base_mask_t; - static unsigned int node_nums; static unsigned int sblink; static struct device *__f0_dev[MAX_NODE_NUMS]; @@ -37,24 +32,6 @@ static struct device *__f4_dev[MAX_NODE_NUMS]; static unsigned int fx_devs = 0; -static dram_base_mask_t get_dram_base_mask(u32 nodeid) -{ - struct device *dev; - dram_base_mask_t d; - dev = __f1_dev[0]; - u32 temp; - temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] - d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too - temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.mask |= temp << 21; - temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] - d.mask |= (temp & 1); // enable bit - d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too - temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.base |= temp << 21; - return d; -} - static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { @@ -125,6 +102,33 @@ } } +static int get_dram_base_limit(u32 nodeid, resource_t *basek, resource_t *limitk) +{ + u32 temp; + + if (fx_devs == 0) + get_fx_devs(); + + + temp = pci_read_config32(__f1_dev[nodeid], 0x40 + (nodeid << 3)); //[39:24] at [31:16] + if (!(temp & 1)) + return 0; // this memory range is not enabled + /* + * BKDG: {DramBase[39:24], 00_0000h} <= address[39:0] so shift left by 8 bits + * for physical address and the convert to KiB by shifting 10 bits left + */ + *basek = ((temp & 0xffff0000)) >> (10 - 8); + /* + * BKDG address[39:0] <= {DramLimit[39:24], FF_FFFFh} converted as above but + * ORed with 0xffff to get real limit before shifting. + */ + temp = pci_read_config32(__f1_dev[nodeid], 0x44 + (nodeid << 3)); //[39:24] at [31:16] + *limitk = ((temp & 0xffff0000) | 0xffff) >> (10 - 8); + *limitk += 1; // round up last byte + + return 1; +} + static u32 amdfam16_nodeid(struct device *dev) { return (dev->path.pci.devfn >> 3) - DEV_CDB; @@ -634,10 +638,10 @@ mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; mem_hole.node_id = -1; for (i = 0; i < node_nums; i++) { - dram_base_mask_t d; + resource_t basek, limitk; u32 hole; - d = get_dram_base_mask(i); - if (!(d.mask & 1)) continue; // no memory on this node + if (!get_dram_base_limit(i, &basek, &limitk)) + continue; // no memory on this node hole = pci_read_config32(__f1_dev[i], 0xf0); if (hole & 2) { // we find the hole mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; @@ -652,18 +656,15 @@ if (mem_hole.node_id == -1) { resource_t limitk_pri = 0; for (i = 0; i < node_nums; i++) { - dram_base_mask_t d; resource_t base_k, limit_k; - d = get_dram_base_mask(i); - if (!(d.base & 1)) continue; - base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; + if (!get_dram_base_limit(i, &base_k, &limit_k)) + continue; // no memory on this node if (base_k > 4 *1024 * 1024) break; // don't need to go to check if (limitk_pri != base_k) { // we find the hole mem_hole.hole_startk = (unsigned int)limitk_pri; // must beblow 4G mem_hole.node_id = i; break; //only one hole } - limit_k = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; limitk_pri = limit_k; } } @@ -716,14 +717,10 @@ idx = 0x10; for (i = 0; i < node_nums; i++) { - dram_base_mask_t d; resource_t basek, limitk, sizek; // 4 1T - d = get_dram_base_mask(i); - - if (!(d.mask & 1)) continue; - basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here - limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; + if (!get_dram_base_limit(i, &basek, &limitk)) + continue; // no memory on this node sizek = limitk - basek; diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 2019fae..e1ff95a 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -29,11 +29,6 @@ #define PCIE_CAP_AER BIT(5) #define PCIE_CAP_ACS BIT(6) -typedef struct dram_base_mask { - u32 base; //[47:27] at [28:8] - u32 mask; //[47:27] at [28:8] and enable at bit 0 -} dram_base_mask_t; - static unsigned int node_nums; static unsigned int sblink; static struct device *__f0_dev[MAX_NODE_NUMS]; @@ -42,24 +37,6 @@ static struct device *__f4_dev[MAX_NODE_NUMS]; static unsigned int fx_devs = 0; -static dram_base_mask_t get_dram_base_mask(u32 nodeid) -{ - struct device *dev; - dram_base_mask_t d; - dev = __f1_dev[0]; - u32 temp; - temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] - d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too - temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.mask |= temp<<21; - temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] - d.mask |= (temp & 1); // enable bit - d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too - temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.base |= temp<<21; - return d; -} - static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { @@ -130,6 +107,33 @@ } } +static int get_dram_base_limit(u32 nodeid, resource_t *basek, resource_t *limitk) +{ + u32 temp; + + if (fx_devs == 0) + get_fx_devs(); + + + temp = pci_read_config32(__f1_dev[nodeid], 0x40 + (nodeid << 3)); //[39:24] at [31:16] + if (!(temp & 1)) + return 0; // this memory range is not enabled + /* + * BKDG: {DramBase[39:24], 00_0000h} <= address[39:0] so shift left by 8 bits + * for physical address and the convert to KiB by shifting 10 bits left + */ + *basek = ((temp & 0xffff0000)) >> (10 - 8); + /* + * BKDG address[39:0] <= {DramLimit[39:24], FF_FFFFh} converted as above but + * ORed with 0xffff to get real limit before shifting. + */ + temp = pci_read_config32(__f1_dev[nodeid], 0x44 + (nodeid << 3)); //[39:24] at [31:16] + *limitk = ((temp & 0xffff0000) | 0xffff) >> (10 - 8); + *limitk += 1; // round up last byte + + return 1; +} + static u32 amdfam16_nodeid(struct device *dev) { return (dev->path.pci.devfn >> 3) - DEV_CDB; @@ -970,10 +974,10 @@ mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; mem_hole.node_id = -1; for (i = 0; i < node_nums; i++) { - dram_base_mask_t d; + resource_t basek, limitk; u32 hole; - d = get_dram_base_mask(i); - if (!(d.mask & 1)) continue; // no memory on this node + if (!get_dram_base_limit(i, &basek, &limitk)) + continue; // no memory on this node hole = pci_read_config32(__f1_dev[i], 0xf0); if (hole & 2) { // we find the hole mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; @@ -988,18 +992,15 @@ if (mem_hole.node_id == -1) { resource_t limitk_pri = 0; for (i = 0; i < node_nums; i++) { - dram_base_mask_t d; resource_t base_k, limit_k; - d = get_dram_base_mask(i); - if (!(d.base & 1)) continue; - base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; + if (!get_dram_base_limit(i, &base_k, &limit_k)) + continue; // no memory on this node if (base_k > 4 *1024 * 1024) break; // don't need to go to check if (limitk_pri != base_k) { // we find the hole mem_hole.hole_startk = (unsigned int)limitk_pri; // must be below 4G mem_hole.node_id = i; break; //only one hole } - limit_k = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; limitk_pri = limit_k; } } @@ -1050,14 +1051,10 @@ idx = 0x10; for (i = 0; i < node_nums; i++) { - dram_base_mask_t d; resource_t basek, limitk, sizek; // 4 1T - d = get_dram_base_mask(i); - - if (!(d.mask & 1)) continue; - basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here - limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; + if (!get_dram_base_limit(i, &basek, &limitk)) + continue; // no memory on this node sizek = limitk - basek; -- To view, visit https://review.coreboot.org/c/coreboot/+/52922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b5c1df96c308ff50c8de104e213219a98f25e10 Gerrit-Change-Number: 52922 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/octopus: add audio codec into SSFC support for Bloog
by Patrick Georgi (Code Review) 06 May '21

06 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52720 ) Change subject: mb/google/octopus: add audio codec into SSFC support for Bloog ...................................................................... mb/google/octopus: add audio codec into SSFC support for Bloog BUG=b:186380809 BRANCH=octopus TEST=adjust SSFC value of CBI to select RT5682 or DA7219 then check whether device tree is updated correspondingly by disabling unselected one. Change-Id: I0975a8b64452c3f636e6c5937c6918518ec5b4e9 Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52720 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marco Chen <marcochen(a)google.com> --- M src/mainboard/google/octopus/Kconfig.name M src/mainboard/google/octopus/variants/bloog/gpio.c M src/mainboard/google/octopus/variants/bloog/overridetree.cb 3 files changed, 18 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Marco Chen: Looks good to me, approved diff --git a/src/mainboard/google/octopus/Kconfig.name b/src/mainboard/google/octopus/Kconfig.name index b384a66..942726e 100644 --- a/src/mainboard/google/octopus/Kconfig.name +++ b/src/mainboard/google/octopus/Kconfig.name @@ -61,6 +61,7 @@ select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + select NHLT_RT5682 if INCLUDE_NHLT_BLOBS config BOARD_GOOGLE_GARG bool "-> Garg" diff --git a/src/mainboard/google/octopus/variants/bloog/gpio.c b/src/mainboard/google/octopus/variants/bloog/gpio.c index d278136..cea0451 100644 --- a/src/mainboard/google/octopus/variants/bloog/gpio.c +++ b/src/mainboard/google/octopus/variants/bloog/gpio.c @@ -26,6 +26,10 @@ PAD_NC(GPIO_161, UP_20K), /* LTE_OFF_ODL -- unused */ + /* GPIO_137 -- HP_INT_ODL and would be amend by SSFC. */ + PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1, + DISPUPD), + /* EN_PP3300_TOUCHSCREEN */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), diff --git a/src/mainboard/google/octopus/variants/bloog/overridetree.cb b/src/mainboard/google/octopus/variants/bloog/overridetree.cb index 7c22ce7..b585c85 100644 --- a/src/mainboard/google/octopus/variants/bloog/overridetree.cb +++ b/src/mainboard/google/octopus/variants/bloog/overridetree.cb @@ -100,6 +100,19 @@ register "mic_amp_in_sel" = ""diff"" device i2c 1a on end end + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)" + register "probed" = "1" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end end # - I2C 5 device pci 17.2 on chip drivers/i2c/generic -- To view, visit https://review.coreboot.org/c/coreboot/+/52720 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0975a8b64452c3f636e6c5937c6918518ec5b4e9 Gerrit-Change-Number: 52720 Gerrit-PatchSet: 2 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/adlrvp_m: Disable Type-C xDCI
by Patrick Georgi (Code Review) 06 May '21

06 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52744 ) Change subject: mb/intel/adlrvp_m: Disable Type-C xDCI ...................................................................... mb/intel/adlrvp_m: Disable Type-C xDCI Disabling this pci 0d.1 device since it is not required. TEST= Boot to OS. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Change-Id: Iccdf38111e3961ba887829abfa4146a9b37df9be Reviewed-on: https://review.coreboot.org/c/coreboot/+/52744 Reviewed-by: Bora Guvendik <bora.guvendik(a)intel.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/intel/adlrvp/devicetree_m.cb 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Bora Guvendik: Looks good to me, approved Sukumar Ghorai: Looks good to me, but someone else must approve diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index ec33ee1..51d97bc 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -164,7 +164,7 @@ device pci 09.0 off end # NPK device pci 0a.0 off end # Crash-log SRAM device pci 0d.0 on end # USB xHCI - device pci 0d.1 on end # USB xDCI (OTG) + device pci 0d.1 off end # USB xDCI (OTG) device pci 0d.2 on end # TBT DMA0 device pci 0d.3 on end # TBT DMA1 device pci 0e.0 off end # VMD -- To view, visit https://review.coreboot.org/c/coreboot/+/52744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccdf38111e3961ba887829abfa4146a9b37df9be Gerrit-Change-Number: 52744 Gerrit-PatchSet: 3 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: arch/x86/walkcbfs.S: Use FMAP instead of "cbfs master header"
by Patrick Georgi (Code Review) 06 May '21

06 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52879 ) Change subject: arch/x86/walkcbfs.S: Use FMAP instead of "cbfs master header" ...................................................................... arch/x86/walkcbfs.S: Use FMAP instead of "cbfs master header" Tested on qemu/i440fx on X86_64: - Page tables are found in cbfs (finding a file works) - returns 0 when a file is not found - works when there is no cbfs file at the start of the FMAP, e.g. with the cbfs master header removed. Change-Id: Ibab657cc40cd5c09c3a73c54950b98ac45a98dbf Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52879 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/arch/x86/Makefile.inc M src/arch/x86/walkcbfs.S 2 files changed, 6 insertions(+), 25 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 0737892..a7d91a4 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -91,6 +91,7 @@ $(eval $(call early_x86_stage,bootblock,elf64-x86-64)) endif +$(call src-to-obj,bootblock,$(dir)/walkcbfs.S): $(obj)/fmap_config.h bootblock-y += walkcbfs.S endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64 diff --git a/src/arch/x86/walkcbfs.S b/src/arch/x86/walkcbfs.S index 393bcf5..4608e2c 100644 --- a/src/arch/x86/walkcbfs.S +++ b/src/arch/x86/walkcbfs.S @@ -1,13 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#define CBFS_HEADER_PTR 0xfffffffc - -#define CBFS_HEADER_MAGIC 0 -#define CBFS_HEADER_VERSION (CBFS_HEADER_MAGIC + 4) -#define CBFS_HEADER_ROMSIZE (CBFS_HEADER_VERSION + 4) -#define CBFS_HEADER_BOOTBLOCKSIZE (CBFS_HEADER_ROMSIZE + 4) -#define CBFS_HEADER_ALIGN (CBFS_HEADER_BOOTBLOCKSIZE + 4) -#define CBFS_HEADER_OFFSET (CBFS_HEADER_ALIGN + 4) +#include <fmap_config.h> /* we use this instead of CBFS_HEADER_ALIGN because the latter is retired. */ #define CBFS_ALIGNMENT 64 @@ -33,14 +26,7 @@ walkcbfs_asm: cld - mov CBFS_HEADER_PTR, %eax - mov CBFS_HEADER_ROMSIZE(%eax), %ecx - bswap %ecx - mov $0, %ebx - sub %ecx, %ebx /* ROM base address in ebx */ - mov CBFS_HEADER_OFFSET(%eax), %ecx - bswap %ecx - add %ecx, %ebx /* address where we start looking for LARCHIVEs */ + movl $FMAP_SECTION_COREBOOT_START, %ebx /* determine filename length */ mov $0, %eax @@ -96,17 +82,11 @@ mov %ecx, %ebx check_for_exit: - /* look if we should exit: did we pass into the bootblock already? */ - mov CBFS_HEADER_PTR, %ecx - mov CBFS_HEADER_BOOTBLOCKSIZE(%ecx), %ecx - bswap %ecx - not %ecx - add $1, %ecx + /* if addr <= COREBOOT_END - 1, continue */ +#define FMAP_SECTION_COREBOOT_END (FMAP_SECTION_COREBOOT_START - 1 + FMAP_SECTION_COREBOOT_SIZE) + movl $FMAP_SECTION_COREBOOT_END, %ecx cmp %ecx, %ebx - /* if bootblockstart >= addr (==we're still in the data area), - * jump back - */ jbe walker out: -- To view, visit https://review.coreboot.org/c/coreboot/+/52879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibab657cc40cd5c09c3a73c54950b98ac45a98dbf Gerrit-Change-Number: 52879 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: merged

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Change in coreboot[master]: arch/x86/walkcbfs.S: Use FMAP instead of "cbfs master header"
by Patrick Georgi (Code Review) 06 May '21

06 May '21

Attention is currently required from: Nico Huber, Patrick Rudolph, Angel Pons, Julius Werner. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52879 ) Change subject: arch/x86/walkcbfs.S: Use FMAP instead of "cbfs master header" ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibab657cc40cd5c09c3a73c54950b98ac45a98dbf Gerrit-Change-Number: 52879 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 06 May 2021 14:34:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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