coreboot-gerrit May 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: vc/amd/fsp/cezanne: Add AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID
by Matt Papageorge (Code Review) 06 May '21

06 May '21

Attention is currently required from: Raul Rangel, Karthik Ramasubramanian. Matt Papageorge has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52869 ) Change subject: vc/amd/fsp/cezanne: Add AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/52869 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib790004b88dfaf7671534f657c7735f6718114db Gerrit-Change-Number: 52869 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 06 May 2021 14:33:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: Always include walkcbfs.S
by Patrick Georgi (Code Review) 06 May '21

06 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52940 ) Change subject: arch/x86: Always include walkcbfs.S ...................................................................... arch/x86: Always include walkcbfs.S Let the linker decide if this code is needed. Change-Id: I26fb19d461db39ce554af7b948f0d10a12920299 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52940 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/arch/x86/Makefile.inc M src/cpu/qemu-x86/Makefile.inc 2 files changed, 1 insertion(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index a3c61c4..0737892 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -91,7 +91,7 @@ $(eval $(call early_x86_stage,bootblock,elf64-x86-64)) endif -bootblock-$(CONFIG_MICROCODE_UPDATE_PRE_RAM) += walkcbfs.S +bootblock-y += walkcbfs.S endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64 diff --git a/src/cpu/qemu-x86/Makefile.inc b/src/cpu/qemu-x86/Makefile.inc index 3f27e8b..fb560d6 100644 --- a/src/cpu/qemu-x86/Makefile.inc +++ b/src/cpu/qemu-x86/Makefile.inc @@ -2,7 +2,6 @@ bootblock-y += cache_as_ram_bootblock.S bootblock-y += bootblock.c -bootblock-$(CONFIG_ARCH_BOOTBLOCK_X86_64) += $(top)/src/arch/x86/walkcbfs.S romstage-y += ../intel/car/romstage.c -- To view, visit https://review.coreboot.org/c/coreboot/+/52940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26fb19d461db39ce554af7b948f0d10a12920299 Gerrit-Change-Number: 52940 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/amd/majolica: Enable S0i3 by default
by Marshall Dawson (Code Review) 06 May '21

06 May '21

Marshall Dawson has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52857 ) Change subject: mb/amd/majolica: Enable S0i3 by default ...................................................................... mb/amd/majolica: Enable S0i3 by default Set s0ix_enable to true. BUG=b:178728116 TEST=Cold boot and perform a cycle of S0i3. Signed-off-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Change-Id: I808e78f41509cb03821513b5b63cc8856c891d8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52857 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/amd/majolica/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Raul Rangel: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/amd/majolica/devicetree.cb b/src/mainboard/amd/majolica/devicetree.cb index fec764e..502ae25 100644 --- a/src/mainboard/amd/majolica/devicetree.cb +++ b/src/mainboard/amd/majolica/devicetree.cb @@ -14,6 +14,8 @@ .flash_ch_en = 0, }" + register "s0ix_enable" = "true" + device domain 0 on device ref gpp_gfx_bridge_0 on end # MXM device ref gpp_bridge_0 on end # NVMe -- To view, visit https://review.coreboot.org/c/coreboot/+/52857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I808e78f41509cb03821513b5b63cc8856c891d8c Gerrit-Change-Number: 52857 Gerrit-PatchSet: 4 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: tests: Add lib/spd_cache-test test case
by Jakub Czapiga (Code Review) 06 May '21

06 May '21

Attention is currently required from: Paul Fagerburg, Jan Dabros. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52938 ) Change subject: tests: Add lib/spd_cache-test test case ...................................................................... Patch Set 2: (2 comments) File tests/include/tests/lib/spd_cache_data.h: https://review.coreboot.org/c/coreboot/+/52938/comment/ffbd5cb9_78d499f9 PS2, Line 5: unsigned char spd_data_ddr4_1[] = { > Can you include notes about where this data came from? Maybe the set of commands to generate it from […] For the record: - modprobe: i2c-i801, eeprom and ee1004 modules - Find number of i2c with description "SMBus I801 adapter" in `i2cdetect -l` output - Dump SPD (0050 and 0052 are most common addresses): `xxd -i /sys/bus/i2c/drivers/ee1004/0-0050/eeprom` I will include a comment with description in next version :) File tests/lib/spd_cache-test.c: https://review.coreboot.org/c/coreboot/+/52938/comment/6bfa667a_6bc52018 PS2, Line 50: static void test_load_spd_cache(void **state) > Can you add comments on what you're testing in each test case? Something like "verify that when the […] Yes, this requires some explanation. I will add it in next version. -- To view, visit https://review.coreboot.org/c/coreboot/+/52938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9a1420e49e1e80d180117c931e630e54c90cd75 Gerrit-Change-Number: 52938 Gerrit-PatchSet: 2 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Comment-Date: Thu, 06 May 2021 14:26:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: tests: Add lib/spd_cache-test test case
by Paul Fagerburg (Code Review) 06 May '21

06 May '21

Attention is currently required from: Jakub Czapiga, Jan Dabros. Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52938 ) Change subject: tests: Add lib/spd_cache-test test case ...................................................................... Patch Set 2: (2 comments) File tests/include/tests/lib/spd_cache_data.h: https://review.coreboot.org/c/coreboot/+/52938/comment/03f58ece_e81f8c03 PS2, Line 5: unsigned char spd_data_ddr4_1[] = { Can you include notes about where this data came from? Maybe the set of commands to generate it from the original file? File tests/lib/spd_cache-test.c: https://review.coreboot.org/c/coreboot/+/52938/comment/ac06e900_876049ac PS2, Line 50: static void test_load_spd_cache(void **state) Can you add comments on what you're testing in each test case? Something like "verify that when the SPD cache is initially set up, it __________" -- To view, visit https://review.coreboot.org/c/coreboot/+/52938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9a1420e49e1e80d180117c931e630e54c90cd75 Gerrit-Change-Number: 52938 Gerrit-PatchSet: 2 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Comment-Date: Thu, 06 May 2021 14:11:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Create volet variant
by Paul Fagerburg (Code Review) 06 May '21

06 May '21

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, Sheng-Liang Pan, YH Lin. Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52871 ) Change subject: mb/google/volteer: Create volet variant ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: > (Auto-Generated by create_coreboot_variant.sh version 4.5.0). LGTM -- To view, visit https://review.coreboot.org/c/coreboot/+/52871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6ca9a78494e3819b0fb39c0bcc70fed95c2c589 Gerrit-Change-Number: 52871 Gerrit-PatchSet: 1 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Comment-Date: Thu, 06 May 2021 14:03:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: tests: Enable config override for tests
by Paul Fagerburg (Code Review) 06 May '21

06 May '21

Attention is currently required from: Jakub Czapiga, Julius Werner, Jan Dabros. Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52937 ) Change subject: tests: Enable config override for tests ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/52937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1aeb78362c2609fbefbfd91c0f58ec19ed258ee1 Gerrit-Change-Number: 52937 Gerrit-PatchSet: 2 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Comment-Date: Thu, 06 May 2021 14:02:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede: Create pirika variant
by Paul Fagerburg (Code Review) 06 May '21

06 May '21

Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52626 ) Change subject: mb/google/dedede: Create pirika variant ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/dedede/Kconfig.name: https://review.coreboot.org/c/coreboot/+/52626/comment/ce2be017_74d91e85 PS1, Line 138: bool "-> Pirika" > We upload the setting for CR50. see https://chromium-review.googlesource.com/c/chromiumos/platform/dev-util/+/2… -- To view, visit https://review.coreboot.org/c/coreboot/+/52626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57bf33deeadacc88800f9ce1d3d54385ba56c798 Gerrit-Change-Number: 52626 Gerrit-PatchSet: 3 Gerrit-Owner: Kirk Wang Gerrit-Reviewer: Alex1 Kao <alex1_kao(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kirk Wang <kirk_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ariel Chang <ariel_chang(a)pegatron.corp-partner.google.com> Gerrit-CC: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-CC: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Thu, 06 May 2021 13:42:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kirk Wang <kirk_wang(a)pegatron.corp-partner.google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: Added Star Labs labtop series
by Star Labs (Code Review) 06 May '21

06 May '21

Star Labs has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52973 ) Change subject: Added Star Labs labtop series ...................................................................... Added Star Labs labtop series Change-Id: Ifa79eaffbb7ac83da0124819eec5559af49cc475 --- M src/mainboard/starlabs/labtop/acpi/mainboard.asl 1 file changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/52973/1 diff --git a/src/mainboard/starlabs/labtop/acpi/mainboard.asl b/src/mainboard/starlabs/labtop/acpi/mainboard.asl index bf73244..7b955c4 100644 --- a/src/mainboard/starlabs/labtop/acpi/mainboard.asl +++ b/src/mainboard/starlabs/labtop/acpi/mainboard.asl @@ -34,7 +34,7 @@ Name (_CID, Package (0x02) { - "PRP00001", + "PRP00001", "PNP0A05" }) @@ -45,7 +45,7 @@ } } -/* +/* * ITE IT8987E Embedded Controller * * We include this here as we need to support different levels within @@ -55,5 +55,3 @@ #define EC_GPE_SCI 0x50 /* GPP_E16 */ #include <ec/starlabs/it8987/acpi/ec.asl> - - -- To view, visit https://review.coreboot.org/c/coreboot/+/52973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa79eaffbb7ac83da0124819eec5559af49cc475 Gerrit-Change-Number: 52973 Gerrit-PatchSet: 1 Gerrit-Owner: Star Labs <admin(a)starlabs.systems> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: Allow enable/disable ME via CMOS
by Star Labs (Code Review) 06 May '21

06 May '21

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52800 to look at the new patch set (#5). Change subject: soc/intel: Allow enable/disable ME via CMOS ...................................................................... soc/intel: Allow enable/disable ME via CMOS Add ME_STATE_BY_CMOS, that will disable the Intel ME. Message is only sent if me_state is set to 1. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I374db3b7c0ded71cdc18f27970252fec7220cc20 --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 71 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/52800/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/52800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I374db3b7c0ded71cdc18f27970252fec7220cc20 Gerrit-Change-Number: 52800 Gerrit-PatchSet: 5 Gerrit-Owner: Star Labs <admin(a)starlabs.systems> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit May 2021