coreboot-gerrit May 2021

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Change in coreboot[master]: security/tpm/tspi/crtm: Fix FMAP TPM PCR
by build bot (Jenkins) (Code Review) 06 May '21

06 May '21

Attention is currently required from: Christian Walter, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52968 ) Change subject: security/tpm/tspi/crtm: Fix FMAP TPM PCR ...................................................................... Patch Set 1: (1 comment) File src/security/tpm/tspi/crtm.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118567): https://review.coreboot.org/c/coreboot/+/52968/comment/af343b0e_7150fdf6 PS1, Line 25: * + Measures the FMAP FMAP partion. 'partion' may be misspelled - perhaps 'partition'? -- To view, visit https://review.coreboot.org/c/coreboot/+/52968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23e61a2dc25cd1c1343fb438febaf8771d1c0621 Gerrit-Change-Number: 52968 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 06 May 2021 07:37:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: security/tpm/tspi/crtm: Fix FMAP TPM PCR
by Arthur Heymans (Code Review) 06 May '21

06 May '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52968 ) Change subject: security/tpm/tspi/crtm: Fix FMAP TPM PCR ...................................................................... security/tpm/tspi/crtm: Fix FMAP TPM PCR TPM_RUNTIME_DATA_PCR is for "for measuring data which changes during runtime e.g. CMOS, NVRAM..." according to comments. FMAP does not change during runtime. Change-Id: I23e61a2dc25cd1c1343fb438febaf8771d1c0621 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/security/tpm/tspi/crtm.c M src/security/tpm/tspi/crtm.h 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/52968/1 diff --git a/src/security/tpm/tspi/crtm.c b/src/security/tpm/tspi/crtm.c index 0841d23..147fc76 100644 --- a/src/security/tpm/tspi/crtm.c +++ b/src/security/tpm/tspi/crtm.c @@ -61,7 +61,7 @@ struct region_device fmap; if (fmap_locate_area_as_rdev("FMAP", &fmap) == 0) { - if (tpm_measure_region(&fmap, TPM_RUNTIME_DATA_PCR, "FMAP: FMAP")) { + if (tpm_measure_region(&fmap, TPM_CRTM_PCR, "FMAP: FMAP")) { printk(BIOS_ERR, "TSPI: Couldn't measure FMAP into CRTM!\n"); return VB2_ERROR_UNKNOWN; diff --git a/src/security/tpm/tspi/crtm.h b/src/security/tpm/tspi/crtm.h index f3678ef..2c139ed 100644 --- a/src/security/tpm/tspi/crtm.h +++ b/src/security/tpm/tspi/crtm.h @@ -22,6 +22,7 @@ * itself. * * Summary: + * + Measures the FMAP FMAP partion. * + Measures bootblock in CBFS or BOOTBLOCK FMAP partition. * + If vboot starts in romstage, it measures the romstage * in CBFS. -- To view, visit https://review.coreboot.org/c/coreboot/+/52968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23e61a2dc25cd1c1343fb438febaf8771d1c0621 Gerrit-Change-Number: 52968 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: security/tpm/crtm: Measure FMAP into TPM
by Arthur Heymans (Code Review) 06 May '21

06 May '21

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52753 ) Change subject: security/tpm/crtm: Measure FMAP into TPM ...................................................................... Patch Set 4: (1 comment) File src/security/tpm/tspi/crtm.c: https://review.coreboot.org/c/coreboot/+/52753/comment/0c14bcc7_f4060301 PS2, Line 64: TPM_CRTM_PCR > So why is it runtime? (Sorry, I expected someone else would answer this and it wouldn't go in so quickly...) Isn't "runtime" for data that is somewhat variable and can change between units or boots or something, whereas "CRTM" is for the core code and data components that are fundamental to the security of the system? If so I would definitely expect the FMAP layout to count to CRTM just like all the code stages in CBFS. CBFS is anchored in the FMAP, after all. Hmm I should have read the comments defining those constants... -- To view, visit https://review.coreboot.org/c/coreboot/+/52753 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic424a094e7f790cce45c5a98b8bc6d46a8dcca1b Gerrit-Change-Number: 52753 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 06 May 2021 07:32:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: lib/romstage_handoff.c: Initialize using a cbmem hook
by Arthur Heymans (Code Review) 06 May '21

06 May '21

Attention is currently required from: Damien Zammit, Lee Leahy, Huang Jin, Kyösti Mälkki, Andrey Petrov. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52933 ) Change subject: lib/romstage_handoff.c: Initialize using a cbmem hook ...................................................................... Patch Set 3: Code-Review-1 (1 comment) Patchset: PS3: > I'd rather just get rid of romstage_handoff completely and converge the existing chipset_state into one implementation. Agreed. I'll work on that. -- To view, visit https://review.coreboot.org/c/coreboot/+/52933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93abf33a6eb055eeaba1fed5042387822de1aa20 Gerrit-Change-Number: 52933 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Damien Zammit Gerrit-Attention: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Attention: Huang Jin <huang.jin(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Thu, 06 May 2021 07:21:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/magolor: Select elan hidi2c address based on FW_...
by David Wu (Code Review) 06 May '21

06 May '21

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52967 ) Change subject: mb/google/dedede/var/magolor: Select elan hidi2c address based on FW_CONFIG value ...................................................................... mb/google/dedede/var/magolor: Select elan hidi2c address based on FW_CONFIG value Select elan hidi2c address 0x10 for magister, based on the value set in the FW_CONFIG. BUG=b:186609348 TEST=build and boot to OS. Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: Id157096a83e7265f6e01e353256e08f9672224f8 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/magolor/overridetree.cb 2 files changed, 30 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/52967/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index f33995c..f981ed0 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -17,6 +17,10 @@ option RT1015_I2C 2 option RT1015P_AUTO 3 end + field ELAN_HID_ADD 17 + option ELAN_NONE 0 + option ELAN_ADD10 1 + end end chip soc/intel/jasperlake diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb index 841f7d6..ce82f96 100644 --- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb +++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb @@ -181,7 +181,29 @@ register "generic.has_power_resource" = "1" register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" - device i2c 15 on end + device i2c 15 on + probe ELAN_HID_ADD ELAN_NONE + end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN6918"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "generic.stop_delay_ms" = "280" + register "generic.stop_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on + probe ELAN_HID_ADD ELAN_ADD10 + end end chip drivers/i2c/generic register "hid" = ""ELAN0001"" @@ -193,7 +215,9 @@ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" register "enable_delay_ms" = "1" register "has_power_resource" = "1" - device i2c 10 on end + device i2c 10 on + probe ELAN_HID_ADD ELAN_NONE + end end chip drivers/i2c/generic register "hid" = ""RAYD0001"" -- To view, visit https://review.coreboot.org/c/coreboot/+/52967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id157096a83e7265f6e01e353256e08f9672224f8 Gerrit-Change-Number: 52967 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure as L2 cache
by Yu-Ping Wu (Code Review) 06 May '21

06 May '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Paul Menzel, Yidi Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52925 ) Change subject: soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure as L2 cache ...................................................................... Patch Set 3: (1 comment) File src/soc/mediatek/mt8195/mmu_operations.c: PS3: This file looks exactly the same as mt8192. If mt8195's mtk_soc_after_dram() will also be the same, could we move mmu_operations to soc/mediatek/common? (We may need to rename mt8195_mcucfg to mcucfg) -- To view, visit https://review.coreboot.org/c/coreboot/+/52925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8777b0c8471fe17ffffdcb6ad5b7c00fb1d35db1 Gerrit-Change-Number: 52925 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Comment-Date: Thu, 06 May 2021 06:49:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: TEST-ONLY: vendorcode/mediatek/mt8192: force use 0.6875mV(SHU1) for 3...
by Xi Chen (Code Review) 06 May '21

06 May '21

Attention is currently required from: Xixi Chen. Hello Xixi Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/52966 to review the following change. Change subject: TEST-ONLY: vendorcode/mediatek/mt8192: force use 0.6875mV(SHU1) for 3200Mbps ...................................................................... TEST-ONLY: vendorcode/mediatek/mt8192: force use 0.6875mV(SHU1) for 3200Mbps Signed-off-by: Xi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Change-Id: I50d20f66b03506817ba1ab7a55e2f1a516ad5559 --- M src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/52966/1 diff --git a/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c b/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c index c228c2c..24d4335 100644 --- a/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c +++ b/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c @@ -1653,6 +1653,9 @@ final_shu = SRAM_SHU0; //DDR4266 #endif + // force to SHU1 to use 0.687mV + final_shu = SRAM_SHU1; + vSetDFSFreqSelByTable(p, get_FreqTbl_by_shuffleIndex(p, final_shu)); DramcDFSDirectJump_SRAMShuRGMode(p, SRAM_SHU1); DramcDFSDirectJump_SRAMShuRGMode(p, final_shu); -- To view, visit https://review.coreboot.org/c/coreboot/+/52966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50d20f66b03506817ba1ab7a55e2f1a516ad5559 Gerrit-Change-Number: 52966 Gerrit-PatchSet: 1 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/cherry: configure GPIOs
by Yu-Ping Wu (Code Review) 06 May '21

06 May '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Paul Menzel, Yidi Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52924 ) Change subject: mb/google/cherry: configure GPIOs ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52924/comment/31f132c5_ad115669 PS2, Line 9: GPIO. : Including GPIO_EC_AP_INT, GPIO_SD_CD, GPIO_EC_IN_RW, : GPIO_GSC_AP_INT and GPIO_EN_SPK. GPIOs, including EC_AP_INT, SD_CD, EC_IN_RW, GSC_AP_INT and EN_SPK. -- To view, visit https://review.coreboot.org/c/coreboot/+/52924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id553f632412af440d21a3b51e017cb74cc27fd22 Gerrit-Change-Number: 52924 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Comment-Date: Thu, 06 May 2021 06:40:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: amd/cezanne: verify transfer buffer in bootblock
by Kangheui Won (Code Review) 06 May '21

06 May '21

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Change in coreboot[master]: psp_verstage: differentiate bios entry
by Kangheui Won (Code Review) 06 May '21

06 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Kangheui Won has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52964 ) Change subject: psp_verstage: differentiate bios entry ...................................................................... psp_verstage: differentiate bios entry AMDFW tool stores bios dir entry to bios1_entry in picasso but bios3_entry in cezanne. Separate getting bios_dir_addr into a function and implement it on each platforms. Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: Ie18ed7979a04319c074b9b251130d419dc7f22dc --- M src/soc/amd/cezanne/psp_verstage/chipset.c M src/soc/amd/common/psp_verstage/include/psp_verstage.h M src/soc/amd/common/psp_verstage/psp_verstage.c M src/soc/amd/picasso/psp_verstage/chipset.c 4 files changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/52964/1 diff --git a/src/soc/amd/cezanne/psp_verstage/chipset.c b/src/soc/amd/cezanne/psp_verstage/chipset.c index 7f944eb..c0593bf 100644 --- a/src/soc/amd/cezanne/psp_verstage/chipset.c +++ b/src/soc/amd/cezanne/psp_verstage/chipset.c @@ -21,6 +21,11 @@ return svc_save_uapp_data(address, size); } +uint32_t get_bios_dir_addr(struct psp_ef_table *ef_table) +{ + return ef_table->bios3_entry; +} + /* Functions below are stub functions for not-yet-implemented PSP features. * These functions should be replaced with proper implementations later. diff --git a/src/soc/amd/common/psp_verstage/include/psp_verstage.h b/src/soc/amd/common/psp_verstage/include/psp_verstage.h index 6589725..7bfc8b7 100644 --- a/src/soc/amd/common/psp_verstage/include/psp_verstage.h +++ b/src/soc/amd/common/psp_verstage/include/psp_verstage.h @@ -48,6 +48,8 @@ uint32_t bios0_entry; uint32_t bios1_entry; uint32_t bios2_entry; + uint32_t reserved1; + uint32_t bios3_entry; } __attribute__((packed, aligned(16))); void test_svc_calls(void); @@ -59,5 +61,6 @@ uint32_t get_max_workbuf_size(uint32_t *size); uint32_t update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t *bios_dir_offset); uint32_t save_uapp_data(void *address, uint32_t size); +uint32_t get_bios_dir_addr(struct psp_ef_table *ef_table); #endif /* PSP_VERSTAGE_H */ diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index f6cc5e9..2265e17 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -107,7 +107,7 @@ } psp_dir_addr = ef_table->psp_table; - bios_dir_addr = ef_table->bios1_entry; + bios_dir_addr = get_bios_dir_addr(ef_table); psp_dir_in_spi = (uint32_t *)((psp_dir_addr & SPI_ADDR_MASK) + (uint32_t)boot_dev.base); bios_dir_in_spi = (uint32_t *)((bios_dir_addr & SPI_ADDR_MASK) + diff --git a/src/soc/amd/picasso/psp_verstage/chipset.c b/src/soc/amd/picasso/psp_verstage/chipset.c index d53f8a0..b7acbcd 100644 --- a/src/soc/amd/picasso/psp_verstage/chipset.c +++ b/src/soc/amd/picasso/psp_verstage/chipset.c @@ -19,3 +19,7 @@ return svc_get_max_workbuf_size(size); } +uint32_t get_bios_dir_addr(struct psp_ef_table *ef_table) +{ + return ef_table->bios1_entry; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/52964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie18ed7979a04319c074b9b251130d419dc7f22dc Gerrit-Change-Number: 52964 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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coreboot-gerrit May 2021