coreboot-gerrit May 2021

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Change in coreboot[master]: src/console: add interrupt enable and status methods
by Kyösti Mälkki (Code Review) 06 May '21

06 May '21

Attention is currently required from: Marc Jones, Jonathan Zhang, Johnny Lin, Rocky Phagura, Angel Pons, Arthur Heymans. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52918 ) Change subject: src/console: add interrupt enable and status methods ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Were the changes submitted, where SMM has console without DEBUG_SMI? -- To view, visit https://review.coreboot.org/c/coreboot/+/52918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e6fe8b82dd6b4d10f84ef4ac28c7cddc71c1bc9 Gerrit-Change-Number: 52918 Gerrit-PatchSet: 2 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Rocky Phagura <rphagura(a)fb.com> Gerrit-Attention: Rocky Phagura Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 06 May 2021 03:08:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: lib/romstage_handoff.c: Initialize using a cbmem hook
by Kyösti Mälkki (Code Review) 06 May '21

06 May '21

Attention is currently required from: Damien Zammit, Lee Leahy, Huang Jin, Arthur Heymans, Andrey Petrov. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52933 ) Change subject: lib/romstage_handoff.c: Initialize using a cbmem hook ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: I'd rather just get rid of romstage_handoff completely and converge the existing chipset_state into one implementation. -- To view, visit https://review.coreboot.org/c/coreboot/+/52933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93abf33a6eb055eeaba1fed5042387822de1aa20 Gerrit-Change-Number: 52933 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Damien Zammit Gerrit-Attention: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Attention: Huang Jin <huang.jin(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Thu, 06 May 2021 03:05:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: include/console: Fix duplicate entry of postcode 0x79
by Furquan Shaikh (Code Review) 05 May '21

05 May '21

Attention is currently required from: Subrata Banik, Nico Huber, Tim Wawrzynczak, Angel Pons. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52895 ) Change subject: include/console: Fix duplicate entry of postcode 0x79 ...................................................................... Patch Set 4: (1 comment) File src/include/console/post_codes.h: https://review.coreboot.org/c/coreboot/+/52895/comment/ed80903d_14931346 PS3, Line 190: POST_BS_WRITE_TABLES > @Angel, as we are planning to move POST_PRE_HARDWAREMAIN and POST_ENTRY_RAMSTAGE between 0x6e and 0 […] All the POST_BS_* post codes are used in the boot state machine as the comment indicates. They are not referenced directly but using the token concatenation: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr… That is why they do not show up in grep. -- To view, visit https://review.coreboot.org/c/coreboot/+/52895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50cc75cd3097fba3e7faff05188511bba69ef1e7 Gerrit-Change-Number: 52895 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Thu, 06 May 2021 01:35:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subi.banik(a)gmail.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/sn65dsi86: Switch EDID reading to use "indirect mode"
by Julius Werner (Code Review) 05 May '21

05 May '21

Attention is currently required from: Vinod Polimera, Doug Anderson, Julius Werner, Xuxin Xiong. Hello Vinod Polimera, build bot (Jenkins), Doug Anderson, Xuxin Xiong, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52959 to look at the new patch set (#2). Change subject: drivers/sn65dsi86: Switch EDID reading to use "indirect mode" ...................................................................... drivers/sn65dsi86: Switch EDID reading to use "indirect mode" The SN65DSI86 eDP bridge supports two ways to read the EDID: for now we've been using "direct mode", which works by basically making the bridge I2C device listen to another chip address besides its own and proxy all requests received there directly to the eDP AUX channel. The great part about that mode is that it is super easy and hassle-free to use. The not so great part about it is that it doesn't work: for EDID extensions, the last byte (which happens to contain the checksum) is somehow always read as zero. We presume this is a hardware bug in the bridge part. The other, much more annoying way is "indirect mode", where each byte transmitted over the AUX channel has to be manually set up in the I2C registers of the bridge, just like we're already doing with DPCD transactions. Thankfully, we can reuse most of the DPCD code for this so it's not a lot of extra code. It's a bit slower but not as much as you'd expect (26ms instead of 18ms on my board), and the difference is not very relevant compared to common total times for display init. Also, some of the (previously unused) enum definitions for the AUX_CMD mode field of the bridge had just been plain wrong for some reason, and needed to be fixed to make this work. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I65f80193380d3c3841f9f5c26897ed672f45e15a --- M src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c 1 file changed, 101 insertions(+), 75 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/52959/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65f80193380d3c3841f9f5c26897ed672f45e15a Gerrit-Change-Number: 52959 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Doug Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Vinod Polimera <vpolimer(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Vinod Polimera <vpolimer(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Doug Anderson <dianders(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/sn65dsi86: Switch EDID reading to use "indirect mode"
by build bot (Jenkins) (Code Review) 05 May '21

05 May '21

Attention is currently required from: Doug Anderson. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52959 ) Change subject: drivers/sn65dsi86: Switch EDID reading to use "indirect mode" ...................................................................... Patch Set 1: (2 comments) File src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118554): https://review.coreboot.org/c/coreboot/+/52959/comment/3cbbdcc8_2b67bee3 PS1, Line 200: rv |= i2c_writeb(bus, chip, SN_AUX_LENGTH_REG, length); /* size of 1 Byte data */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118554): https://review.coreboot.org/c/coreboot/+/52959/comment/53ddb187_80274463 PS1, Line 201: rv |= i2c_writeb(bus, chip, SN_AUX_CMD_REG, AUX_CMD_SEND | (command[request] << 4)); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/52959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65f80193380d3c3841f9f5c26897ed672f45e15a Gerrit-Change-Number: 52959 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Doug Anderson <dianders(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Doug Anderson <dianders(a)chromium.org> Gerrit-Comment-Date: Thu, 06 May 2021 00:54:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/sn65dsi86: Switch EDID reading to use "indirect mode"
by Julius Werner (Code Review) 05 May '21

05 May '21

Attention is currently required from: Doug Anderson. Hello Doug Anderson, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/52959 to review the following change. Change subject: drivers/sn65dsi86: Switch EDID reading to use "indirect mode" ...................................................................... drivers/sn65dsi86: Switch EDID reading to use "indirect mode" The SN65DSI86 eDP bridge supports two ways to read the EDID: for now we've been using "direct mode", which works by basically making the bridge I2C device listen to another chip address besides its own and proxy all requests received there directly to the eDP AUX channel. The great part about that mode is that it is super easy and hassle-free to use. The not so great part about it is that it doesn't work: for EDID extensions, the last byte (which happens to contain the checksum) is somehow always read as zero. We presume this is a hardware bug in the bridge part. The other, much more annoying way is "indirect mode", where each byte transmitted over the AUX channel has to be manually set up in the I2C registers of the bridge, just like we're already doing with DPCD transactions. Thankfully, we can reuse most of the DPCD code for this so it's not a lot of extra code. It's a bit slower but not as much as you'd expect (26ms instead of 18ms on my board), and the difference is not very relevant compared to common total times for display init. Also, some of the (previously unused) enum definitions for the AUX_CMD mode field of the bridge had just been plain wrong for some reason, and needed to be fixed to make this work. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I65f80193380d3c3841f9f5c26897ed672f45e15a --- M src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c 1 file changed, 101 insertions(+), 75 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/52959/1 diff --git a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c index ca41cdb..386f4d5 100644 --- a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c +++ b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c @@ -127,10 +127,10 @@ enum i2c_over_aux { I2C_OVER_AUX_WRITE_MOT_0 = 0x0, I2C_OVER_AUX_READ_MOT_0 = 0x1, - I2C_OVER_AUX_WRITE_STATUS_UPDATE_0 = 0x4, - I2C_OVER_AUX_WRITE_MOT_1 = 0x5, - I2C_OVER_AUX_READ_MOT_1 = 0x6, - I2C_OVER_AUX_WRITE_STATUS_UPDATE_1 = 0x7, + I2C_OVER_AUX_WRITE_STATUS_UPDATE_0 = 0x2, + I2C_OVER_AUX_WRITE_MOT_1 = 0x4, + I2C_OVER_AUX_READ_MOT_1 = 0x5, + I2C_OVER_AUX_WRITE_STATUS_UPDATE_1 = 0x6, NATIVE_AUX_WRITE = 0x8, NATIVE_AUX_READ = 0x9, }; @@ -150,9 +150,11 @@ REDRIVER_SEMI_AUTO_LINK_TRAINING = 0xb, }; -enum dpcd_request { - DPCD_READ = 0x0, - DPCD_WRITE = 0x1, +enum aux_request { + DPCD_READ, + DPCD_WRITE, + I2C_RAW_READ, + I2C_RAW_WRITE, }; enum { @@ -169,29 +171,99 @@ 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400 }; -enum cb_err sn65dsi86_bridge_read_edid(uint8_t bus, uint8_t chip, struct edid *out) +static cb_err_t sn65dsi86_bridge_aux_request(uint8_t bus, + uint8_t chip, + unsigned int target_reg, + unsigned int len, + enum aux_request request, + uint8_t *data) { - int ret; + int rv; + int i; + uint32_t length; + uint8_t buf; + uint8_t reg; + + static const uint8_t command[] = { + [DPCD_WRITE] = NATIVE_AUX_WRITE, + [DPCD_READ] = NATIVE_AUX_READ, + [I2C_RAW_WRITE] = I2C_OVER_AUX_WRITE_MOT_1, + [I2C_RAW_READ] = I2C_OVER_AUX_READ_MOT_1, + }; + + while (len) { + length = MIN(len, 16); + + rv = i2c_writeb(bus, chip, SN_AUX_ADDR_19_16_REG, (target_reg >> 16) & 0xF); + rv |= i2c_writeb(bus, chip, SN_AUX_ADDR_15_8_REG, (target_reg >> 8) & 0xFF); + rv |= i2c_writeb(bus, chip, SN_AUX_ADDR_7_0_REG, (target_reg) & 0xFF); + rv |= i2c_writeb(bus, chip, SN_AUX_LENGTH_REG, length); /* size of 1 Byte data */ + rv |= i2c_writeb(bus, chip, SN_AUX_CMD_REG, AUX_CMD_SEND | (command[request] << 4)); + if (rv) { + printk(BIOS_ERR, "ERROR: aux command setup failed\n"); + return CB_ERR; + } + + if (request == DPCD_WRITE || request == I2C_RAW_WRITE) { + reg = SN_AUX_WDATA_REG_0; + for (i = 0; i < length; i++) + if (i2c_writeb(bus, chip, reg++, *data++)) { + printk(BIOS_ERR, "ERROR: aux command write failed\n"); + return CB_ERR; + } + + } else { + if (!wait_ms(100, + !i2c_readb(bus, chip, SN_AUX_CMD_REG, + &buf) && !(buf & AUX_CMD_SEND))) { + printk(BIOS_ERR, "ERROR: aux command send failed\n"); + return CB_ERR; + } + + reg = SN_AUX_RDATA_REG_0; + for (i = 0; i < length; i++) { + if (i2c_readb(bus, chip, reg++, &buf)) { + printk(BIOS_ERR, "ERROR: aux command read failed\n"); + return CB_ERR; + } + *data++ = buf; + } + } + + len -= length; + } + + return CB_SUCCESS; +} + +cb_err_t sn65dsi86_bridge_read_edid(uint8_t bus, uint8_t chip, struct edid *out) +{ + cb_err_t err; u8 edid[EDID_LENGTH * 2]; int edid_size = EDID_LENGTH; - /* Send I2C command to claim EDID I2c slave */ - i2c_writeb(bus, chip, SN_I2C_CLAIM_ADDR_EN1, (EDID_I2C_ADDR << 1) | 0x1); - - /* read EDID */ - ret = i2c_read_bytes(bus, EDID_I2C_ADDR, 0x0, edid, EDID_LENGTH); - if (ret != 0) { + uint8_t reg_addr = 0; + err = sn65dsi86_bridge_aux_request(bus, chip, EDID_I2C_ADDR, 1, + I2C_RAW_WRITE, &reg_addr); + if (!err) + err = sn65dsi86_bridge_aux_request(bus, chip, EDID_I2C_ADDR, EDID_LENGTH, + I2C_RAW_READ, edid); + if (err) { printk(BIOS_ERR, "ERROR: Failed to read EDID.\n"); - return CB_ERR; + return err; } if (edid[EDID_EXTENSION_FLAG]) { edid_size += EDID_LENGTH; - ret = i2c_read_bytes(bus, EDID_I2C_ADDR, EDID_LENGTH, - &edid[EDID_LENGTH], EDID_LENGTH); - if (ret != 0) { + reg_addr = EDID_LENGTH; + err = sn65dsi86_bridge_aux_request(bus, chip, EDID_I2C_ADDR, 1, + I2C_RAW_WRITE, &reg_addr); + if (!err) + err = sn65dsi86_bridge_aux_request(bus, chip, EDID_I2C_ADDR, + EDID_LENGTH, I2C_RAW_READ, &edid[EDID_LENGTH]); + if (err) { printk(BIOS_ERR, "Failed to read EDID ext block.\n"); - return CB_ERR; + return err; } } @@ -203,67 +275,21 @@ return CB_SUCCESS; } -static void sn65dsi86_bridge_dpcd_request(uint8_t bus, - uint8_t chip, - unsigned int dpcd_reg, - unsigned int len, - enum dpcd_request request, - uint8_t *data) -{ - int i; - uint32_t length; - uint8_t buf; - uint8_t reg; - - while (len) { - length = MIN(len, 16); - - i2c_writeb(bus, chip, SN_AUX_ADDR_19_16_REG, (dpcd_reg >> 16) & 0xF); - i2c_writeb(bus, chip, SN_AUX_ADDR_15_8_REG, (dpcd_reg >> 8) & 0xFF); - i2c_writeb(bus, chip, SN_AUX_ADDR_7_0_REG, (dpcd_reg) & 0xFF); - i2c_writeb(bus, chip, SN_AUX_LENGTH_REG, length); /* size of 1 Byte data */ - if (request == DPCD_WRITE) { - reg = SN_AUX_WDATA_REG_0; - for (i = 0; i < length; i++) - i2c_writeb(bus, chip, reg++, *data++); - - i2c_writeb(bus, chip, - SN_AUX_CMD_REG, AUX_CMD_SEND | (NATIVE_AUX_WRITE << 4)); - } else { - i2c_writeb(bus, chip, - SN_AUX_CMD_REG, AUX_CMD_SEND | (NATIVE_AUX_READ << 4)); - if (!wait_ms(100, - !i2c_readb(bus, chip, SN_AUX_CMD_REG, - &buf) && !(buf & AUX_CMD_SEND))) { - printk(BIOS_ERR, "ERROR: aux command send failed\n"); - } - - reg = SN_AUX_RDATA_REG_0; - for (i = 0; i < length; i++) { - i2c_readb(bus, chip, reg++, &buf); - *data++ = buf; - } - } - - len -= length; - } -} - static void sn65dsi86_bridge_valid_dp_rates(uint8_t bus, uint8_t chip, bool rate_valid[]) { unsigned int rate_per_200khz; uint8_t dpcd_val; int i, j; - sn65dsi86_bridge_dpcd_request(bus, chip, - DP_BRIDGE_DPCD_REV, 1, DPCD_READ, &dpcd_val); + sn65dsi86_bridge_aux_request(bus, chip, + DP_BRIDGE_DPCD_REV, 1, DPCD_READ, &dpcd_val); if (dpcd_val >= DP_BRIDGE_14) { /* eDP 1.4 devices must provide a custom table */ uint16_t sink_rates[DP_MAX_SUPPORTED_RATES] = {0}; - sn65dsi86_bridge_dpcd_request(bus, chip, DP_SUPPORTED_LINK_RATES, - sizeof(sink_rates), - DPCD_READ, (void *)sink_rates); + sn65dsi86_bridge_aux_request(bus, chip, DP_SUPPORTED_LINK_RATES, + sizeof(sink_rates), + DPCD_READ, (void *)sink_rates); for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { rate_per_200khz = le16_to_cpu(sink_rates[i]); @@ -288,7 +314,7 @@ } /* On older versions best we can do is use DP_MAX_LINK_RATE */ - sn65dsi86_bridge_dpcd_request(bus, chip, DP_MAX_LINK_RATE, 1, DPCD_READ, &dpcd_val); + sn65dsi86_bridge_aux_request(bus, chip, DP_MAX_LINK_RATE, 1, DPCD_READ, &dpcd_val); switch (dpcd_val) { default: @@ -410,8 +436,8 @@ * at DisplayPort address 0x0010A prior to link training. */ buf = 0x1; - sn65dsi86_bridge_dpcd_request(bus, chip, - DP_BRIDGE_CONFIGURATION_SET, 1, DPCD_WRITE, &buf); + sn65dsi86_bridge_aux_request(bus, chip, + DP_BRIDGE_CONFIGURATION_SET, 1, DPCD_WRITE, &buf); int i; /* Kernel driver suggests to retry this up to 10 times if it fails. */ for (i = 0; i < 10; i++) { @@ -441,7 +467,7 @@ { uint8_t lane_count; - sn65dsi86_bridge_dpcd_request(bus, chip, DP_MAX_LANE_COUNT, 1, DPCD_READ, &lane_count); + sn65dsi86_bridge_aux_request(bus, chip, DP_MAX_LANE_COUNT, 1, DPCD_READ, &lane_count); lane_count &= DP_LANE_COUNT_MASK; i2c_write_field(bus, chip, SN_SSC_CONFIG_REG, MIN(lane_count, 3), 3, 4); -- To view, visit https://review.coreboot.org/c/coreboot/+/52959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65f80193380d3c3841f9f5c26897ed672f45e15a Gerrit-Change-Number: 52959 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Doug Anderson <dianders(a)chromium.org> Gerrit-Attention: Doug Anderson <dianders(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmaster
by Kane Chen (Code Review) 05 May '21

05 May '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Kane Chen, Karthik Ramasubramanian. Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52873 ) Change subject: soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmaster ...................................................................... Patch Set 6: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/52873/comment/8754de70_f35757dd PS5, Line 20: > nit: `TEST=... […] Done File src/soc/intel/alderlake/smihandler.c: https://review.coreboot.org/c/coreboot/+/52873/comment/078735a4_475026a6 PS5, Line 28: { > a small comment referencing why this is done at the top of these functions would be helpful Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cf5cf91ebad4a49df6679e01fc88ff60c81526c Gerrit-Change-Number: 52873 Gerrit-PatchSet: 6 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 05 May 2021 23:59:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXIT
by Kane Chen (Code Review) 05 May '21

05 May '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Kane Chen, Karthik Ramasubramanian. Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52874 ) Change subject: soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXIT ...................................................................... Patch Set 7: (3 comments) File src/soc/intel/alderlake/pmc.c: https://review.coreboot.org/c/coreboot/+/52874/comment/a2d8d862_784f5eff PS6, Line 147: /* : * Enable Power button SMI only after BS_DEV_INIT_CHIPS (FSP-S) is done. : */ > nit: can be a one-line comment Done File src/soc/intel/jasperlake/pmc.c: https://review.coreboot.org/c/coreboot/+/52874/comment/9bcbd8d7_0a28bed1 PS6, Line 98: /* : * Enable Power button SMI only after BS_DEV_INIT_CHIPS (FSP-S) is done. : */ > same Done File src/soc/intel/tigerlake/pmc.c: https://review.coreboot.org/c/coreboot/+/52874/comment/339004df_2464376c PS6, Line 151: /* : * Enable Power button SMI only after BS_DEV_INIT_CHIPS (FSP-S) is done. : */ > same Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70b871f2676a89bc782116e02beba5c20ec51eef Gerrit-Change-Number: 52874 Gerrit-PatchSet: 7 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 05 May 2021 23:59:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXIT
by Kane Chen (Code Review) 05 May '21

05 May '21

Attention is currently required from: Furquan Shaikh, Karthik Ramasubramanian. Hello build bot (Jenkins), Furquan Shaikh, Kane Chen, Tim Wawrzynczak, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52874 to look at the new patch set (#7). Change subject: soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXIT ...................................................................... soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXIT On tgl, we noticed system hang if a shutdown is triggered before fsps. The dut is unable to shutdown properly due to tcss is stuck before tcss_init in fsps. This change enable power button smi on jsl, tgl, adl after fsps. it can also prevent a shutdown failure due to lack of fsps init on certain ip. BUG=b:186194102, b:186815114 TEST=Power on the system and pressing power button repeatedly doesn't cause the system hang during shutdown. Change-Id: I70b871f2676a89bc782116e02beba5c20ec51eef Signed-off-by: Kane Chen <kane.chen(a)intel.corp-partner.google.com> --- M src/soc/intel/alderlake/cpu.c M src/soc/intel/alderlake/pmc.c M src/soc/intel/jasperlake/cpu.c M src/soc/intel/jasperlake/pmc.c M src/soc/intel/tigerlake/cpu.c M src/soc/intel/tigerlake/pmc.c 6 files changed, 38 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/52874/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/52874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70b871f2676a89bc782116e02beba5c20ec51eef Gerrit-Change-Number: 52874 Gerrit-PatchSet: 7 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmaster
by Kane Chen (Code Review) 05 May '21

05 May '21

Attention is currently required from: Furquan Shaikh, Kane Chen, Karthik Ramasubramanian. Hello build bot (Jenkins), Furquan Shaikh, Kane Chen, Tim Wawrzynczak, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52873 to look at the new patch set (#6). Change subject: soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmaster ...................................................................... soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmaster If a power button SMI is triggered between where it is currently enabled and before FSP-S exits, when the SMI handler disables bus mastering for all devices, it inadvertently also disables the PMC's I/O decoding, so the register write to actually go into S5 does not succeed, and the system hangs. This can be solved by skipping the PMC when disabling bus mastering in the SMI handler, for which a callback, smihandler_soc_disable_busmaster is provided. BUG=b:186194102, b:186815114 TEST=Power on the system and pressing power button repeatedly doesn't cause the system hang during shutdown. Change-Id: I1cf5cf91ebad4a49df6679e01fc88ff60c81526c Signed-off-by: Kane Chen <kane.chen(a)intel.corp-partner.google.com> --- M src/soc/intel/alderlake/smihandler.c M src/soc/intel/jasperlake/smihandler.c M src/soc/intel/tigerlake/smihandler.c 3 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/52873/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/52873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cf5cf91ebad4a49df6679e01fc88ff60c81526c Gerrit-Change-Number: 52873 Gerrit-PatchSet: 6 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit May 2021