coreboot-gerrit May 2021

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Change in coreboot[master]: psp_verstage: move platform-specific code to chipset.c
by Kangheui Won (Code Review) 06 May '21

06 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Kangheui Won has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52963 ) Change subject: psp_verstage: move platform-specific code to chipset.c ...................................................................... psp_verstage: move platform-specific code to chipset.c Move all platform-specific code except direct svc calls to chipset.c. There will be differences between each platforms and we can't put everything into svc.c. TEST=build firmware for zork Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: Ie7a71d1632800072a17c26591e13e09e0269cf75 --- M src/soc/amd/cezanne/psp_verstage/Makefile.inc R src/soc/amd/cezanne/psp_verstage/chipset.c M src/soc/amd/cezanne/psp_verstage/svc.c M src/soc/amd/picasso/psp_verstage/Makefile.inc A src/soc/amd/picasso/psp_verstage/chipset.c M src/soc/amd/picasso/psp_verstage/svc.c 6 files changed, 38 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/52963/1 diff --git a/src/soc/amd/cezanne/psp_verstage/Makefile.inc b/src/soc/amd/cezanne/psp_verstage/Makefile.inc index 8bb1173..433bfa7 100644 --- a/src/soc/amd/cezanne/psp_verstage/Makefile.inc +++ b/src/soc/amd/cezanne/psp_verstage/Makefile.inc @@ -8,7 +8,7 @@ subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../../common/psp_verstage verstage-y += svc.c -verstage-y += stub.c +verstage-y += chipset.c verstage-y += $(top)/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_startup.S verstage-y += $(top)/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_end.S diff --git a/src/soc/amd/cezanne/psp_verstage/stub.c b/src/soc/amd/cezanne/psp_verstage/chipset.c similarity index 61% rename from src/soc/amd/cezanne/psp_verstage/stub.c rename to src/soc/amd/cezanne/psp_verstage/chipset.c index b3ec704..7f944eb 100644 --- a/src/soc/amd/cezanne/psp_verstage/stub.c +++ b/src/soc/amd/cezanne/psp_verstage/chipset.c @@ -11,6 +11,21 @@ #include <reset.h> #include <timer.h> +uint32_t update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t *bios_dir_offset) +{ + return svc_update_psp_bios_dir(psp_dir_offset, bios_dir_offset); +} + +uint32_t save_uapp_data(void *address, uint32_t size) +{ + return svc_save_uapp_data(address, size); +} + + +/* Functions below are stub functions for not-yet-implemented PSP features. + * These functions should be replaced with proper implementations later. + */ + uint32_t svc_write_postcode(uint32_t postcode) { return 0; diff --git a/src/soc/amd/cezanne/psp_verstage/svc.c b/src/soc/amd/cezanne/psp_verstage/svc.c index 3d10c22..70cb369 100644 --- a/src/soc/amd/cezanne/psp_verstage/svc.c +++ b/src/soc/amd/cezanne/psp_verstage/svc.c @@ -82,11 +82,6 @@ return retval; } -uint32_t update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t *bios_dir_offset) -{ - return svc_update_psp_bios_dir(psp_dir_offset, bios_dir_offset); -} - uint32_t svc_update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t *bios_dir_offset) { @@ -96,11 +91,6 @@ return retval; } -uint32_t save_uapp_data(void *address, uint32_t size) -{ - return svc_save_uapp_data(address, size); -} - uint32_t svc_save_uapp_data(void *address, uint32_t size) { uint32_t retval = 0; diff --git a/src/soc/amd/picasso/psp_verstage/Makefile.inc b/src/soc/amd/picasso/psp_verstage/Makefile.inc index 32b594d..41296c9 100644 --- a/src/soc/amd/picasso/psp_verstage/Makefile.inc +++ b/src/soc/amd/picasso/psp_verstage/Makefile.inc @@ -4,6 +4,7 @@ verstage-generic-ccopts += -I$(src)/vendorcode/amd/fsp/picasso/include verstage-y += svc.c +verstage-y += chipset.c verstage-y += $(top)/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_startup.S verstage-y += $(top)/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_end.S diff --git a/src/soc/amd/picasso/psp_verstage/chipset.c b/src/soc/amd/picasso/psp_verstage/chipset.c new file mode 100644 index 0000000..d53f8a0 --- /dev/null +++ b/src/soc/amd/picasso/psp_verstage/chipset.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bl_uapp/bl_syscall_public.h> +#include <psp_verstage.h> + +uint32_t update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t *bios_dir_offset) +{ + return svc_update_psp_bios_dir(psp_dir_offset, bios_dir_offset, + DIR_OFFSET_SET); +} + +uint32_t save_uapp_data(void *address, uint32_t size) +{ + return svc_save_uapp_data(UAPP_COPYBUF_CHROME_WORKBUF, address, size); +} + +uint32_t get_max_workbuf_size(uint32_t *size) +{ + return svc_get_max_workbuf_size(size); +} + diff --git a/src/soc/amd/picasso/psp_verstage/svc.c b/src/soc/amd/picasso/psp_verstage/svc.c index 28e6baf..d94ec76 100644 --- a/src/soc/amd/picasso/psp_verstage/svc.c +++ b/src/soc/amd/picasso/psp_verstage/svc.c @@ -96,12 +96,6 @@ return retval; } -uint32_t update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t *bios_dir_offset) -{ - return svc_update_psp_bios_dir(psp_dir_offset, bios_dir_offset, - DIR_OFFSET_SET); -} - uint32_t svc_update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t *bios_dir_offset, enum dir_offset_operation operation) { @@ -112,11 +106,6 @@ return retval; } -uint32_t save_uapp_data(void *address, uint32_t size) -{ - return svc_save_uapp_data(UAPP_COPYBUF_CHROME_WORKBUF, address, size); -} - uint32_t svc_save_uapp_data(enum uapp_copybuf type, void *address, uint32_t size) { @@ -149,11 +138,6 @@ return retval; } -uint32_t get_max_workbuf_size(uint32_t *size) -{ - return svc_get_max_workbuf_size(size); -} - uint32_t svc_get_max_workbuf_size(uint32_t *size) { uint32_t retval = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/52963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7a71d1632800072a17c26591e13e09e0269cf75 Gerrit-Change-Number: 52963 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: cezanne/psp_verstage: clean up duplicated target
by Kangheui Won (Code Review) 06 May '21

06 May '21

1 0

Change in coreboot[master]: cezanne/psp_verstage: populate a/b firmware
by Kangheui Won (Code Review) 06 May '21

06 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Kangheui Won has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52961 ) Change subject: cezanne/psp_verstage: populate a/b firmware ...................................................................... cezanne/psp_verstage: populate a/b firmware Build amdfw_[ab] and put them into CBFS. We can reuse FW_[AB] position from zork since we have same flash layout and size. Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: Idb31afa7a513f01593b2af75515a170dfca8d360 --- M src/mainboard/google/guybrush/Kconfig M src/mainboard/google/mancomb/Kconfig M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc 4 files changed, 97 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/52961/1 diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index 8c23cf0..ef27cd5 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -71,6 +71,22 @@ hex default 0x50 +config CEZANNE_FW_A_POSITION + hex + default 0xFF012040 + depends on VBOOT_SLOTS_RW_AB + help + Location of the AMD firmware in the RW_A region. This is the + start of the RW-A region + 64 bytes for the cbfs header. + +config CEZANNE_FW_B_POSITION + hex + default 0xFF312040 + depends on VBOOT_SLOTS_RW_AB + help + Location of the AMD firmware in the RW_B region. This is the + start of the RW-A region + 64 bytes for the cbfs header. + config EFS_SPI_READ_MODE int default 0 if EM100 # Normal read mode diff --git a/src/mainboard/google/mancomb/Kconfig b/src/mainboard/google/mancomb/Kconfig index 4ed29cd..328fb5d 100644 --- a/src/mainboard/google/mancomb/Kconfig +++ b/src/mainboard/google/mancomb/Kconfig @@ -63,6 +63,22 @@ hex default 0x50 +config CEZANNE_FW_A_POSITION + hex + default 0xFF012040 + depends on VBOOT_SLOTS_RW_AB + help + Location of the AMD firmware in the RW_A region. This is the + start of the RW-A region + 64 bytes for the cbfs header. + +config CEZANNE_FW_B_POSITION + hex + default 0xFF312040 + depends on VBOOT_SLOTS_RW_AB + help + Location of the AMD firmware in the RW_B region. This is the + start of the RW-A region + 64 bytes for the cbfs header. + config EFS_SPI_READ_MODE int default 0 if EM100 # Normal read mode diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 7d76699..cd07108 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -417,4 +417,32 @@ This is the byte before the default first byte used by VBNV (0x26 + 0x0E - 1) +if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK + +config RWA_REGION_ONLY + string + default "apu/amdfw_a" + help + Add a space-delimited list of filenames that should only be in the + RW-A section. + +config RWB_REGION_ONLY + string + default "apu/amdfw_b" + help + Add a space-delimited list of filenames that should only be in the + RW-B section. + +config CEZANNE_FW_A_POSITION + hex + help + Location of the AMD firmware in the RW_A region + +config CEZANNE_FW_B_POSITION + hex + help + Location of the AMD firmware in the RW_B region + +endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK + endif # SOC_AMD_CEZANNE diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index ebdad45..8b4b1bc 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -234,11 +234,48 @@ $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ --maxsize $(PSP_BIOSBIN_SIZE) +$(obj)/amdfw_a.rom: $(obj)/amdfw.rom + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(AMDFW_COMMON_ARGS) \ + $(OPT_APOB_NV_SIZE) \ + $(OPT_APOB_NV_BASE) \ + --location $(shell printf "%#x" $(CONFIG_CEZANNE_FW_A_POSITION)) \ + --anywhere \ + --multilevel \ + --output $@ + +$(obj)/amdfw_b.rom: $(obj)/amdfw.rom + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(AMDFW_COMMON_ARGS) \ + $(OPT_APOB_NV_SIZE) \ + $(OPT_APOB_NV_BASE) \ + --location $(shell printf "%#x" $(CONFIG_CEZANNE_FW_B_POSITION)) \ + --anywhere \ + --multilevel \ + --output $@ + + cbfs-files-y += apu/amdfw apu/amdfw-file := $(obj)/amdfw.rom apu/amdfw-position := $(CEZANNE_FWM_POSITION) apu/amdfw-type := raw +ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) +cbfs-files-y += apu/amdfw_a +apu/amdfw_a-file := $(obj)/amdfw_a.rom +apu/amdfw_a-position := $(call strip_quotes, $(CONFIG_CEZANNE_FW_A_POSITION)) +apu/amdfw_a-type := raw + +cbfs-files-y += apu/amdfw_b +apu/amdfw_b-file := $(obj)/amdfw_b.rom +apu/amdfw_b-position := $(call strip_quotes, $(CONFIG_CEZANNE_FW_B_POSITION)) +apu/amdfw_b-type := raw +endif + cpu_microcode_bins += $(wildcard ${FIRMWARE_LOCATION}/UcodePatch_*.bin) endif # ($(CONFIG_SOC_AMD_CEZANNE),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/52961 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb31afa7a513f01593b2af75515a170dfca8d360 Gerrit-Change-Number: 52961 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: cezanne/psp_verstage: reduce memory usage
by Kangheui Won (Code Review) 06 May '21

06 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Kangheui Won, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52751 to look at the new patch set (#2). Change subject: cezanne/psp_verstage: reduce memory usage ...................................................................... cezanne/psp_verstage: reduce memory usage For now we only have 80KB for psp_verstage in cezanne. (it's 160KB for picasso). So we have to trim down various things to fit into 80KB space. This should be reverted after we have enough space in the PSP since this increases boot time quite a lot. Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: I30730a6dc53e2449981c635ecfe63029c73e58ee --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/common/psp_verstage/Makefile.inc 2 files changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/52751/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52751 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30730a6dc53e2449981c635ecfe63029c73e58ee Gerrit-Change-Number: 52751 Gerrit-PatchSet: 2 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mainboard/pcengines/apu1/OemCustomize.c: make AGESA AmdInitPost happy
by Krystian Hebel (Code Review) 06 May '21

06 May '21

Attention is currently required from: Michał Żygowski. Krystian Hebel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52779 ) Change subject: mainboard/pcengines/apu1/OemCustomize.c: make AGESA AmdInitPost happy ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/52779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id555b458c61df9a27a93f44f600d1718867106ca Gerrit-Change-Number: 52779 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Thu, 06 May 2021 06:27:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: include/console: Fix duplicate entry of postcode 0x79
by Subrata Banik (Code Review) 06 May '21

06 May '21

Attention is currently required from: Subrata Banik, Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52895 ) Change subject: include/console: Fix duplicate entry of postcode 0x79 ...................................................................... Patch Set 4: (1 comment) File src/include/console/post_codes.h: https://review.coreboot.org/c/coreboot/+/52895/comment/6956ac02_3b34a8bf PS3, Line 190: POST_BS_WRITE_TABLES > All the POST_BS_* post codes are used in the boot state machine as the comment indicates. […] Ahh, got it. Thanks. btw, looks like Nico and Angel shared their feedback and i have addressed those. Can we make progress with this CL now ? -- To view, visit https://review.coreboot.org/c/coreboot/+/52895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50cc75cd3097fba3e7faff05188511bba69ef1e7 Gerrit-Change-Number: 52895 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 06 May 2021 06:27:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subi.banik(a)gmail.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/metaknight: Update LTE USB port configuration
by Karthik Ramasubramanian (Code Review) 06 May '21

06 May '21

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52960 ) Change subject: mb/google/dedede/var/metaknight: Update LTE USB port configuration ...................................................................... mb/google/dedede/var/metaknight: Update LTE USB port configuration Update LTE USB port configuration at run-time after probing the firmware config. By default the concerned USB port takes the Type-A port configuration. BUG=b:186380807 BRANCH=dedede TEST=Build and boot to OS in metaknight Change-Id: I5ad5a1670adef54075923cf912fb41a1ce776155 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/metaknight/Makefile.inc M src/mainboard/google/dedede/variants/metaknight/overridetree.cb A src/mainboard/google/dedede/variants/metaknight/ramstage.c 3 files changed, 58 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/52960/1 diff --git a/src/mainboard/google/dedede/variants/metaknight/Makefile.inc b/src/mainboard/google/dedede/variants/metaknight/Makefile.inc index 67a7ab2..2479ae9 100644 --- a/src/mainboard/google/dedede/variants/metaknight/Makefile.inc +++ b/src/mainboard/google/dedede/variants/metaknight/Makefile.inc @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only ramstage-y += gpio.c +ramstage-y += ramstage.c smm-y += variant.c diff --git a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb index 0052ec7..c8c56f9 100644 --- a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb +++ b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb @@ -69,23 +69,12 @@ chip drivers/usb/acpi device usb 0.0 on chip drivers/usb/acpi - register "desc" = ""LTE"" - register "type" = "UPC_TYPE_INTERNAL" - register "has_power_resource" = "1" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17)" - register "reset_off_delay_ms" = "10" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" - register "enable_delay_ms" = "20" - device usb 2.3 on - probe DB_PORTS DB_PORTS_LTE_HDMI - end - end - chip drivers/usb/acpi - register "desc" = ""Right Type-A Port"" + register "desc" = ""Multi-use Port"" register "type" = "UPC_TYPE_A" register "group" = "ACPI_PLD_GROUP(2, 2)" device usb 2.3 on probe DB_PORTS DB_PORTS_1A_HDMI + probe DB_PORTS DB_PORTS_LTE_HDMI end end chip drivers/usb/acpi @@ -99,18 +88,12 @@ device usb 2.6 on end end chip drivers/usb/acpi - register "desc" = ""LTE"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 3.3 on - probe DB_PORTS DB_PORTS_LTE_HDMI - end - end - chip drivers/usb/acpi - register "desc" = ""Right Type-A Port"" + register "desc" = ""Multi-use Port"" register "type" = "UPC_TYPE_USB3_A" register "group" = "ACPI_PLD_GROUP(2, 2)" device usb 3.3 on probe DB_PORTS DB_PORTS_1A_HDMI + probe DB_PORTS DB_PORTS_LTE_HDMI end end end diff --git a/src/mainboard/google/dedede/variants/metaknight/ramstage.c b/src/mainboard/google/dedede/variants/metaknight/ramstage.c new file mode 100644 index 0000000..3c8e196 --- /dev/null +++ b/src/mainboard/google/dedede/variants/metaknight/ramstage.c @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi_device.h> +#include <baseboard/variants.h> +#include <console/console.h> +#include <drivers/usb/acpi/chip.h> +#include <fw_config.h> +#include <gpio.h> +#include <soc/pci_devs.h> + +#define LTE_USB_PORT_ID 3 +#define LTE_USB_PORT_TYPE 2 +static struct acpi_gpio lte_reset_gpio = ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17); +static struct acpi_gpio lte_enable_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10); + +static void update_xhci_devtree(void) +{ + struct device *xhci, *hub = NULL, *port = NULL; + struct drivers_usb_acpi_config *config; + + xhci = pcidev_path_on_root(PCH_DEVFN_XHCI); + if (!xhci) { + printk(BIOS_ERR, "%s: Could not locate XHCI device in DT\n", __func__); + return; + } + + while ((hub = dev_bus_each_child(xhci->link_list, hub)) != NULL) { + while ((port = dev_bus_each_child(hub->link_list, port)) != NULL) { + if (!port->chip_info || port->path.usb.port_id != LTE_USB_PORT_ID) + continue; + + if (!fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_LTE_HDMI))) + continue; + + config = port->chip_info; + config->type = UPC_TYPE_INTERNAL; + if (port->path.usb.port_type == LTE_USB_PORT_TYPE) { + config->has_power_resource = 1; + memcpy(&config->reset_gpio, &lte_reset_gpio, + sizeof(config->reset_gpio)); + config->reset_off_delay_ms = 10; + memcpy(&config->enable_gpio, &lte_enable_gpio, + sizeof(config->enable_gpio)); + config->enable_delay_ms = 20; + } + } + } +} + +void variant_devtree_update(void) +{ + update_xhci_devtree(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/52960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ad5a1670adef54075923cf912fb41a1ce776155 Gerrit-Change-Number: 52960 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: Add a variant callback to update devicetree config
by Karthik Ramasubramanian (Code Review) 06 May '21

06 May '21

Attention is currently required from: David Wu. Karthik Ramasubramanian has uploaded a new patch set (#3) to the change originally created by David Wu. ( https://review.coreboot.org/c/coreboot/+/52887 ) Change subject: mb/google/dedede: Add a variant callback to update devicetree config ...................................................................... mb/google/dedede: Add a variant callback to update devicetree config This callback is required to update the devicetree config at run-time after probing the firmware config. BUG=b:186380807 BRANCH=dedede TEST=Build and boot to OS in metaknight. Change-Id: I857211bfc4beb36ab225f3786c1707336a34aae9 Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/dedede/mainboard.c M src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/52887/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/52887 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I857211bfc4beb36ab225f3786c1707336a34aae9 Gerrit-Change-Number: 52887 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias pads
by Tim Wawrzynczak (Code Review) 06 May '21

06 May '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51649 ) Change subject: soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias pads ...................................................................... soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias pads TGL boards using the Type-C subsystem for USB Type-C ports without a retimer attached may require a DC bias on the aux lines for certain modes to work. This patch adds native coreboot support for programming the IOM to handle this DC bias via a simple devicetree setting. Previously a UPD was required to tell the FSP which GPIOs were used for the pullup and pulldown biases, but the API for this UPD was effectively undocumented. BUG=b:174116646 TEST=Verified on volteer2 that a Type-C flash drive is enumerated succesfully on all ports. Verified all major power flows (boot, reboot, powerdown and S0ix/suspend) still work as expected. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I70e36a41e760f4a435511c147cc5744a77dbccc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51649 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/volteer/variants/eldrid/overridetree.cb M src/mainboard/google/volteer/variants/elemi/overridetree.cb M src/mainboard/google/volteer/variants/lindar/overridetree.cb M src/mainboard/google/volteer/variants/malefor/overridetree.cb M src/mainboard/google/volteer/variants/voema/overridetree.cb M src/mainboard/google/volteer/variants/volteer/overridetree.cb M src/mainboard/google/volteer/variants/volteer2/overridetree.cb M src/soc/intel/common/block/include/intelblocks/tcss.h M src/soc/intel/common/block/tcss/tcss.c M src/soc/intel/tigerlake/Makefile.inc M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c A src/soc/intel/tigerlake/include/soc/tcss.h 13 files changed, 86 insertions(+), 31 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb index ed157559..f64370a 100644 --- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -15,8 +15,8 @@ register "TcssAuxOri" = "1" register "DdiPort1Hpd" = "0" register "DdiPort2Hpd" = "0" - register "IomTypeCPortPadCfg[0]" = "0x090E000A" - register "IomTypeCPortPadCfg[1]" = "0x090E000D" + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E10, .pad_auxn_dc = GPP_E13}" + #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ diff --git a/src/mainboard/google/volteer/variants/elemi/overridetree.cb b/src/mainboard/google/volteer/variants/elemi/overridetree.cb index 5aba269..ae73246 100644 --- a/src/mainboard/google/volteer/variants/elemi/overridetree.cb +++ b/src/mainboard/google/volteer/variants/elemi/overridetree.cb @@ -3,8 +3,7 @@ register "TcssAuxOri" = "1" register "DdiPort1Hpd" = "0" register "DdiPort2Hpd" = "0" - register "IomTypeCPortPadCfg[0]" = "0x090E000A" - register "IomTypeCPortPadCfg[1]" = "0x090E000D" + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E10, .pad_auxn_dc = GPP_E13}" # Enable EMMC PCIE 5 using clk 5 register "PcieRpEnable[4]" = "1" diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb index 5edd6db..8274531 100644 --- a/src/mainboard/google/volteer/variants/lindar/overridetree.cb +++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb @@ -2,8 +2,8 @@ register "DdiPort1Hpd" = "0" register "DdiPort2Hpd" = "0" register "TcssAuxOri" = "1" - register "IomTypeCPortPadCfg[0]" = "0x090E000A" - register "IomTypeCPortPadCfg[1]" = "0x090E000D" + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E10, .pad_auxn_dc = GPP_E13}" + # USB Port Config register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-A / Type-C C1 diff --git a/src/mainboard/google/volteer/variants/malefor/overridetree.cb b/src/mainboard/google/volteer/variants/malefor/overridetree.cb index 00d609f..0d25df8 100644 --- a/src/mainboard/google/volteer/variants/malefor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/malefor/overridetree.cb @@ -12,8 +12,7 @@ register "SaGv" = "SaGv_Disabled" register "TcssAuxOri" = "1" - register "IomTypeCPortPadCfg[0]" = "0x090E000A" - register "IomTypeCPortPadCfg[1]" = "0x090E000D" + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E10, .pad_auxn_dc = GPP_E13}" # I2C Port Config register "SerialIoI2cMode" = "{ diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb index 86b71ee..32f1a53 100644 --- a/src/mainboard/google/volteer/variants/voema/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb @@ -9,8 +9,7 @@ register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-A / Type-C Port 0 register "TcssAuxOri" = "1" - register "IomTypeCPortPadCfg[0]" = "0x090E000A" - register "IomTypeCPortPadCfg[1]" = "0x090E000D" + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E10, .pad_auxn_dc = GPP_E13}" # Disable WLAN PCIE 7 register "PcieRpEnable[6]" = "0" diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index bce953b..786ac02 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -44,8 +44,7 @@ }, }" register "TcssAuxOri" = "1" - register "IomTypeCPortPadCfg[0]" = "0x090E000A" - register "IomTypeCPortPadCfg[1]" = "0x090E000D" + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E10, .pad_auxn_dc = GPP_E13}" register "HybridStorageMode" = "1" diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index 635a310..4e8302a 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -1,7 +1,6 @@ chip soc/intel/tigerlake register "TcssAuxOri" = "1" - register "IomTypeCPortPadCfg[0]" = "0x090E000A" - register "IomTypeCPortPadCfg[1]" = "0x090E000D" + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E10, .pad_auxn_dc = GPP_E13}" register "DdiPort1Hpd" = "0" register "DdiPort2Hpd" = "0" #+-------------------+---------------------------+ diff --git a/src/soc/intel/common/block/include/intelblocks/tcss.h b/src/soc/intel/common/block/include/intelblocks/tcss.h index 68e279c..29093d1 100644 --- a/src/soc/intel/common/block/include/intelblocks/tcss.h +++ b/src/soc/intel/common/block/include/intelblocks/tcss.h @@ -3,6 +3,8 @@ #ifndef _TCSS_H_ #define _TCSS_H_ +#include <intelblocks/gpio.h> + /* PMC IPC related offsets and commands */ #define PMC_IPC_USBC_CMD_ID 0xA7 #define PMC_IPC_USBC_SUBCMD_ID 0x0 @@ -136,7 +138,17 @@ uint8_t usb3_port; /* USB3 Port Number */ }; -void tcss_configure(void); +struct typec_aux_bias_pads { + gpio_t pad_auxn_dc; + gpio_t pad_auxp_dc; +}; + +/* + * 1) Initialize TCSS muxes to disconnected state + * 2) Configure GPIO pads to provide DC Bias on AUX signals + * 3) Detect DP-over-Type-C alternate mode + */ +void tcss_configure(const struct typec_aux_bias_pads pads[MAX_TYPE_C_PORTS]); /* * Mainboard method to setup any mux config needed for TCSS display operations. diff --git a/src/soc/intel/common/block/tcss/tcss.c b/src/soc/intel/common/block/tcss/tcss.c index 6d1f3af..da19954 100644 --- a/src/soc/intel/common/block/tcss/tcss.c +++ b/src/soc/intel/common/block/tcss/tcss.c @@ -4,12 +4,18 @@ #include <console/console.h> #include <device/pci.h> #include <intelblocks/pmc_ipc.h> +#include <intelblocks/systemagent.h> #include <intelblocks/tcss.h> #include <inttypes.h> #include <security/vboot/vboot_common.h> #include <soc/pci_devs.h> +#include <soc/pcr_ids.h> +#include <soc/tcss.h> #include <stdlib.h> +#define BIAS_CTRL_VW_INDEX_SHIFT 16 +#define BIAS_CTRL_BIT_POS_SHIFT 8 + static uint32_t tcss_make_conn_cmd(int u, int u3, int u2, int ufp, int hsl, int sbu, int acc) { @@ -307,7 +313,32 @@ } } -void tcss_configure(void) +static uint32_t calc_bias_ctrl_reg_value(gpio_t pad) +{ + unsigned int vw_index, vw_bit; + const unsigned int cpu_pid = gpio_get_pad_cpu_portid(pad); + if (!gpio_get_vw_info(pad, &vw_index, &vw_bit) || !cpu_pid) + return 0; + + return vw_index << BIAS_CTRL_VW_INDEX_SHIFT | + vw_bit << BIAS_CTRL_BIT_POS_SHIFT | + cpu_pid; +} + +static void tcss_configure_aux_bias_pads( + const struct typec_aux_bias_pads pads[MAX_TYPE_C_PORTS]) +{ + for (size_t i = 0; i < MAX_TYPE_C_PORTS; i++) { + if (pads[i].pad_auxn_dc && pads[i].pad_auxp_dc) { + REGBAR32(PID_IOM, IOM_AUX_BIAS_CTRL_PULLUP_OFFSET(i)) = + calc_bias_ctrl_reg_value(pads[i].pad_auxp_dc); + REGBAR32(PID_IOM, IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET(i)) = + calc_bias_ctrl_reg_value(pads[i].pad_auxn_dc); + } + } +} + +void tcss_configure(const struct typec_aux_bias_pads aux_bias_pads[MAX_TYPE_C_PORTS]) { const struct tcss_port_map *port_map; size_t num_ports; @@ -320,6 +351,9 @@ for (i = 0; i < num_ports; i++) tcss_init_mux(i, &port_map[i]); + /* This should be performed before alternate modes are entered */ + tcss_configure_aux_bias_pads(aux_bias_pads); + if (CONFIG(ENABLE_TCSS_DISPLAY_DETECTION)) tcss_configure_dp_mode(port_map, num_ports); } diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index ae6101d..787aa05 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -37,12 +37,12 @@ ramstage-y += fsp_params.c ramstage-y += gpio.c ramstage-y += lockdown.c +ramstage-y += me.c ramstage-y += p2sb.c ramstage-y += pmc.c ramstage-y += reset.c ramstage-y += soundwire.c ramstage-y += systemagent.c -ramstage-y += me.c ramstage-y += xhci.c ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog_lib.c diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 8c902c3..c011093 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -9,6 +9,7 @@ #include <intelblocks/gspi.h> #include <intelblocks/pcie_rp.h> #include <intelblocks/power_limit.h> +#include <intelblocks/tcss.h> #include <soc/gpe.h> #include <soc/gpio.h> #include <soc/pch.h> @@ -335,17 +336,14 @@ uint8_t UsbTcPortEn; /* - * IOM Port Config - * If a port orientation needs to be controlled by the SOC this setting must be - * updated to reflect the correct GPIOs being used for the SOC port flipping. - * There are 4 ports each with a pair of GPIOs for Pull Up and Pull Down - * 0,1 are pull up and pull down for port 0 - * 2,3 are pull up and pull down for port 1 - * 4,5 are pull up and pull down for port 2 - * 6,7 are pull up and pull down for port 3 - * values to be programmed correspond to the GPIO family and offsets + * These GPIOs will be programmed by the IOM to handle biasing of the + * Type-C aux (SBU) signals when certain alternate modes are used. + * `pad_auxn_dc` should be assigned to the GPIO pad providing negative + * bias (name usually contains `AUXN_DC` or `AUX_N`); similarly, + * `pad_auxp_dc` should be assigned to the GPIO providing positive bias + * (name often contains `AUXP_DC` or `_AUX_P`). */ - uint32_t IomTypeCPortPadCfg[8]; + struct typec_aux_bias_pads typec_aux_bias_pads[MAX_TYPE_C_PORTS]; /* * SOC Aux orientation override: diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 9fbf9bd..1f1f365 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -23,6 +23,7 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/soc_chip.h> +#include <soc/tcss.h> #include <string.h> /* THC assignment definition */ @@ -188,8 +189,9 @@ params->UsbTcPortEn = config->UsbTcPortEn; params->TcssAuxOri = config->TcssAuxOri; - for (i = 0; i < 8; i++) - params->IomTypeCPortPadCfg[i] = config->IomTypeCPortPadCfg[i]; + + /* Explicitly clear this field to avoid using defaults */ + memset(params->IomTypeCPortPadCfg, 0, sizeof(params->IomTypeCPortPadCfg)); /* * Set FSPS UPD ITbtConnectTopologyTimeoutInMs with value 0. FSP will @@ -460,8 +462,10 @@ printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n", __FILE__, __func__); - if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS)) - tcss_configure(); + if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS)) { + const config_t *config = config_of_soc(); + tcss_configure(config->typec_aux_bias_pads); + } break; default: break; diff --git a/src/soc/intel/tigerlake/include/soc/tcss.h b/src/soc/intel/tigerlake/include/soc/tcss.h new file mode 100644 index 0000000..713528b --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/tcss.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _SOC_TCSS_H_ +#define _SOC_TCSS_H_ + +/* IOM aux bias control registers in REGBAR MMIO space */ +#define IOM_AUX_BIAS_CTRL_PULLUP_OFFSET_0 0x1070 +#define IOM_AUX_BIAS_CTRL_PULLUP_OFFSET(x) (IOM_AUX_BIAS_CTRL_PULLUP_OFFSET_0 + (x) * 4) +#define IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET_0 0x1088 +#define IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET(x) (IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET_0 + (x) * 4) + +#endif /* _SOC_TCSS_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/51649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70e36a41e760f4a435511c147cc5744a77dbccc0 Gerrit-Change-Number: 51649 Gerrit-PatchSet: 24 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/tigkerlake: Add IOM PCR PID
by Tim Wawrzynczak (Code Review) 06 May '21

06 May '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52592 ) Change subject: soc/intel/tigkerlake: Add IOM PCR PID ...................................................................... soc/intel/tigkerlake: Add IOM PCR PID Required for accessing IOM REGBAR space. Change-Id: Ic1c9beee69d184388f3e850744b3aeebe38eafbb Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52592 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/tigerlake/include/soc/pcr_ids.h 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/intel/tigerlake/include/soc/pcr_ids.h b/src/soc/intel/tigerlake/include/soc/pcr_ids.h index 03d36bf..c5d8862 100644 --- a/src/soc/intel/tigerlake/include/soc/pcr_ids.h +++ b/src/soc/intel/tigerlake/include/soc/pcr_ids.h @@ -26,6 +26,7 @@ #define PID_PSF3 0xbc #define PID_PSF4 0xbd #define PID_SCS 0xc0 +#define PID_IOM 0xc1 #define PID_RTC 0xc3 #define PID_ITSS 0xc4 #define PID_ESPI 0xc7 -- To view, visit https://review.coreboot.org/c/coreboot/+/52592 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1c9beee69d184388f3e850744b3aeebe38eafbb Gerrit-Change-Number: 52592 Gerrit-PatchSet: 5 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit May 2021