coreboot-gerrit May 2021

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Change in coreboot[master]: soc/amd{common,cezanne}: Move pcie_gpp.c to common
by Raul Rangel (Code Review) 10 May '21

10 May '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54026 ) Change subject: soc/amd{common,cezanne}: Move pcie_gpp.c to common ...................................................................... soc/amd{common,cezanne}: Move pcie_gpp.c to common Cezanne and Picasso can now use the same driver. BUG=b:184766519 TEST=Boot guybrush and dump ASL. Verified it didn't change. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ie4ede82935d6c69b323c1fdceaa61e306aa2820a --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/common/block/pci/Kconfig M src/soc/amd/common/block/pci/Makefile.inc R src/soc/amd/common/block/pci/pcie_gpp.c 5 files changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/54026/1 diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 51bc4bc..327ec12 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -50,6 +50,7 @@ select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_PCI_MMCONF + select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER select SOC_AMD_COMMON_BLOCK_PM select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE select SOC_AMD_COMMON_BLOCK_PSP_GEN2 diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 7053960..4731dc5 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -39,7 +39,6 @@ ramstage-y += fch.c ramstage-y += fsp_s_params.c ramstage-y += gpio.c -ramstage-y += pcie_gpp.c ramstage-y += reset.c ramstage-y += root_complex.c ramstage-y += uart.c diff --git a/src/soc/amd/common/block/pci/Kconfig b/src/soc/amd/common/block/pci/Kconfig index 4af0aa0..302a6b8 100644 --- a/src/soc/amd/common/block/pci/Kconfig +++ b/src/soc/amd/common/block/pci/Kconfig @@ -10,3 +10,9 @@ help Selecting this option adds the AMD-common enable_pci_mmconf function to the build. + +config SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER + bool + depends on SOC_AMD_COMMON_BLOCK_PCI + help + Select this option to use AMD common PCIe GPP driver. diff --git a/src/soc/amd/common/block/pci/Makefile.inc b/src/soc/amd/common/block/pci/Makefile.inc index 8c7a989..e013777 100644 --- a/src/soc/amd/common/block/pci/Makefile.inc +++ b/src/soc/amd/common/block/pci/Makefile.inc @@ -3,6 +3,7 @@ ramstage-y += amd_pci_util.c ramstage-y += pci_routing_info.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_prt.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER) += pcie_gpp.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_PCI diff --git a/src/soc/amd/cezanne/pcie_gpp.c b/src/soc/amd/common/block/pci/pcie_gpp.c similarity index 100% rename from src/soc/amd/cezanne/pcie_gpp.c rename to src/soc/amd/common/block/pci/pcie_gpp.c -- To view, visit https://review.coreboot.org/c/coreboot/+/54026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4ede82935d6c69b323c1fdceaa61e306aa2820a Gerrit-Change-Number: 54026 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [NOT FOR MERGE] nb/intel/gm45: Make DDR2 raminit work
by Angel Pons (Code Review) 10 May '21

10 May '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54024 ) Change subject: [NOT FOR MERGE] nb/intel/gm45: Make DDR2 raminit work ...................................................................... [NOT FOR MERGE] nb/intel/gm45: Make DDR2 raminit work List of changes: - Update some timing and ODT values - Patch RCOMP calibration to better match what MRC binaries do - Replay a hardcoded list of RCOMP codes after RcvEn This makes raminit work at DDR2-800 speeds and fixes S3 resume as well. Tested on Toshiba Satellite A300-1ME with two 2 GiB DDR2-800 SO-DIMMs. Change-Id: Ibaee524b8ff652ddadd66cb0eb680401b988ff7c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/gm45/gm45.h M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/gm45/raminit_rcomp_calibration.c M src/northbridge/intel/gm45/raminit_receive_enable_calibration.c 4 files changed, 107 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/54024/1 diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index f28c6d1..bdf0432 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -419,7 +419,7 @@ int raminit_read_vco_index(void); u32 raminit_get_rank_addr(unsigned int channel, unsigned int rank); -void raminit_rcomp_calibration(stepping_t stepping); +void raminit_rcomp_calibration(int ddr_type, stepping_t stepping); void raminit_reset_readwrite_pointers(void); void raminit_receive_enable_calibration(int ddr_type, const timings_t *, const dimminfo_t *); void raminit_write_training(const mem_clock_t, const dimminfo_t *, int s3resume); diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index ecada7b..2b8c44e 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -1049,7 +1049,7 @@ } /* Perform RCOMP calibration for DDR3. */ - raminit_rcomp_calibration(stepping); + raminit_rcomp_calibration(spd_type, stepping); /* Run initial RCOMP. */ mchbar_setbits32(0x418, 1 << 17); @@ -1119,7 +1119,7 @@ reg = (reg & ~(0xf << 10)) | (2 << 10); else reg = (reg & ~(0xf << 10)) | (3 << 10); - reg = (reg & ~(0x7 << 5)) | (3 << 5); + reg = (reg & ~(0x7 << 5)) | (2 << 5); } else if (timings->mem_clock != MEM_CLOCK_1067MT) { reg = (reg & ~(0x7 << 15)) | ((9 - timings->CAS) << 15); reg = (reg & ~(0xf << 10)) | ((timings->CAS - 3) << 10); @@ -1288,11 +1288,11 @@ reg = (reg & ~(0xf << (44 - 32))) | (8 << (44 - 32)); reg = (reg & ~(0xf << (40 - 32))) | (7 << (40 - 32)); if (timings->mem_clock == MEM_CLOCK_667MT) { - reg = (reg & ~(0xf << (36 - 32))) | (4 << (36 - 32)); - reg = (reg & ~(0xf << (32 - 32))) | (4 << (32 - 32)); + reg = (reg & ~(0xf << (36 - 32))) | (8 << (36 - 32)); + reg = (reg & ~(0xf << (32 - 32))) | (8 << (32 - 32)); } else { - reg = (reg & ~(0xf << (36 - 32))) | (5 << (36 - 32)); - reg = (reg & ~(0xf << (32 - 32))) | (5 << (32 - 32)); + reg = (reg & ~(0xf << (36 - 32))) | (9 << (36 - 32)); + reg = (reg & ~(0xf << (32 - 32))) | (9 << (32 - 32)); } mchbar_write32(CxODT_HIGH(ch), reg); @@ -2217,6 +2217,84 @@ raminit_write_training(timings->mem_clock, dimms, s3resume); } + /* + * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done + * after receiver enable calibration, otherwise raminit sometimes + * completes with non-working memory. + */ + mchbar_write32(0x0530, 0x06060005); + mchbar_write32(0x0680, 0x06060606); + mchbar_write32(0x0684, 0x08070606); + mchbar_write32(0x0688, 0x0e0e0c0a); + mchbar_write32(0x068c, 0x0e0e0e0e); + mchbar_write32(0x0698, 0x06060606); + mchbar_write32(0x069c, 0x08070606); + mchbar_write32(0x06a0, 0x0c0c0b0a); + mchbar_write32(0x06a4, 0x0c0c0c0c); + + mchbar_write32(0x06c0, 0x02020202); + mchbar_write32(0x06c4, 0x03020202); + mchbar_write32(0x06c8, 0x04040403); + mchbar_write32(0x06cc, 0x04040404); + mchbar_write32(0x06d8, 0x02020202); + mchbar_write32(0x06dc, 0x03020202); + mchbar_write32(0x06e0, 0x04040403); + mchbar_write32(0x06e4, 0x04040404); + + mchbar_write32(0x0700, 0x02020202); + mchbar_write32(0x0704, 0x03020202); + mchbar_write32(0x0708, 0x04040403); + mchbar_write32(0x070c, 0x04040404); + mchbar_write32(0x0718, 0x02020202); + mchbar_write32(0x071c, 0x03020202); + mchbar_write32(0x0720, 0x04040403); + mchbar_write32(0x0724, 0x04040404); + + mchbar_write32(0x0740, 0x02020202); + mchbar_write32(0x0744, 0x03020202); + mchbar_write32(0x0748, 0x04040403); + mchbar_write32(0x074c, 0x04040404); + mchbar_write32(0x0758, 0x02020202); + mchbar_write32(0x075c, 0x03020202); + mchbar_write32(0x0760, 0x04040403); + mchbar_write32(0x0764, 0x04040404); + + mchbar_write32(0x0780, 0x06060606); + mchbar_write32(0x0784, 0x09070606); + mchbar_write32(0x0788, 0x0e0e0c0b); + mchbar_write32(0x078c, 0x0e0e0e0e); + mchbar_write32(0x0798, 0x06060606); + mchbar_write32(0x079c, 0x09070606); + mchbar_write32(0x07a0, 0x0d0d0c0b); + mchbar_write32(0x07a4, 0x0d0d0d0d); + + mchbar_write32(0x07c0, 0x06060606); + mchbar_write32(0x07c4, 0x09070606); + mchbar_write32(0x07c8, 0x0e0e0c0b); + mchbar_write32(0x07cc, 0x0e0e0e0e); + mchbar_write32(0x07d8, 0x06060606); + mchbar_write32(0x07dc, 0x09070606); + mchbar_write32(0x07e0, 0x0d0d0c0b); + mchbar_write32(0x07e4, 0x0d0d0d0d); + + mchbar_write32(0x0840, 0x06060606); + mchbar_write32(0x0844, 0x08070606); + mchbar_write32(0x0848, 0x0e0e0c0a); + mchbar_write32(0x084c, 0x0e0e0e0e); + mchbar_write32(0x0858, 0x06060606); + mchbar_write32(0x085c, 0x08070606); + mchbar_write32(0x0860, 0x0c0c0b0a); + mchbar_write32(0x0864, 0x0c0c0c0c); + + mchbar_write32(0x0880, 0x02020202); + mchbar_write32(0x0884, 0x03020202); + mchbar_write32(0x0888, 0x04040403); + mchbar_write32(0x088c, 0x04040404); + mchbar_write32(0x0898, 0x02020202); + mchbar_write32(0x089c, 0x03020202); + mchbar_write32(0x08a0, 0x04040403); + mchbar_write32(0x08a4, 0x04040404); + igd_compute_ggc(sysinfo); /* Program final memory map (with real values). */ diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c index aef863f..b74765f 100644 --- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c +++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c @@ -161,11 +161,13 @@ mchbar += 4; } } -void raminit_rcomp_calibration(const stepping_t stepping) { +void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) { const int a1step = stepping >= STEPPING_CONVERSION_A1; int i; + char magic_comp[2] = {0}; + enum { PULL_UP = 0, PULL_DOWN = 1, @@ -196,6 +198,10 @@ reg = mchbar_read32(0x518); lut_idx[channel][group][PULL_UP] = (reg >> 24) & 0x7f; lut_idx[channel][group][PULL_DOWN] = (reg >> 16) & 0x7f; + if (i == 1) { + magic_comp[0] = (reg >> 8) & 0x3f; + magic_comp[1] = (reg >> 0) & 0x3f; + } } /* Cleanup? */ mchbar_setbits32(0x400, 1 << 3); @@ -216,13 +222,19 @@ for (channel = 0; channel < 2; ++channel) { for (group = 0; group < 6; ++group) { for (pu_pd = PULL_DOWN; pu_pd >= PULL_UP; --pu_pd) { - lookup_and_write( - a1step, - lut_idx[channel][group][pu_pd] - 7, - ddr3_lookup_schedule[group][pu_pd], - mchbar); + if (ddr_type == DDR3) { + lookup_and_write( + a1step, + lut_idx[channel][group][pu_pd] - 7, + ddr3_lookup_schedule[group][pu_pd], + mchbar); + } mchbar += 0x0018; } + if (ddr_type == DDR2) { + mchbar_clrsetbits32(mchbar + 0, 0x7f << 24, lut_idx[channel][group][PULL_DOWN] << 24); + mchbar_clrsetbits32(mchbar + 4, 0x7f << 0, lut_idx[channel][group][PULL_UP] << 0); + } mchbar += 0x0010; /* Channel B knows only the first two groups. */ if ((1 == channel) && (1 == group)) @@ -230,4 +242,7 @@ } mchbar += 0x0040; } + + mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26); + mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20); } diff --git a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c index 75ecec2..9e026b3 100644 --- a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c +++ b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c @@ -203,7 +203,7 @@ const unsigned int t_bound = (timings->mem_clock == MEM_CLOCK_1067MT) ? 9 : (ddr_type == DDR3) ? 12 - : 15; + : 12; const unsigned int p_bound = (timings->mem_clock == MEM_CLOCK_1067MT) ? 8 : 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/54024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibaee524b8ff652ddadd66cb0eb680401b988ff7c Gerrit-Change-Number: 54024 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/adlrvp_m: Enable CR50 TPM support over SPI
by Thejaswani Putta (Code Review) 10 May '21

10 May '21

Thejaswani Putta has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54023 ) Change subject: mb/intel/adlrvp_m: Enable CR50 TPM support over SPI ...................................................................... mb/intel/adlrvp_m: Enable CR50 TPM support over SPI Add Kconfig options and enable TPM device in devicetree BUG: SYSCROS-57029 TEST:Booted the image and checked the successful TPM communication in verstage,romstage & ramstage from Coreboot logs. Signed-off-by: Thejaswani Puta thejaswani.putta(a)intel.com <thejaswani.putta(a)intel.com> Change-Id: Icaedf9f17e35e82c35cbabd6d2938c167e42e9e8 --- M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/adlrvp/devicetree_m.cb M src/mainboard/intel/adlrvp/early_gpio_m.c M src/mainboard/intel/adlrvp/gpio_m.c 4 files changed, 45 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/54023/1 diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index ce5665c..d807a0a 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -19,6 +19,9 @@ select HAVE_SPD_IN_CBFS select DRIVERS_SOUNDWIRE_ALC711 select SOC_INTEL_CSE_LITE_SKU + select MAINBOARD_HAS_TPM2 + select MAINBOARD_HAS_SPI_TPM_CR50 + select SPI_TPM config CHROMEOS select GBB_FLAG_FORCE_DEV_SWITCH_ON @@ -96,4 +99,11 @@ config UART_FOR_CONSOLE int default 0 + +config DRIVER_TPM_SPI_BUS + default 0x2 + +config TPM_TIS_ACPI_INTERRUPT + int + default 67 # GPE0_DW2_3 (GPP_E3) endif diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index 51d97bc..1e57e10 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -4,6 +4,15 @@ device lapic 0 on end end + # This disables autonomous GPIO power management, otherwise + # old cr50 FW only supports short pulses. + register "gpio_override_pm" = "1" + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_4]" = "0" + register "gpio_pm[COMM_5]" = "0" + # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE @@ -97,14 +106,14 @@ register "SerialIoGSpiMode" = "{ [PchSerialIoIndexGSPI0] = PchSerialIoPci, - [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, }" register "SerialIoGSpiCsMode" = "{ [PchSerialIoIndexGSPI0] = 0, - [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI1] = 1, [PchSerialIoIndexGSPI2] = 0, [PchSerialIoIndexGSPI3] = 0, }" @@ -131,6 +140,10 @@ # Intel Common SoC Config register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[1] = { + .speed_mhz = 1, + .early_init = 1, + }, .i2c[0] = { .speed = I2C_SPEED_FAST, }, @@ -233,7 +246,14 @@ device pci 1e.0 on end # UART0 device pci 1e.1 off end # UART1 device pci 1e.2 on end # GSPI0 - device pci 1e.3 off end # GSPI1 + device pci 1e.3 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E3_IRQ)" + device spi 0 on end + end + end # GSPI1 device pci 1f.0 on end # eSPI device pci 1f.1 on end # P2SB device pci 1f.2 hidden end # PMC diff --git a/src/mainboard/intel/adlrvp/early_gpio_m.c b/src/mainboard/intel/adlrvp/early_gpio_m.c index 116d3c6..24b8980 100644 --- a/src/mainboard/intel/adlrvp/early_gpio_m.c +++ b/src/mainboard/intel/adlrvp/early_gpio_m.c @@ -11,6 +11,17 @@ PAD_CFG_GPO(GPP_E5, 0, PLTRST), /* WWAN_PWR_EN */ PAD_CFG_GPO(GPP_A8, 1, DEEP), + /* H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, INVERT), + /* TPM */ + /* F16 : GSPI1_CS0N */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4), + /* F11 : GSPI1_CLK */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4), + /* F13 : GSPI1_MISO */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4), + /* F12 : GSPI1_MOSI */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4), }; static const struct pad_config early_uart_gpio_table[] = { diff --git a/src/mainboard/intel/adlrvp/gpio_m.c b/src/mainboard/intel/adlrvp/gpio_m.c index 6f89fd2..85d6ccf 100644 --- a/src/mainboard/intel/adlrvp/gpio_m.c +++ b/src/mainboard/intel/adlrvp/gpio_m.c @@ -157,7 +157,7 @@ PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* S7 : SNDW4_DATA */ - PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2) + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), }; void variant_configure_gpio_pads(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/54023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icaedf9f17e35e82c35cbabd6d2938c167e42e9e8 Gerrit-Change-Number: 54023 Gerrit-PatchSet: 1 Gerrit-Owner: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation/releases: Fill in coreboot 4.14 release notes
by Patrick Georgi (Code Review) 10 May '21

10 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54003 ) Change subject: Documentation/releases: Fill in coreboot 4.14 release notes ...................................................................... Documentation/releases: Fill in coreboot 4.14 release notes Change-Id: I79530c91424112247e485a5a41debc666e0072d4 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54003 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Documentation/releases/coreboot-4.14-relnotes.md 1 file changed, 67 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/Documentation/releases/coreboot-4.14-relnotes.md b/Documentation/releases/coreboot-4.14-relnotes.md index 3593bdc..40589a1 100644 --- a/Documentation/releases/coreboot-4.14-relnotes.md +++ b/Documentation/releases/coreboot-4.14-relnotes.md @@ -1,14 +1,73 @@ -Upcoming release - coreboot 4.14 -================================ +coreboot 4.14 +============= -The 4.14 release is planned for May 2021. +coreboot 4.14 was released on May 10th, 2021. -Update this document with changes that should be in the release notes. +Since 4.13 there have been 3660 new commits by 215 developers. +Of these, about 50 contributed to coreboot for the first time. +Welcome to the project! -* Please use Markdown. -* See the past few release notes for the general format. -* The chip and board additions and removals will be updated right - before the release, so those do not need to be added. +These changes have been all over the place, so that there's no +particular area to focus on when describing this release: We had +improvements to mainboards, to chipsets (including much welcomed +work to open source implementations of what has been blobs before), +to the overall architecture. + +Thank you to all developers who made coreboot the great open source +firmware project that it is, and made our code better than ever. + +New mainboards +-------------- + +* AMD Bilby +* AMD Majolica +* GIGABYTE GA-D510UD +* Google Blipper +* Google Brya +* Google Cherry +* Google Collis +* Google Copano +* Google Cozmo +* Google Cret +* Google Drobit +* Google Galtic +* Google Gumboz +* Google Guybrush +* Google Herobrine +* Google Homestar +* Google Katsu +* Google Kracko +* Google Lalala +* Google Makomo +* Google Mancomb +* Google Marzipan +* Google Pirika +* Google Sasuke +* Google Sasukette +* Google Spherion +* Google Storo +* Google Volet +* HP 280 G2 +* Intel Alderlake-M RVP +* Intel Alderlake-M RVP with Chrome EC +* Intel Elkhartlake LPDDR4x CRB +* Intel shadowmountain +* Kontron COMe-mAL10 +* MSI H81M-P33 (MS-7817 v1.2) +* Pine64 ROCKPro64 +* Purism Librem 14 +* System76 darp5 +* System76 galp3-c +* System76 gaze15 +* System76 oryp5 +* System76 oryp6 + +Removed mainboards +------------------ + +* Google Boldar +* Intel Cannonlake U LPDDR4 RVP +* Intel Cannonlake Y LPDDR4 RVP Deprecations and incompatible changes ------------------------------------- @@ -95,7 +154,6 @@ Features supported, (performance/stability) test scopes, known issues, features gaps are described in [4]. -### Add significant changes here [1] https://www.intel.com/content/www/us/en/products/details/processors/xeon/sc… [2] https://www.intel.com/content/www/us/en/products/docs/processors/xeon/3rd-g… -- To view, visit https://review.coreboot.org/c/coreboot/+/54003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79530c91424112247e485a5a41debc666e0072d4 Gerrit-Change-Number: 54003 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/x86/smm: Fix typo
by Patrick Georgi (Code Review) 10 May '21

10 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53926 ) Change subject: cpu/x86/smm: Fix typo ...................................................................... cpu/x86/smm: Fix typo Change-Id: I28f262078cf7f5ec4ed707639e845710a8cc56ea Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53926 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/x86/smm/smm_stub.S 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index 28b7d57..0c690da 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -97,7 +97,7 @@ movw %ax, %gs /* The CPU number is calculated by reading the initial APIC id. Since - * the OS can maniuplate the APIC id use the non-changing cpuid result + * the OS can manipulate the APIC id use the non-changing cpuid result * for APIC id (eax). A table is used to handle a discontiguous * APIC id space. */ apic_id: -- To view, visit https://review.coreboot.org/c/coreboot/+/53926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28f262078cf7f5ec4ed707639e845710a8cc56ea Gerrit-Change-Number: 53926 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/x86/smm: Fix typo
by Patrick Georgi (Code Review) 10 May '21

10 May '21

Attention is currently required from: Paul Menzel. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53926 ) Change subject: cpu/x86/smm: Fix typo ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/53926/comment/29362b0b_ebff252f PS1, Line 7: cpu/x86/smm: Fix typo > That's kinda obvious from the patch, no? Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/53926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28f262078cf7f5ec4ed707639e845710a8cc56ea Gerrit-Change-Number: 53926 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 10 May 2021 20:31:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: *x86: fix x2apic mode boot issue
by Patrick Georgi (Code Review) 10 May '21

10 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52696 ) Change subject: *x86: fix x2apic mode boot issue ...................................................................... *x86: fix x2apic mode boot issue Fix booting issues on google/kahlee introduced by CB:51723. Update use inital apic id in smm_stub.S to support xapic mode error. Check more bits(LAPIC_BASE_MSR BIT10 and BIT11) for x2apic mode. TEST=Boot to OS and check apicid, debug log for CPUIDs cpuid_ebx(1), cpuid_ext(0xb, 0), cpuid_edx(0xb) etc Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: Ia28f60a077182c3753f6ba9fbdd141f951d39b37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52696 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/x86/smm/smm_stub.S M src/include/cpu/x86/lapic.h M src/include/cpu/x86/lapic_def.h 3 files changed, 22 insertions(+), 17 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index f479d62..28b7d57 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -98,28 +98,31 @@ /* The CPU number is calculated by reading the initial APIC id. Since * the OS can maniuplate the APIC id use the non-changing cpuid result - * for APIC id (ax). A table is used to handle a discontiguous + * for APIC id (eax). A table is used to handle a discontiguous * APIC id space. */ apic_id: - mov $LAPIC_BASE_MSR, %ecx - rdmsr - andl $LAPIC_BASE_MSR_X2APIC_MODE, %eax - jz xapic + mov $LAPIC_BASE_MSR, %ecx + rdmsr + and $LAPIC_BASE_X2APIC_ENABLED, %eax + cmp $LAPIC_BASE_X2APIC_ENABLED, %eax + jne xapic x2apic: - mov $X2APIC_LAPIC_ID, %ecx - rdmsr - jmp apicid_end + mov $0xb, %eax + mov $0, %ecx + cpuid + mov %edx, %eax + jmp apicid_end xapic: - movl $(LOCAL_APIC_ADDR | LAPIC_ID), %esi - movl (%esi), %eax - shr $24, %eax + mov $1, %eax + cpuid + mov %ebx, %eax + shr $24, %eax apicid_end: - - mov $(apic_to_cpu_num), %ebx - xor %ecx, %ecx + mov $(apic_to_cpu_num), %ebx + xor %ecx, %ecx 1: cmp (%ebx, %ecx, 2), %ax diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index e2ca297..717fc9a 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -12,7 +12,7 @@ { msr_t msr; msr = rdmsr(LAPIC_BASE_MSR); - return (msr.lo & LAPIC_BASE_MSR_X2APIC_MODE); + return ((msr.lo & LAPIC_BASE_X2APIC_ENABLED) == LAPIC_BASE_X2APIC_ENABLED); } static inline void x2apic_send_ipi(uint32_t icrlow, uint32_t apicid) @@ -79,8 +79,8 @@ static __always_inline unsigned int initial_lapicid(void) { uint32_t lapicid; - if (is_x2apic_mode()) - lapicid = lapic_read(LAPIC_ID); + if (is_x2apic_mode() && cpuid_get_max_func() >= 0xb) + lapicid = cpuid_ext(0xb, 0).edx; else lapicid = cpuid_ebx(1) >> 24; return lapicid; diff --git a/src/include/cpu/x86/lapic_def.h b/src/include/cpu/x86/lapic_def.h index 5b25e5a..d5e863a 100644 --- a/src/include/cpu/x86/lapic_def.h +++ b/src/include/cpu/x86/lapic_def.h @@ -5,6 +5,8 @@ #define LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR (1 << 8) #define LAPIC_BASE_MSR_X2APIC_MODE (1 << 10) #define LAPIC_BASE_MSR_ENABLE (1 << 11) +#define LAPIC_BASE_X2APIC_ENABLED \ + (LAPIC_BASE_MSR_X2APIC_MODE | LAPIC_BASE_MSR_ENABLE) #define LAPIC_BASE_MSR_ADDR_MASK 0xFFFFF000 #ifndef LOCAL_APIC_ADDR -- To view, visit https://review.coreboot.org/c/coreboot/+/52696 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia28f60a077182c3753f6ba9fbdd141f951d39b37 Gerrit-Change-Number: 52696 Gerrit-PatchSet: 6 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: doc/relnotes/4.14: add Intel Xeon-SP support status change
by Patrick Georgi (Code Review) 10 May '21

10 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52735 ) Change subject: doc/relnotes/4.14: add Intel Xeon-SP support status change ...................................................................... doc/relnotes/4.14: add Intel Xeon-SP support status change Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: Ibead1c75bb4e41fedc2799366b5b006d76fc8f4e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52735 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Documentation/releases/coreboot-4.14-relnotes.md 1 file changed, 24 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/Documentation/releases/coreboot-4.14-relnotes.md b/Documentation/releases/coreboot-4.14-relnotes.md index b6c927e..3593bdc 100644 --- a/Documentation/releases/coreboot-4.14-relnotes.md +++ b/Documentation/releases/coreboot-4.14-relnotes.md @@ -76,4 +76,28 @@ for common ACPI GNVS table entries were largely moved to one centralized implementation. +### Intel Xeon Scalable Processor support is now considered mature + +Intel Xeon Scalable Processor (Xeon-SP) family [1] is designed +primarily to serve the needs of the server market. + +coreboot support for Xeon-SP is in src/soc/intel/xeon_sp directory. +This release has support for SkyLake-SP (SKX-SP) which is the 2nd +generation, and for CooperLake-SP (CPX-SP) which is the 3rd generation +or the latest generation [2] on market. + +With this release, the codebase for multiple generations of Xeon-SP +were unified and optimized: +* SKX-SP SoC code is used in OCP TiogaPass mainboard [3]. Support for +this board is in Proof Of Concept Status. +* CPX-SP SoC code is used in OCP DeltaLake mainboard. Support for +this board is in DVT (Design Validation Test) exit equivalent status. +Features supported, (performance/stability) test scopes, known issues, +features gaps are described in [4]. + ### Add significant changes here + +[1] https://www.intel.com/content/www/us/en/products/details/processors/xeon/sc… +[2] https://www.intel.com/content/www/us/en/products/docs/processors/xeon/3rd-g… +[3] ../mainboard/ocp/tiogapass.md +[4] ../mainboard/ocp/deltalake.md -- To view, visit https://review.coreboot.org/c/coreboot/+/52735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibead1c75bb4e41fedc2799366b5b006d76fc8f4e Gerrit-Change-Number: 52735 Gerrit-PatchSet: 8 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/cbfstool: several fixes to build on OpenBSD
by Idwer Vollering (Code Review) 10 May '21

10 May '21

Attention is currently required from: David Hendricks. Idwer Vollering has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54022 ) Change subject: util/cbfstool: several fixes to build on OpenBSD ...................................................................... Patch Set 1: Code-Review-1 (1 comment) Patchset: PS1: This depends on a (pending) change in vboot_reference. -- To view, visit https://review.coreboot.org/c/coreboot/+/54022 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69ca92175abef8d38c7bad2b2e9ed40f5cdd1d32 Gerrit-Change-Number: 54022 Gerrit-PatchSet: 1 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Comment-Date: Mon, 10 May 2021 20:09:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: doc/relnotes/4.14: add Intel Xeon-SP support status change
by Subrata Banik (Code Review) 10 May '21

10 May '21

Attention is currently required from: Marc Jones, Anjaneya "Reddy" Chagam, Jonathan Zhang, Christian Walter, Stefan Reinauer, David Hendricks, ron minnich. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52735 ) Change subject: doc/relnotes/4.14: add Intel Xeon-SP support status change ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibead1c75bb4e41fedc2799366b5b006d76fc8f4e Gerrit-Change-Number: 52735 Gerrit-PatchSet: 7 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Mon, 10 May 2021 20:06:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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