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Change subject: util/cbfstool: several fixes to build on OpenBSD
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> This depends on a (pending) change in vboot_reference.
This depends on vboot_reference: https://chromium-review.googlesource.com/c/chromiumos/platform/vboot_refereā¦
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Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52908 )
Change subject: mb/google/guybrush: Configure wake resource for WiFi
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52908/comment/167fb511_fa5c0ce0
PS1, Line 13: is added to SSDT.
> > At what point did you check it? IIUC, it gets set on the suspend path in kernel. [ā¦]
Performed a rogue experiment of setting the bit corresponding to GEVENT_8 in SMI:event_enable register as part of S0ix entry. With that bit set, I was able to wakeup the system using Wake on WLAN disconnect.
[ 852.973207] rtw_8822ce 0000:01:00.0: Unknown wakeup reason 4
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Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54035 )
Change subject: Doc/nb/intel/sandybridge: Fix up some typos and cosmetics
......................................................................
Doc/nb/intel/sandybridge: Fix up some typos and cosmetics
Change-Id: I23b0c94ec9881aef8e39a14bc048856a65a6286d
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M Documentation/northbridge/intel/sandybridge/index.md
M Documentation/northbridge/intel/sandybridge/nri.md
M Documentation/northbridge/intel/sandybridge/nri_registers.md
3 files changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/54035/1
diff --git a/Documentation/northbridge/intel/sandybridge/index.md b/Documentation/northbridge/intel/sandybridge/index.md
index c1d4b99..27fbb2cc2 100644
--- a/Documentation/northbridge/intel/sandybridge/index.md
+++ b/Documentation/northbridge/intel/sandybridge/index.md
@@ -4,6 +4,6 @@
## Topics
-- [Native Ram Initialization](nri.md)
+- [Native RAM Initialization](nri.md)
- [RAM initialization feature matrix](nri_features.md)
- [ME Cleaner](me_cleaner.md)
diff --git a/Documentation/northbridge/intel/sandybridge/nri.md b/Documentation/northbridge/intel/sandybridge/nri.md
index 812cd23..bf0b89f 100644
--- a/Documentation/northbridge/intel/sandybridge/nri.md
+++ b/Documentation/northbridge/intel/sandybridge/nri.md
@@ -40,7 +40,7 @@
+---------+-------------------------------------------------------------------+------------+--------------+
```
-## (Inoffical) register documentation
+## (Unoffical) register documentation
- [Sandy Bridge - Register documentation](nri_registers.md)
## Frequency selection
@@ -83,7 +83,7 @@
> **Note:** This feature is available since coreboot 4.4
### MRC cache
-The name *MRC cache* might be missleading as in case of *Native ram init*
+The name *MRC cache* might be misleading as in case of *Native RAM init*
there's no MRC, but for historical reasons it's still named *MRC cache*.
The MRC cache is part of flash memory that is writeable by coreboot.
At the end of the boot process coreboot will write the RAM training results to
diff --git a/Documentation/northbridge/intel/sandybridge/nri_registers.md b/Documentation/northbridge/intel/sandybridge/nri_registers.md
index 8f85629..aae1205 100644
--- a/Documentation/northbridge/intel/sandybridge/nri_registers.md
+++ b/Documentation/northbridge/intel/sandybridge/nri_registers.md
@@ -1,9 +1,9 @@
-# Inoffical Documentation of Intel MCHBAR register space.
+# Unofficial Documentation of Intel MCHBAR register space.
The MCHBAR can be enabled by using register 0x48 of PCI(0:0:0) device.
This documentation is incomplete and might be incorrect.
-Please handle with care !
+Please handle with care!
**MCHBAR + 0x4**
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Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54032 )
Change subject: Documentation/releases: Add more details about release notes
......................................................................
Documentation/releases: Add more details about release notes
There are some steps when updating the release notes that are easily
missed (see: I missed them for 4.14), so document them.
Change-Id: Icdb69eb74f8dd3a7189eb8803b0259c4e6a31f96
Signed-off-by: Patrick Georgi <pgeorgi(a)google.com>
---
M Documentation/releases/checklist.md
1 file changed, 4 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/54032/1
diff --git a/Documentation/releases/checklist.md b/Documentation/releases/checklist.md
index 7e66c4d..50d99f6 100644
--- a/Documentation/releases/checklist.md
+++ b/Documentation/releases/checklist.md
@@ -59,8 +59,9 @@
- [ ] If there are any deprecations announced for the following release,
make sure that a list of currently affected boards and chipsets is
part of the release notes.
-- [ ] Finalize release notes (as much as possible), without specifying
- release commit ids.
+- [ ] Finalize release notes as much as possible
+- [ ] Prepare release notes template for following release
+- [ ] Update `Documentation/releases/index.md`
- [ ] Run `util/vboot_list/vboot_list.sh` script to update the list of
boards supported by vboot.
@@ -68,7 +69,7 @@
- [ ] Select a commit ID to base the release upon, announce to IRC,
ask for testing.
- [ ] Test the commit selected for release.
-- [ ] Update release notes with actual commit id, push to repo.
+- [ ] Submit release notes
- [ ] Create new release notes doc template for the next version.
- [ ] Fill in the release date, remove "Upcoming release" and other filler
from the current release notes.
--
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Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54031 )
Change subject: Documentation/releases: Add 4.15 release notes template
......................................................................
Documentation/releases: Add 4.15 release notes template
Change-Id: I52bd1ee6b297ba08e335f5c65941b09f14689a00
Signed-off-by: Patrick Georgi <pgeorgi(a)google.com>
---
A Documentation/releases/coreboot-4.15-relnotes.md
M Documentation/releases/index.md
2 files changed, 18 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/54031/1
diff --git a/Documentation/releases/coreboot-4.15-relnotes.md b/Documentation/releases/coreboot-4.15-relnotes.md
new file mode 100644
index 0000000..6244cf6
--- /dev/null
+++ b/Documentation/releases/coreboot-4.15-relnotes.md
@@ -0,0 +1,16 @@
+Upcoming release - coreboot 4.15
+================================
+
+The 4.15 release is planned for October 2021.
+
+Update this document with changes that should be in the release notes.
+
+* Please use Markdown.
+* See the past few release notes for the general format.
+* The chip and board additions and removals will be updated right
+ before the release, so those do not need to be added.
+
+Significant changes
+-------------------
+
+### Add significant changes here
diff --git a/Documentation/releases/index.md b/Documentation/releases/index.md
index 081d1fc..78ad127 100644
--- a/Documentation/releases/index.md
+++ b/Documentation/releases/index.md
@@ -14,6 +14,7 @@
* [4.11 - November 2019](coreboot-4.11-relnotes.md)
* [4.12 - May 2020](coreboot-4.12-relnotes.md)
* [4.13 - November 2020](coreboot-4.13-relnotes.md)
+* [4.14 - May 2021](coreboot-4.14-relnotes.md)
The checklist contains instructions to ensure that a release covers all
important things and provides a reliable format for tarballs, branch
@@ -25,4 +26,4 @@
----------------
Please add to the release notes as changes are added:
-* [4.14 - May 2021](coreboot-4.14-relnotes.md)
+* [4.15 - October 2021](coreboot-4.15-relnotes.md)
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Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54030 )
Change subject: Documentation/releases: Update checklist
......................................................................
Documentation/releases: Update checklist
Since we want commits to go through 24 hours of review, move the
vboot list update a week earlier. Also point more directly at the
right script to execute.
Change-Id: I49e6dfe22894402d5a0526588f8a04595ac88862
Signed-off-by: Patrick Georgi <pgeorgi(a)google.com>
---
M Documentation/releases/checklist.md
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/54030/1
diff --git a/Documentation/releases/checklist.md b/Documentation/releases/checklist.md
index 3f19bfb..7e66c4d 100644
--- a/Documentation/releases/checklist.md
+++ b/Documentation/releases/checklist.md
@@ -61,6 +61,8 @@
part of the release notes.
- [ ] Finalize release notes (as much as possible), without specifying
release commit ids.
+- [ ] Run `util/vboot_list/vboot_list.sh` script to update the list of
+ boards supported by vboot.
### Day of release
- [ ] Select a commit ID to base the release upon, announce to IRC,
@@ -71,7 +73,6 @@
- [ ] Fill in the release date, remove "Upcoming release" and other filler
from the current release notes.
- [ ] Run release script.
-- [ ] Run vboot_list script.
- [ ] Test the release from the actual release tarballs.
- [ ] Push signed Tag to repo.
- [ ] Announce that the release tag is done on IRC.
--
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Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54019 )
Change subject: payloads/Tianocore: Update default build target, simplify build options
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Intel GM45 and X4X targets don't work with UefiPayloadPkg but do with CorebootPayloadPkg. [ā¦]
do those platforms work with `TIANOCORE_USE_8254_TIMER` selected? If so, could just select that as a default for ones that need it
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