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Change in coreboot[master]: amd/cezanne: adding support for the changed AMD FSP API for USB PHY
by Julian Schroeder (Code Review) 11 May '21

11 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Julian Schroeder has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54065 ) Change subject: amd/cezanne: adding support for the changed AMD FSP API for USB PHY ...................................................................... Patch Set 2: (3 comments) File src/vendorcode/amd/fsp/cezanne/FspUsb.h: https://review.coreboot.org/c/coreboot/+/54065/comment/68be28d2_b23d7c05 PS1, Line 10: #if 0 > ? oops! I have to take this out. https://review.coreboot.org/c/coreboot/+/54065/comment/bcb6de39_a99f2665 PS1, Line 44: compdstune > Is there documentation that could be added to these? Or maybe we can define some enums? This stuff is explained in the USB2 spec and the PPR. I don't think we can explain this properly in a comment. https://review.coreboot.org/c/coreboot/+/54065/comment/748307d1_4cc825c7 PS1, Line 67: > nit: indenting will update the patch in a minute -- To view, visit https://review.coreboot.org/c/coreboot/+/54065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I011ca40a334e4fd26778ca7f18b653298b14019b Gerrit-Change-Number: 54065 Gerrit-PatchSet: 2 Gerrit-Owner: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 11 May 2021 16:20:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: amd/cezanne: adding support for the changed AMD FSP API for USB PHY
by Julian Schroeder (Code Review) 11 May '21

11 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Julian Schroeder, Felix Held. Hello Jason Glenesk, Raul Rangel, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54065 to look at the new patch set (#2). Change subject: amd/cezanne: adding support for the changed AMD FSP API for USB PHY ...................................................................... amd/cezanne: adding support for the changed AMD FSP API for USB PHY The AMD FSP is using a new structure for USB and USB C phy settings. This patch removes old, unused structures, adds the new one and enables the devicetree interface for it. Signed-off-by: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Change-Id: I011ca40a334e4fd26778ca7f18b653298b14019b --- M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb M src/soc/amd/cezanne/chip.h M src/soc/amd/cezanne/fsp_m_params.c A src/vendorcode/amd/fsp/cezanne/FspUsb.h M src/vendorcode/amd/fsp/cezanne/FspmUpd.h 5 files changed, 178 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/54065/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I011ca40a334e4fd26778ca7f18b653298b14019b Gerrit-Change-Number: 54065 Gerrit-PatchSet: 2 Gerrit-Owner: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: ec: Add Star Labs ITE 8987E support
by Andy Pont (Code Review) 11 May '21

11 May '21

Attention is currently required from: Star Labs. Andy Pont has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52797 ) Change subject: ec: Add Star Labs ITE 8987E support ...................................................................... Patch Set 8: (3 comments) Patchset: PS8: Found a couple of issues that were missed in the code tidy up. File src/ec/starlabs/it8987/acpi/ec.asl: https://review.coreboot.org/c/coreboot/+/52797/comment/eb16a6e9_c63d2dfb PS8, Line 97: Store (0x03, \_SB.PCI0.GFX0.CLID) This doesn't exist in coreboot, hence being commented out, so we should probably take it out. File src/ec/starlabs/it8987/chip.h: https://review.coreboot.org/c/coreboot/+/52797/comment/b8965378_e5fdbf0e PS8, Line 10: _EC_ITE_IT8987_CHIP_H Oops, comment didn't get corrected when the include guard got changed. -- To view, visit https://review.coreboot.org/c/coreboot/+/52797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1967f7c4a7e3cab714f22844bf36749e0c9652b6 Gerrit-Change-Number: 52797 Gerrit-PatchSet: 8 Gerrit-Owner: Star Labs <admin(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Star Labs <admin(a)starlabs.systems> Gerrit-Comment-Date: Tue, 11 May 2021 16:18:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/metaknight: Update DPTF parameters
by Raymond Wong (Code Review) 11 May '21

11 May '21

Attention is currently required from: David Wu, Evan Green, Brian Nemec, Karthikeyan Ramasubramanian. Raymond Wong has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54046 ) Change subject: mb/google/dedede/var/metaknight: Update DPTF parameters ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/54046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0ec1ec48b8971efe87f1f8d10332a9c16352122 Gerrit-Change-Number: 54046 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Brian Nemec <bnemec(a)google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Raymond Wong <wongraymond(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Evan Green <evgreen(a)chromium.org> Gerrit-Attention: Brian Nemec <bnemec(a)google.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Comment-Date: Tue, 11 May 2021 16:08:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: amd/cezanne: adding support for the changed AMD FSP API for USB PHY
by Raul Rangel (Code Review) 11 May '21

11 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Julian Schroeder, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54065 ) Change subject: amd/cezanne: adding support for the changed AMD FSP API for USB PHY ...................................................................... Patch Set 1: (3 comments) File src/vendorcode/amd/fsp/cezanne/FspUsb.h: https://review.coreboot.org/c/coreboot/+/54065/comment/27c3d85d_f42916f8 PS1, Line 10: #if 0 ? https://review.coreboot.org/c/coreboot/+/54065/comment/c6e91209_4135cf30 PS1, Line 44: compdstune Is there documentation that could be added to these? Or maybe we can define some enums? https://review.coreboot.org/c/coreboot/+/54065/comment/e8eb64fb_59365680 PS1, Line 67: nit: indenting -- To view, visit https://review.coreboot.org/c/coreboot/+/54065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I011ca40a334e4fd26778ca7f18b653298b14019b Gerrit-Change-Number: 54065 Gerrit-PatchSet: 1 Gerrit-Owner: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 11 May 2021 16:01:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: ec: Add Star Labs ITE 8987E support
by Patrick Rudolph (Code Review) 11 May '21

11 May '21

Attention is currently required from: Star Labs, Andy Pont. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52797 ) Change subject: ec: Add Star Labs ITE 8987E support ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1967f7c4a7e3cab714f22844bf36749e0c9652b6 Gerrit-Change-Number: 52797 Gerrit-PatchSet: 8 Gerrit-Owner: Star Labs <admin(a)starlabs.systems> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Star Labs <admin(a)starlabs.systems> Gerrit-Attention: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Comment-Date: Tue, 11 May 2021 15:52:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: amd/cezanne: adding support for the changed AMD FSP API for USB PHY
by Julian Schroeder (Code Review) 11 May '21

11 May '21

Julian Schroeder has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54065 ) Change subject: amd/cezanne: adding support for the changed AMD FSP API for USB PHY ...................................................................... amd/cezanne: adding support for the changed AMD FSP API for USB PHY The AMD FSP is using a new structure for USB and USB C phy settings. This patch removes old, unused structures, adds the new one and enables the devicetree interface for it. Signed-off-by: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Change-Id: I011ca40a334e4fd26778ca7f18b653298b14019b --- M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb M src/soc/amd/cezanne/chip.h M src/soc/amd/cezanne/fsp_m_params.c A src/vendorcode/amd/fsp/cezanne/FspUsb.h M src/vendorcode/amd/fsp/cezanne/FspmUpd.h 5 files changed, 211 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/54065/1 diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 3097425..3896126 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -162,4 +162,128 @@ device ref uart_0 on end # UART0 + register "usb_phy" = "{ + .Usb2PhyPort[0] = { + .compdstune = 3, + .sqrxtune = 3, + .txfslstune = 3, + .txpreempamptune = 1, + .txpreemppulsetune = 0, + .txrisetune = 1, + .txvreftune = 6, + .txhsxvtune = 3, + .txrestune = 1, + }, + .Usb2PhyPort[1] = { + .compdstune = 3, + .sqrxtune = 3, + .txfslstune = 3, + .txpreempamptune = 1, + .txpreemppulsetune = 0, + .txrisetune = 1, + .txvreftune = 6, + .txhsxvtune = 3, + .txrestune = 1, + }, + .Usb2PhyPort[2] = { + .compdstune = 1, + .sqrxtune = 3, + .txfslstune = 3, + .txpreempamptune = 2, + .txpreemppulsetune = 0, + .txrisetune = 2, + .txvreftune = 3, + .txhsxvtune = 3, + .txrestune = 2, + }, + .Usb2PhyPort[3] = { + .compdstune = 1, + .sqrxtune = 3, + .txfslstune = 3, + .txpreempamptune = 2, + .txpreemppulsetune = 0, + .txrisetune = 2, + .txvreftune = 3, + .txhsxvtune = 3, + .txrestune = 2, + }, + .Usb2PhyPort[4] = { + .compdstune = 3, + .sqrxtune = 3, + .txfslstune = 3, + .txpreempamptune = 1, + .txpreemppulsetune = 0, + .txrisetune = 1, + .txvreftune = 6, + .txhsxvtune = 3, + .txrestune = 1, + }, + .Usb2PhyPort[5] = { + .compdstune = 3, + .sqrxtune = 3, + .txfslstune = 3, + .txpreempamptune = 1, + .txpreemppulsetune = 0, + .txrisetune = 1, + .txvreftune = 6, + .txhsxvtune = 3, + .txrestune = 1, + }, + .Usb2PhyPort[6] = { + .compdstune = 1, + .sqrxtune = 3, + .txfslstune = 3, + .txpreempamptune = 2, + .txpreemppulsetune = 0, + .txrisetune = 2, + .txvreftune = 3, + .txhsxvtune = 3, + .txrestune = 2, + }, + .Usb2PhyPort[7] = { + .compdstune = 1, + .sqrxtune = 3, + .txfslstune = 3, + .txpreempamptune = 2, + .txpreemppulsetune = 0, + .txrisetune = 2, + .txvreftune = 3, + .txhsxvtune = 3, + .txrestune = 2, + }, + + .Usb3PhyPort[0] = { + .tx_term_ctrl=2, + .rx_term_ctrl=2, + .tx_vboost_lvl_en=1, + .tx_vboost_lvl=5, + }, + .Usb3PhyPort[1] = { + .tx_term_ctrl=2, + .rx_term_ctrl=2, + .tx_vboost_lvl_en=1, + .tx_vboost_lvl=5, + }, + .Usb3PhyPort[2] = { + .tx_term_ctrl=2, + .rx_term_ctrl=2, + .tx_vboost_lvl_en=1, + .tx_vboost_lvl=5, + }, + .Usb3PhyPort[3] = { + .tx_term_ctrl=2, + .rx_term_ctrl=2, + .tx_vboost_lvl_en=1, + .tx_vboost_lvl=5, + }, + + .ComboPhyStaticConfig[0] = 0, + .ComboPhyStaticConfig[1] = 0, + .Version_Major = 0xd, + .Version_Minor = 0x4, + .TableLength = 0x40, + .BatteryChargerEnable = 0, + .PhyP3CpmP4Support = 0, + }" + end # chip soc/amd/cezanne diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index 244f2ba..630fe19 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -7,6 +7,7 @@ #include <soc/i2c.h> #include <drivers/i2c/designware/dw_i2c.h> #include <types.h> +#include <vendorcode/amd/fsp/cezanne/FspUsb.h> struct soc_amd_cezanne_config { struct soc_amd_common_config common_config; @@ -75,6 +76,7 @@ uint32_t telemetry_vddcrsocfull_scale_current_mA; uint32_t telemetry_vddcrsocoffset; + struct usb_phy_config usb_phy; }; #endif /* CEZANNE_CHIP_H */ diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index 8da38ff..e316366 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -128,5 +128,7 @@ mcfg->telemetry_vddcrsocOffset = config->telemetry_vddcrsocoffset; + memcpy(&mcfg->usb_phy, &config->usb_phy, sizeof(struct usb_phy_config) ); + fsp_fill_pcie_ddi_descriptors(mcfg); } diff --git a/src/vendorcode/amd/fsp/cezanne/FspUsb.h b/src/vendorcode/amd/fsp/cezanne/FspUsb.h new file mode 100644 index 0000000..23ba25d --- /dev/null +++ b/src/vendorcode/amd/fsp/cezanne/FspUsb.h @@ -0,0 +1,77 @@ +#ifndef __FSPUSB_H__ +#define __FSPUSB_H__ + +#include <FspUpd.h> + +#define USB2_PORT_COUNT 8 +#define USB3_PORT_COUNT 4 +#define USBC_COMBO_PHY_COUNT 2 + +#if 0 +struct fch_usb2_phy __attribute__ ((__packed__)) { + uint8_t compdstune; ///< COMPDSTUNE + uint8_t sqrxtune; ///< SQRXTUNE + uint8_t txfslstune; ///< TXFSLSTUNE + uint8_t txpreempamptune; ///< TXPREEMPAMPTUNE + uint8_t txpreemppulsetune; ///< TXPREEMPPULSETUNE + uint8_t txrisetune; ///< TXRISETUNE + uint8_t txvreftune; ///< TXVREFTUNE + uint8_t txhsxvtune; ///< TXHSXVTUNE + uint8_t txrestune; ///< TXRESTUNE +}; + +struct fch_usb3_phy __attribute__ ((__packed__)) { + uint8_t TX_TERM_CTRL; ///< tx_term_ctrl + uint8_t RX_TERM_CTRL; ///< rx_term_ctrl + uint8_t TX_VBOOST_LVL_EN; ///< TX_VBOOST_LVL_EN + uint8_t TX_VBOOST_LVL; ///< TX_VBOOST_LVL +}; + +struct usb_phy_config __attribute__ ((__packed__)) { + uint8_t Version_Major; ///< USB IP version + uint8_t Version_Minor; ///< USB IP version + uint8_t TableLength; ///< TableLength + uint8_t Reserved0; + fch_usb2_phy Usb2PhyPort[USB2_PORT_COUNT]; ///< USB 2.0 Driving Strength + fch_usb3_phy Usb3PhyPort[USB3_PORT_COUNT]; ///< USB3 PHY Adjustment + uint8_t BatteryChargerEnable; ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0] + uint8_t PhyP3CpmP4Support; ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0] + uint8_t ComboPhyStaticConfig[USBC_COMBO_PHY_COUNT]; ///< 0-Type C, 1- USB only mode, 2- DP only mode, 3- USB + DP + uint8_t Reserved2[4]; +}; +#else +struct fch_usb2_phy { + uint8_t compdstune; ///< COMPDSTUNE + uint8_t sqrxtune; ///< SQRXTUNE + uint8_t txfslstune; ///< TXFSLSTUNE + uint8_t txpreempamptune; ///< TXPREEMPAMPTUNE + uint8_t txpreemppulsetune; ///< TXPREEMPPULSETUNE + uint8_t txrisetune; ///< TXRISETUNE + uint8_t txvreftune; ///< TXVREFTUNE + uint8_t txhsxvtune; ///< TXHSXVTUNE + uint8_t txrestune; ///< TXRESTUNE +} __attribute__ ((__packed__)) ; + +struct fch_usb3_phy { + uint8_t tx_term_ctrl; ///< tx_term_ctrl + uint8_t rx_term_ctrl; ///< rx_term_ctrl + uint8_t tx_vboost_lvl_en; ///< TX_VBOOST_LVL_EN + uint8_t tx_vboost_lvl; ///< TX_VBOOST_LVL +} __attribute__ ((__packed__)) ; + +struct usb_phy_config { + uint8_t Version_Major; ///< USB IP version + uint8_t Version_Minor; ///< USB IP version + uint8_t TableLength; ///< TableLength + uint8_t Reserved0; + struct fch_usb2_phy Usb2PhyPort[USB2_PORT_COUNT]; ///< USB 2.0 Driving Strength + struct fch_usb3_phy Usb3PhyPort[USB3_PORT_COUNT]; ///< USB3 PHY Adjustment + uint8_t BatteryChargerEnable; ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0] + uint8_t PhyP3CpmP4Support; ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0] + uint8_t ComboPhyStaticConfig[USBC_COMBO_PHY_COUNT]; ///< 0-Type C, 1- USB only mode, 2- DP only mode, 3- USB + DP + uint8_t Reserved2[4]; +} __attribute__ ((__packed__)) ; + +#endif + +#endif diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h index f01af85..e53f14b 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h +++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h @@ -1,6 +1,6 @@ /** @file * - * This file is automatically generated. + * This file is _NOT_ automatically generated in coreboot! * */ @@ -8,6 +8,7 @@ #define __FSPMUPD_H__ #include <FspUpd.h> +#include <FspUsb.h> #define FSPM_UPD_DXIO_DESCRIPTOR_COUNT 14 #define FSPM_UPD_DDI_DESCRIPTOR_COUNT 5 @@ -79,24 +80,7 @@ /** Offset 0x0447**/ uint8_t emmc0_sdr104_hs400_driver_strength; /** Offset 0x0448**/ uint8_t emmc0_ddr50_driver_strength; /** Offset 0x0449**/ uint8_t emmc0_sdr50_driver_strength; - /** Offset 0x044A**/ uint8_t fch_usb_version_major; - /** Offset 0x044B**/ uint8_t fch_usb_version_minor; - /** Offset 0x044C**/ uint8_t fch_usb_2_port0_phy_tune[9]; - /** Offset 0x0455**/ uint8_t fch_usb_2_port1_phy_tune[9]; - /** Offset 0x045E**/ uint8_t fch_usb_2_port2_phy_tune[9]; - /** Offset 0x0467**/ uint8_t fch_usb_2_port3_phy_tune[9]; - /** Offset 0x0470**/ uint8_t fch_usb_2_port4_phy_tune[9]; - /** Offset 0x0479**/ uint8_t fch_usb_2_port5_phy_tune[9]; - /** Offset 0x0482**/ uint8_t fch_usb_2_port6_phy_tune[9]; - /** Offset 0x048B**/ uint8_t fch_usb_2_port7_phy_tune[9]; - /** Offset 0x0494**/ uint8_t fch_usb_device_removable; - /** Offset 0x0495**/ uint8_t fch_usb_3_port_force_gen1; - /** Offset 0x0496**/ uint8_t fch_usb_u3_rx_det_wa_enable; - /** Offset 0x0497**/ uint8_t fch_usb_u3_rx_det_wa_portmap; - /** Offset 0x0498**/ uint8_t fch_usb_early_debug_select_enable; - /** Offset 0x0499**/ uint32_t xhci_oc_pin_select; - /** Offset 0x049D**/ uint8_t xhci0_force_gen1; - /** Offset 0x049E**/ uint8_t xhci_sparse_mode_enable; + /** Offset 0x044A**/ uint8_t UnusedUpdSpace0[85]; /** Offset 0x049F**/ uint32_t gnb_ioapic_base; /** Offset 0x04A3**/ uint8_t gnb_ioapic_id; /** Offset 0x04A4**/ uint8_t fch_ioapic_id; @@ -107,8 +91,9 @@ /** Offset 0x04CB**/ uint32_t telemetry_vddcrvddoffset; /** Offset 0x04CF**/ uint32_t telemetry_vddcrsocfull_scale_current; /** Offset 0x04D3**/ uint32_t telemetry_vddcrsocOffset; - /** Offset 0x04D7**/ uint8_t UnusedUpdSpace0[41]; - /** Offset 0x0500**/ uint16_t UpdTerminator; + /** Offset 0x04D7**/ struct usb_phy_config usb_phy; + /** Offset 0x053B**/ uint8_t UnusedUpdSpace1[197]; + /** Offset 0x0600**/ uint16_t UpdTerminator; } FSP_M_CONFIG; /** Fsp M UPD Configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/54065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I011ca40a334e4fd26778ca7f18b653298b14019b Gerrit-Change-Number: 54065 Gerrit-PatchSet: 1 Gerrit-Owner: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: docs: add recommendation for gpios regarding soft straps
by Felix Singer (Code Review) 11 May '21

11 May '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Paul Menzel, Arthur Heymans, Michael Niewöhner. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52297 ) Change subject: docs: add recommendation for gpios regarding soft straps ...................................................................... Patch Set 9: Code-Review+1 (1 comment) File Documentation/getting_started/gpio.md: https://review.coreboot.org/c/coreboot/+/52297/comment/1c5bd3d0_54bb4391 PS9, Line 135: a an -- To view, visit https://review.coreboot.org/c/coreboot/+/52297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33063a3f6a1c9cd5267d85f7da84deb554489a26 Gerrit-Change-Number: 52297 Gerrit-PatchSet: 9 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Tue, 11 May 2021 15:47:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/Tianocore: Update default build target, simplify build options
by Matt DeVillier (Code Review) 11 May '21

11 May '21

Attention is currently required from: Martin Roth, Stefan Reinauer, Angel Pons, Patrik Tesarik. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54019 ) Change subject: payloads/Tianocore: Update default build target, simplify build options ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > I meant what you described, excuse me. […] ah, yes because it boots in graphical vs text mode, the prompt might not show up over serial console. Not something I'd tested TBH -- To view, visit https://review.coreboot.org/c/coreboot/+/54019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If545fbd0c30be6dcc6ff43107b80980fa23a527e Gerrit-Change-Number: 54019 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrik Tesarik <depate(a)das-labor.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrik Tesarik <depate(a)das-labor.org> Gerrit-Comment-Date: Tue, 11 May 2021 15:32:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Patrik Tesarik <depate(a)das-labor.org> Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: memlayout changes for QCSDI & WMM feature
by Ravi kumar (Code Review) 11 May '21

11 May '21

Attention is currently required from: Sudheer Amrabadi. Hello Sudheer Amrabadi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/54064 to review the following change. Change subject: sc7280: memlayout changes for QCSDI & WMM feature ...................................................................... sc7280: memlayout changes for QCSDI & WMM feature Change-Id: If5ebcc9a35e0b86321045ef44bb4874144c6402f Signed-off-by: Sudheer Kumar Amrabadi <samrab(a)codeaurora.org> --- M src/soc/qualcomm/sc7280/memlayout.ld 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/54064/1 diff --git a/src/soc/qualcomm/sc7280/memlayout.ld b/src/soc/qualcomm/sc7280/memlayout.ld index 7b6f5a3..ed7fce4 100644 --- a/src/soc/qualcomm/sc7280/memlayout.ld +++ b/src/soc/qualcomm/sc7280/memlayout.ld @@ -22,8 +22,9 @@ AOPSRAM_END(0x0B100000) SSRAM_START(0x14680000) - OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K) - REGION(qcsdi, 0x14699000, 52K, 4K) + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x14680000, 100K) + REGION(qcsdi, 0x14699000, 48K, 4K) + REGION(modem_id, 0x146A5D00, 4, 4) SSRAM_END(0x146AB000) BSRAM_START(0x14800000) -- To view, visit https://review.coreboot.org/c/coreboot/+/54064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5ebcc9a35e0b86321045ef44bb4874144c6402f Gerrit-Change-Number: 54064 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Sudheer Amrabadi <samrab(a)codeaurora.org> Gerrit-Attention: Sudheer Amrabadi <samrab(a)codeaurora.org> Gerrit-MessageType: newchange

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