coreboot-gerrit May 2021

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Change in coreboot[master]: soc/amd/common/block/espi_util: Workaround in-band reset race condition
by Raul Rangel (Code Review) 11 May '21

11 May '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54070 ) Change subject: soc/amd/common/block/espi_util: Workaround in-band reset race condition ...................................................................... soc/amd/common/block/espi_util: Workaround in-band reset race condition When performing an in-band reset the host controller and the peripheral can have mismatched IO configs. i.e., The eSPI peripheral can be in IO-4 mode while, the eSPI host will be in IO-1. This results in the peripheral getting invalid packets and thus not responding. If the peripheral is alerting when we perform an in-band reset, there is a race condition in espi_send_command. 1) espi_send_command clears the interrupt status. 2) eSPI host controller hardware notices the alert and sends a GET_STATUS. 3) espi_send_command writes the in-band reset command. 4) eSPI hardware enqueues the in-band reset until GET_STATUS is complete. 5) GET_STATUS fails with NO_RESPONSE and sets the interrupt status. 6) eSPI hardware performs in-band reset. 7) espi_send_command checks the status and sees a NO_RESPONSE bit. As a workaround we allow the NO_RESPONSE status code when we perform an in-band reset. BUG=b:186135022 TEST=suspend_stress_test and S5->S0 tests on guybrush. Verified S3 suspend and S5 resume on zork. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I71271377f20eaf29032214be98794e1645d9b70a --- M src/soc/amd/common/block/lpc/espi_util.c 1 file changed, 31 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/54070/1 diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index 276bb3c..45117e5 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -419,6 +419,7 @@ union espi_txhdr1 hdr1; union espi_txhdr2 hdr2; union espi_txdata data; + uint32_t expected_status_codes; } __packed; /* Wait up to ESPI_CMD_TIMEOUT_US for hardware to clear DNCMD_STATUS bit. */ @@ -512,13 +513,14 @@ return -1; } - if (status & ~ESPI_STATUS_DNCMD_COMPLETE) { + if (status & ~(ESPI_STATUS_DNCMD_COMPLETE | cmd->expected_status_codes)) { espi_show_failure(cmd, "Error: unexpected eSPI status register bits set", status); return -1; } - espi_write32(ESPI_SLAVE0_INT_STS, ESPI_STATUS_DNCMD_COMPLETE); + espi_write32(ESPI_SLAVE0_INT_STS, + ESPI_STATUS_DNCMD_COMPLETE | cmd->expected_status_codes); return 0; } @@ -530,6 +532,33 @@ .cmd_type = CMD_TYPE_IN_BAND_RESET, .cmd_sts = 1, }, + + /* + * When performing an in-band reset the host controller and the + * peripheral can have mismatched IO configs. + * + * i.e., The eSPI peripheral can be in IO-4 mode while, the + * eSPI host will be in IO-1. This results in the peripheral + * getting invalid packets and thus not responding. + * + * If the peripheral is alerting when we perform an in-band + * reset, there is a race condition in espi_send_command. + * 1) espi_send_command clears the interrupt status. + * 2) eSPI host controller hardware notices the alert and sends + * a GET_STATUS. + * 3) espi_send_command writes the in-band reset command. + * 4) eSPI hardware enqueues the in-band reset until GET_STATUS + * is complete. + * 5) GET_STATUS fails with NO_RESPONSE and sets the interrupt + * status. + * 6) eSPI hardware performs in-band reset. + * 7) espi_send_command checks the status and sees a + * NO_RESPONSE bit. + * + * As a workaround we allow the NO_RESPONSE status code when + * we perform an in-band reset. + */ + .expected_status_codes = ESPI_STATUS_NO_RESPONSE, }; return espi_send_command(&cmd); -- To view, visit https://review.coreboot.org/c/coreboot/+/54070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71271377f20eaf29032214be98794e1645d9b70a Gerrit-Change-Number: 54070 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/{common,picasso}: Use common PCIE_GPP_DRIVER driver
by Raul Rangel (Code Review) 11 May '21

11 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54028 ) Change subject: soc/amd/{common,picasso}: Use common PCIE_GPP_DRIVER driver ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/54028/comment/87209985_0191cbe2 PS1, Line 7: Enable PCIE_GPP_DRIVER > "use common PCIE_GPP_DRIVER driver" maybe? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/54028 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic09200156e8a37bd1a29ca95a17c8f8ae2b92bd3 Gerrit-Change-Number: 54028 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 11 May 2021 18:55:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/{common,picasso}: Use common PCIE_GPP_DRIVER driver
by Raul Rangel (Code Review) 11 May '21

11 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54028 to look at the new patch set (#2). Change subject: soc/amd/{common,picasso}: Use common PCIE_GPP_DRIVER driver ...................................................................... soc/amd/{common,picasso}: Use common PCIE_GPP_DRIVER driver This will change the names of the GPP bridges, but this ok since there is no hand written ASL that references these names. BUG=b:184766519 TEST=Boot picasso and dump ACPI Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ic09200156e8a37bd1a29ca95a17c8f8ae2b92bd3 --- M src/soc/amd/common/block/pci/pcie_gpp.c M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/pcie_gpp.c 3 files changed, 10 insertions(+), 192 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/54028/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54028 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic09200156e8a37bd1a29ca95a17c8f8ae2b92bd3 Gerrit-Change-Number: 54028 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: payloads/Tianocore: Update default build target, simplify build options
by Matt DeVillier (Code Review) 11 May '21

11 May '21

Attention is currently required from: Martin Roth, Stefan Reinauer, Angel Pons, Patrik Tesarik. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54019 ) Change subject: payloads/Tianocore: Update default build target, simplify build options ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > No problem, can you give a hint how we can tackle this? For my use case text mode would be really ni […] possible we could add Kconfig option for this, and pass thru to makefile. Would need some changes on the Tianocore side but probably not too much -- To view, visit https://review.coreboot.org/c/coreboot/+/54019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If545fbd0c30be6dcc6ff43107b80980fa23a527e Gerrit-Change-Number: 54019 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrik Tesarik <depate(a)das-labor.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrik Tesarik <depate(a)das-labor.org> Gerrit-Comment-Date: Tue, 11 May 2021 18:32:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Patrik Tesarik <depate(a)das-labor.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/octopus/var/fleex: Add cs42l42 HSBIAS setting
by Furquan Shaikh (Code Review) 11 May '21

11 May '21

Attention is currently required from: Ian Feng. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53901 ) Change subject: mb/google/octopus/var/fleex: Add cs42l42 HSBIAS setting ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/53901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12c0e0a0f7490d35d36fe8ccbc940f29e1bb7976 Gerrit-Change-Number: 53901 Gerrit-PatchSet: 3 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Vitaly Rodionov <vitaly.rodionov(a)cirrus.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 11 May 2021 18:29:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: soc/intel/tigerlake: tcss change
by Deepti Deshatty (Code Review) 11 May '21

11 May '21

Attention is currently required from: Maulik V Vaghela. Deepti Deshatty has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54069 ) Change subject: soc/intel/common: soc/intel/tigerlake: tcss change ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/54069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc0330950b3a85681b8212b61b84811fdbe65149 Gerrit-Change-Number: 54069 Gerrit-PatchSet: 1 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Comment-Date: Tue, 11 May 2021 18:12:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: soc/intel/tigerlake: tcss change
by build bot (Jenkins) (Code Review) 11 May '21

11 May '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54069 ) Change subject: soc/intel/common: soc/intel/tigerlake: tcss change ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/tigerlake/fsp_params.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119050): https://review.coreboot.org/c/coreboot/+/54069/comment/01185e34_14c2e982 PS1, Line 473: /* Return type-c auxillary bias pads */ 'auxillary' may be misspelled - perhaps 'auxiliary'? -- To view, visit https://review.coreboot.org/c/coreboot/+/54069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc0330950b3a85681b8212b61b84811fdbe65149 Gerrit-Change-Number: 54069 Gerrit-PatchSet: 1 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 11 May 2021 18:09:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: soc/intel/tigerlake: tcss change
by Deepti Deshatty (Code Review) 11 May '21

11 May '21

Deepti Deshatty has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54069 ) Change subject: soc/intel/common: soc/intel/tigerlake: tcss change ...................................................................... soc/intel/common: soc/intel/tigerlake: tcss change Add config 'SOC_INTEL_COMMON_BLOCK_TCSS_DC_BIAS_SKIP' to skip type-c aux bias pad configuration in tcss. TEST= Signed-off-by: Deepti Deshatty <deepti.deshatty(a)intel.com> Change-Id: Idc0330950b3a85681b8212b61b84811fdbe65149 --- M src/soc/intel/common/block/include/intelblocks/tcss.h M src/soc/intel/common/block/tcss/Kconfig M src/soc/intel/common/block/tcss/tcss.c M src/soc/intel/tigerlake/fsp_params.c 4 files changed, 47 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/54069/1 diff --git a/src/soc/intel/common/block/include/intelblocks/tcss.h b/src/soc/intel/common/block/include/intelblocks/tcss.h index 29093d1..2a56fa4 100644 --- a/src/soc/intel/common/block/include/intelblocks/tcss.h +++ b/src/soc/intel/common/block/include/intelblocks/tcss.h @@ -148,7 +148,7 @@ * 2) Configure GPIO pads to provide DC Bias on AUX signals * 3) Detect DP-over-Type-C alternate mode */ -void tcss_configure(const struct typec_aux_bias_pads pads[MAX_TYPE_C_PORTS]); +void tcss_configure(void); /* * Mainboard method to setup any mux config needed for TCSS display operations. @@ -167,4 +167,11 @@ */ const struct tcss_port_map *mainboard_tcss_get_port_info(size_t *num_ports); +/* + * Soc methode to return 'typec_aux_bias_pads' soc config. + * All platforms may not define 'typec_aux_bias_pads'. + * Hence weak method is implemented to return NULL. + */ +const struct typec_aux_bias_pads *soc_get_typec_aux_bias_pads(void); + #endif /* _TCSS_H_ */ diff --git a/src/soc/intel/common/block/tcss/Kconfig b/src/soc/intel/common/block/tcss/Kconfig index 3eb0931..e0bf896 100644 --- a/src/soc/intel/common/block/tcss/Kconfig +++ b/src/soc/intel/common/block/tcss/Kconfig @@ -8,3 +8,9 @@ depends on SOC_INTEL_COMMON_BLOCK_TCSS && RUN_FSP_GOP help Enable displays to be detected over Type-C ports during boot. + +config SOC_INTEL_COMMON_BLOCK_TCSS_DC_BIAS_SKIP + def_bool n + depends on SOC_INTEL_COMMON_BLOCK_TCSS + help + Skip IOM configuration to handle Type-C aux lines DC bias in TCSS. diff --git a/src/soc/intel/common/block/tcss/tcss.c b/src/soc/intel/common/block/tcss/tcss.c index da19954..a2fc873 100644 --- a/src/soc/intel/common/block/tcss/tcss.c +++ b/src/soc/intel/common/block/tcss/tcss.c @@ -10,9 +10,12 @@ #include <security/vboot/vboot_common.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> -#include <soc/tcss.h> #include <stdlib.h> +#if !CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS_DC_BIAS_SKIP) +#include <soc/tcss.h> +#endif + #define BIAS_CTRL_VW_INDEX_SHIFT 16 #define BIAS_CTRL_BIT_POS_SHIFT 8 @@ -313,6 +316,12 @@ } } +#if !CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS_DC_BIAS_SKIP) +__weak const struct typec_aux_bias_pads *soc_get_typec_aux_bias_pads(void) +{ + NULL; +} + static uint32_t calc_bias_ctrl_reg_value(gpio_t pad) { unsigned int vw_index, vw_bit; @@ -325,20 +334,25 @@ cpu_pid; } -static void tcss_configure_aux_bias_pads( - const struct typec_aux_bias_pads pads[MAX_TYPE_C_PORTS]) +static void tcss_configure_aux_bias_pads(void) { + const struct typec_aux_bias_pads *p_pads = soc_get_typec_aux_bias_pads(); + + if (*p_pads == NULL) + return; + for (size_t i = 0; i < MAX_TYPE_C_PORTS; i++) { - if (pads[i].pad_auxn_dc && pads[i].pad_auxp_dc) { + if (p_pads[i].pad_auxn_dc && p_pads[i].pad_auxp_dc) { REGBAR32(PID_IOM, IOM_AUX_BIAS_CTRL_PULLUP_OFFSET(i)) = - calc_bias_ctrl_reg_value(pads[i].pad_auxp_dc); + calc_bias_ctrl_reg_value(p_pads[i].pad_auxp_dc); REGBAR32(PID_IOM, IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET(i)) = - calc_bias_ctrl_reg_value(pads[i].pad_auxn_dc); + calc_bias_ctrl_reg_value(p_pads[i].pad_auxn_dc); } } } +#endif -void tcss_configure(const struct typec_aux_bias_pads aux_bias_pads[MAX_TYPE_C_PORTS]) +void tcss_configure(void) { const struct tcss_port_map *port_map; size_t num_ports; @@ -351,8 +365,10 @@ for (i = 0; i < num_ports; i++) tcss_init_mux(i, &port_map[i]); +#if !CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS_DC_BIAS_SKIP) /* This should be performed before alternate modes are entered */ - tcss_configure_aux_bias_pads(aux_bias_pads); + tcss_configure_aux_bias_pads(); +#endif if (CONFIG(ENABLE_TCSS_DISPLAY_DETECTION)) tcss_configure_dp_mode(port_map, num_ports); diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 1f1f365..7a6ea48 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -462,16 +462,21 @@ printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n", __FILE__, __func__); - if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS)) { - const config_t *config = config_of_soc(); - tcss_configure(config->typec_aux_bias_pads); - } + if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS)) + tcss_configure(); break; default: break; } } +/* Return type-c auxillary bias pads */ +const struct typec_aux_bias_pads *soc_get_typec_aux_bias_pads(void) +{ + const config_t *config = config_of_soc(); + return config->typec_aux_bias_pads; +} + /* Mainboard GPIO Configuration */ __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) { -- To view, visit https://review.coreboot.org/c/coreboot/+/54069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc0330950b3a85681b8212b61b84811fdbe65149 Gerrit-Change-Number: 54069 Gerrit-PatchSet: 1 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: tests: Enable config override for tests
by Patrick Georgi (Code Review) 11 May '21

11 May '21

Attention is currently required from: Jakub Czapiga, Julius Werner, Jan Dabros. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52937 ) Change subject: tests: Enable config override for tests ...................................................................... Patch Set 2: (1 comment) File tests/Makefile.inc: https://review.coreboot.org/c/coreboot/+/52937/comment/b4c7d230_6cac7b77 PS2, Line 89: $(TEST_KCONFIG_AUTOHEADER) > It does not use file under path from this variable directly, but logically it does. […] Right, to ensure that the file is around in time. Somehow I forgot about that aspect. Sorry for the noise. -- To view, visit https://review.coreboot.org/c/coreboot/+/52937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1aeb78362c2609fbefbfd91c0f58ec19ed258ee1 Gerrit-Change-Number: 52937 Gerrit-PatchSet: 2 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Comment-Date: Tue, 11 May 2021 17:45:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-MessageType: comment

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Change in coreboot[master]: docs: add recommendation for gpios regarding soft straps
by Michael Niewöhner (Code Review) 11 May '21

11 May '21

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52297 ) Change subject: docs: add recommendation for gpios regarding soft straps ...................................................................... docs: add recommendation for gpios regarding soft straps Soft straps, that can be configured by the vendor in the Intel Flash Image Tool (FIT), can influence some pads' default state. It is possible to select either a native function or GPIO mode for some pads on non-server SoCs, while on server SoCs most pads can be controlled. Thus, add a recommendation to always configure all pads for a board to guarantee integrity between different board or vendor firmware revisions where the soft straps might have been changed. Change-Id: I33063a3f6a1c9cd5267d85f7da84deb554489a26 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52297 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M Documentation/getting_started/gpio.md 1 file changed, 16 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/Documentation/getting_started/gpio.md b/Documentation/getting_started/gpio.md index 19e74ee..5d5623a 100644 --- a/Documentation/getting_started/gpio.md +++ b/Documentation/getting_started/gpio.md @@ -130,24 +130,24 @@ GPIO configuration the macro `PAD_NC(pad, NONE)` can be used to explicitly configure a pad as unconnected. -In case there are no schematics available for a board and the vendor sets a pad -to something like `GPIORXDIS=1`, `GPIOTXDIS=1` with an internal pull resistor, -an unconnected or otherwise unused pad can be assumed. In this case it is -recommended to keep the pull resistor, because the external circuit might rely -on it. +In case there are no schematics available for a board and the vendor set a +pad to something like `GPIORXDIS=1`, `GPIOTXDIS=1` with an internal pull +resistor, an unconnected or otherwise unused pad can be assumed. In this case it +is recommended to keep the pull resistor, because the external circuit might +rely on it. Unconnected pads defaulting to a native function (input and output) usually don't need to be configured as GPIO with the `GPIORXDIS` bit set. For clarity and documentation purpose the macro may be used as well for them. Some pads configured as native input function explicitly require external -pull-ups when unused, according to the PDGs: +pull-ups when being unused, according to the PDGs: - eDP_HPD - SMBCLK/SMBDATA - SML0CLK/SML0DATA/SML0ALERT - SATAGP* -If the board was designed correctly, nothing needs to be done for them +When the board was designed correctly, nothing needs to be done for them explicitly, while using `PAD_NC(pad, NONE)` can act as documentation. If such a pad is missing the external pull resistor due to bad board design, the pad should be configured with `PAD_NC(pad, NONE)` anyway to disconnect it @@ -162,6 +162,15 @@ input. There is a real risk in this case of short-circuiting a component which could cause catastrophic failures, up to and including your mainboard! +## Soft Straps + +Soft straps, that can be configured by the vendor in the Intel Flash Image Tool +(FIT), can influence some pads' default mode. It is possible to select either a +native function or GPIO mode for some pads on non-server SoCs, while on server +SoCs most pads can be controlled. Thus, it is generally recommended to always +configure all pads and don't just rely on the defaults mentioned in the +datasheet(s) which might not reflect what the vendor configured. + ## Pad-related known issues and workarounds ### LPC_CLKRUNB blocks S0ix states when board uses eSPI -- To view, visit https://review.coreboot.org/c/coreboot/+/52297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33063a3f6a1c9cd5267d85f7da84deb554489a26 Gerrit-Change-Number: 52297 Gerrit-PatchSet: 11 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit May 2021