coreboot-gerrit May 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: amd/cezanne: adding support for the changed AMD FSP API for USB PHY
by Raul Rangel (Code Review) 11 May '21

11 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Julian Schroeder, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54065 ) Change subject: amd/cezanne: adding support for the changed AMD FSP API for USB PHY ...................................................................... Patch Set 3: (1 comment) File src/vendorcode/amd/fsp/cezanne/FspUsb.h: https://review.coreboot.org/c/coreboot/+/54065/comment/4dee2841_86413341 PS1, Line 44: compdstune > This stuff is explained in the USB2 spec and the PPR. […] Can you maybe add some breadcrumbs on where to look for these parameters? Right now I have no idea what these mean or where the documentation is for them. -- To view, visit https://review.coreboot.org/c/coreboot/+/54065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I011ca40a334e4fd26778ca7f18b653298b14019b Gerrit-Change-Number: 54065 Gerrit-PatchSet: 3 Gerrit-Owner: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 11 May 2021 20:02:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/dptf: Add OEM variables support
by Tim Wawrzynczak (Code Review) 11 May '21

11 May '21

Attention is currently required from: Lance Zhao, Furquan Shaikh, Justin TerAvest, Sumeet R Pawnikar, Todd Broch, Aaron Durbin, Patrick Rudolph, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50127 ) Change subject: drivers/intel/dptf: Add OEM variables support ...................................................................... Patch Set 6: (1 comment) File src/drivers/intel/dptf/dptf.c: https://review.coreboot.org/c/coreboot/+/50127/comment/9b3c6d8d_02b41928 PS6, Line 128: get_STA_value I think as is, this will return `ACPI_STATUS_DEVICE_ALL_OFF` for IETM? it calls `is_participant_used` to check if the device should be present or not -- To view, visit https://review.coreboot.org/c/coreboot/+/50127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf3cf7b40e9a441b41d0c659d76895a58669c2fb Gerrit-Change-Number: 50127 Gerrit-PatchSet: 6 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Todd Broch <tbroch(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Justin TerAvest <teravest(a)chromium.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Todd Broch <tbroch(a)chromium.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 11 May 2021 19:59:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: enable DPTF functionality for brya
by Tim Wawrzynczak (Code Review) 11 May '21

11 May '21

Attention is currently required from: Furquan Shaikh, Sumeet R Pawnikar. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52859 ) Change subject: mb/google/brya: enable DPTF functionality for brya ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brya/variants/brya0/overridetree.cb: https://review.coreboot.org/c/coreboot/+/52859/comment/6bfb8bd2_f2fc0882 PS3, Line 14: Ambient I only see the first two sensors in the EC code... when I cherry pick this patch, I see a large negative temp for TSR2: ``` localhost ~ # grep -H . /sys/class/thermal/thermal_zone*/{type,temp} /sys/class/thermal/thermal_zone0/type:x86_pkg_temp /sys/class/thermal/thermal_zone1/type:INT3400 Thermal /sys/class/thermal/thermal_zone2/type:TSR0 /sys/class/thermal/thermal_zone3/type:TSR1 /sys/class/thermal/thermal_zone4/type:TSR2 /sys/class/thermal/thermal_zone5/type:TCPU /sys/class/thermal/thermal_zone0/temp:24000 /sys/class/thermal/thermal_zone1/temp:20000 /sys/class/thermal/thermal_zone2/temp:24850 /sys/class/thermal/thermal_zone3/temp:29850 /sys/class/thermal/thermal_zone4/temp:-273150 /sys/class/thermal/thermal_zone5/temp:19000 ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/52859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33266c85aa30869466034ccbab04a3c7820ae2b0 Gerrit-Change-Number: 52859 Gerrit-PatchSet: 3 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Comment-Date: Tue, 11 May 2021 19:54:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: chromeec: Add battery display SoC to ACPI
by Daisuke Nojiri (Code Review) 11 May '21

11 May '21

Daisuke Nojiri has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/52686 ) Change subject: chromeec: Add battery display SoC to ACPI ...................................................................... Abandoned No longer needed. -- To view, visit https://review.coreboot.org/c/coreboot/+/52686 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a29bd2cc836ad65df3299011ef3620e992980a5 Gerrit-Change-Number: 52686 Gerrit-PatchSet: 1 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: chromeec: Add battery display SoC to ACPI
by Tim Wawrzynczak (Code Review) 11 May '21

11 May '21

Attention is currently required from: Daisuke Nojiri. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52686 ) Change subject: chromeec: Add battery display SoC to ACPI ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: I don't think this is required anymore? -- To view, visit https://review.coreboot.org/c/coreboot/+/52686 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a29bd2cc836ad65df3299011ef3620e992980a5 Gerrit-Change-Number: 52686 Gerrit-PatchSet: 1 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Comment-Date: Tue, 11 May 2021 19:35:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Disable EC sync for adlrvp_ext_ec
by Tim Wawrzynczak (Code Review) 11 May '21

11 May '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54016 ) Change subject: mb/intel/adlrvp: Disable EC sync for adlrvp_ext_ec ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: does it fail with recovery reason 0x58, VB2_RECOVERY_EC_HASH_SIZE ? -- To view, visit https://review.coreboot.org/c/coreboot/+/54016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62a4fceb83dc6b20f699b4662e8f421aadafdee5 Gerrit-Change-Number: 54016 Gerrit-PatchSet: 3 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Tue, 11 May 2021 19:28:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/espi_util: Workaround in-band reset race condition
by Raul Rangel (Code Review) 11 May '21

11 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Rob Barnes, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54070 ) Change subject: soc/amd/common/block/espi_util: Workaround in-band reset race condition ...................................................................... Patch Set 1: (2 comments) File src/soc/amd/common/block/lpc/espi_util.c: https://review.coreboot.org/c/coreboot/+/54070/comment/a9cc69a8_ea44a7aa PS1, Line 544: If the peripheral is alerting when we perform an in-band : * reset > Do we know why the peripheral is alerting? It's a keyboard IRQ from the little bit I've seen. I haven't done a deep dive to see what causes it yet. https://review.coreboot.org/c/coreboot/+/54070/comment/a24c8a34_21d19766 PS1, Line 558: workaround > I am a bit skeptical about this. This is one race condition that we are working around. […] Yes we could, A port 80 write in the middle of espi_setup is another race condition. Ideally there would be a mutex that prevents the eSPI hardware from sending any transactions over the bus so the firmware can write and wait for transactions. I can't find any such mutex, so we will always be fighting with the hardware. On boards that have a full rework #22 that ties eSPI_RESET# to SLP_S5, this condition isn't hit. We currently have b/187538731 open to pick which option we want to use on proto 1. -- To view, visit https://review.coreboot.org/c/coreboot/+/54070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71271377f20eaf29032214be98794e1645d9b70a Gerrit-Change-Number: 54070 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 11 May 2021 19:24:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/amd/majolica: Disable IO ports 0x60/0x64
by Raul Rangel (Code Review) 11 May '21

11 May '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54071 ) Change subject: mb/amd/majolica: Disable IO ports 0x60/0x64 ...................................................................... mb/amd/majolica: Disable IO ports 0x60/0x64 I suspect there is additional initialization required to enable the 8042 keyboard controller on the EC. By removing the range we no longer encounter long 20 second delays when reading the IO ports. Since depthcharge polls the IO ports it makes it seem like depthcharge locked up. BUG=b:182100027 TEST=Boot majolica with depthcharge to OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I56a7eb4200e4615e1b4d9f14594d64f93e031a54 --- M src/mainboard/amd/majolica/devicetree.cb 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/54071/1 diff --git a/src/mainboard/amd/majolica/devicetree.cb b/src/mainboard/amd/majolica/devicetree.cb index 422c009..0f540a1 100644 --- a/src/mainboard/amd/majolica/devicetree.cb +++ b/src/mainboard/amd/majolica/devicetree.cb @@ -2,8 +2,7 @@ chip soc/amd/cezanne register "common_config.espi_config" = "{ - .std_io_decode_bitmap = ESPI_DECODE_IO_0X60_0X64_EN | ESPI_DECODE_IO_0x80_EN - | ESPI_DECODE_IO_0X2E_0X2F_EN, + .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN, .io_mode = ESPI_IO_MODE_QUAD, .op_freq_mhz = ESPI_OP_FREQ_16_MHZ, .crc_check_enable = 1, -- To view, visit https://review.coreboot.org/c/coreboot/+/54071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56a7eb4200e4615e1b4d9f14594d64f93e031a54 Gerrit-Change-Number: 54071 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/metaknight: Update DPTF parameters
by Evan Green (Code Review) 11 May '21

11 May '21

Attention is currently required from: David Wu, Brian Nemec, Karthikeyan Ramasubramanian. Evan Green has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54046 ) Change subject: mb/google/dedede/var/metaknight: Update DPTF parameters ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0ec1ec48b8971efe87f1f8d10332a9c16352122 Gerrit-Change-Number: 54046 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Brian Nemec <bnemec(a)google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Raymond Wong <wongraymond(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Brian Nemec <bnemec(a)google.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Comment-Date: Tue, 11 May 2021 19:10:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/espi_util: Workaround in-band reset race condition
by Furquan Shaikh (Code Review) 11 May '21

11 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes, Felix Held. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54070 ) Change subject: soc/amd/common/block/espi_util: Workaround in-band reset race condition ...................................................................... Patch Set 1: Code-Review+2 (3 comments) Patchset: PS1: Change looks okay as a workaround for now. But, we might need to reconsider the decision about what eSPI_RESET# should be tied to on the SoC. File src/soc/amd/common/block/lpc/espi_util.c: https://review.coreboot.org/c/coreboot/+/54070/comment/13d6d06d_0d516854 PS1, Line 544: If the peripheral is alerting when we perform an in-band : * reset Do we know why the peripheral is alerting? https://review.coreboot.org/c/coreboot/+/54070/comment/64bd5d8f_98145d33 PS1, Line 558: workaround I am a bit skeptical about this. This is one race condition that we are working around. Depending upon what state the espi controller was in when the platform reset, could we see different kinds of race conditions? Basically we are working around the fact that we are not tying the eSPI_RESET# to anything on the SoC that resets on platform reset. Would it make sense to have a GPIO control eSPI_RESET# (at least as a no-stuff connection for future build)? It might give some flexibility if we start seeing more issues during other kinds of testing. -- To view, visit https://review.coreboot.org/c/coreboot/+/54070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71271377f20eaf29032214be98794e1645d9b70a Gerrit-Change-Number: 54070 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 11 May 2021 19:06:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit May 2021