coreboot-gerrit May 2021

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Change in coreboot[master]: cpu/x86/smm: Fix size_t type mismatch in print statement
by Paul Menzel (Code Review) 16 May '21

16 May '21

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54342 ) Change subject: cpu/x86/smm: Fix size_t type mismatch in print statement ...................................................................... cpu/x86/smm: Fix size_t type mismatch in print statement Fix the format warning below: CC ramstage/cpu/x86/smm/smm_module_loader.o src/cpu/x86/smm/smm_module_loader.c: In function 'smm_module_setup_stub': src/cpu/x86/smm/smm_module_loader.c:360:70: error: format '%lx' expects argument of type 'long unsigned int', but argument 5 has type 'unsigned int' [-Werror=format=] 360 | printk(BIOS_ERR, "%s: state save size: %zx : smm_entry_offset -> %lx\n", | ~~^ | | | long unsigned int | %x Fixes: afb7a814 ("cpu/x86/smm: Introduce SMM module loader version 2") Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Change-Id: I4172e0f4dc40437250da89b7720a5c1e5fbab709 --- M src/cpu/x86/smm/smm_module_loader.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/54342/1 diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 1a7b448..ecdd493 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -357,7 +357,7 @@ /* The save state size encroached over the first SMM entry point. */ if (size <= SMM_ENTRY_OFFSET) { printk(BIOS_ERR, "%s: encroachment over SMM entry point\n", __func__); - printk(BIOS_ERR, "%s: state save size: %zx : smm_entry_offset -> %lx\n", + printk(BIOS_ERR, "%s: state save size: %zx : smm_entry_offset -> %zx\n", __func__, size, (size_t)SMM_ENTRY_OFFSET); return -1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/54342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4172e0f4dc40437250da89b7720a5c1e5fbab709 Gerrit-Change-Number: 54342 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/smm: Fix uintptr_t type mismatches in print statements
by Paul Menzel (Code Review) 16 May '21

16 May '21

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54341 ) Change subject: cpu/x86/smm: Fix uintptr_t type mismatches in print statements ...................................................................... cpu/x86/smm: Fix uintptr_t type mismatches in print statements Fix the uintptr_t type mismatches of the type below: CC ramstage/cpu/x86/smm/smm_module_loader.o src/cpu/x86/smm/smm_module_loader.c: In function 'smm_create_map': src/cpu/x86/smm/smm_module_loader.c:146:19: error: format '%zx' expects argument of type 'size_t', but argument 3 has type 'uintptr_t' {aka 'long unsigned int'} [-Werror=format=] 146 | " smbase %zx entry %zx\n", | ~~^ | | | unsigned int | %lx 147 | cpus[i].smbase, cpus[i].entry); | ~~~~~~~~~~~~~~ | | | uintptr_t {aka long unsigned int} Fixes: afb7a814 ("cpu/x86/smm: Introduce SMM module loader version 2") Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Change-Id: I32bff397c8a033fe34390e6c1a7dfe773707a4e8 --- M src/cpu/x86/smm/smm_module_loader.c 1 file changed, 7 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/54341/1 diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index e3b8417..1a7b448 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi_gnvs.h> +#include <inttypes.h> #include <stdint.h> #include <string.h> #include <rmodule.h> @@ -143,10 +144,10 @@ for (i = 0; i < num_cpus; i++) { printk(BIOS_DEBUG, "CPU 0x%x\n", i); printk(BIOS_DEBUG, - " smbase %zx entry %zx\n", + " smbase %" PRIxPTR " entry %" PRIxPTR "\n", cpus[i].smbase, cpus[i].entry); printk(BIOS_DEBUG, - " ss_start %zx code_end %zx\n", + " ss_start %" PRIxPTR " code_end %" PRIxPTR "\n", cpus[i].ss_start, cpus[i].code_end); seg_count++; if (seg_count >= cpus_in_segment) { @@ -217,13 +218,13 @@ if (cpus[num_cpus].active) { if (cpus[num_cpus - 1].smbase + SMM_ENTRY_OFFSET < stack_top) { printk(BIOS_ERR, "%s: stack encroachment\n", __func__); - printk(BIOS_ERR, "%s: smbase %zx, stack_top %lx\n", + printk(BIOS_ERR, "%s: smbase %" PRIxPTR ", stack_top %lx\n", __func__, cpus[num_cpus].smbase, stack_top); return 0; } } - printk(BIOS_INFO, "%s: smbase %zx, stack_top %lx\n", + printk(BIOS_INFO, "%s: smbase %" PRIxPTR ", stack_top %lx\n", __func__, cpus[num_cpus-1].smbase, stack_top); /* start at 1, the first CPU stub code is already there */ @@ -231,9 +232,9 @@ for (i = 1; i < num_cpus; i++) { memcpy((int *)cpus[i].code_start, (int *)cpus[0].code_start, size); printk(BIOS_DEBUG, - "SMM Module: placing smm entry code at %zx, cpu # 0x%x\n", + "SMM Module: placing smm entry code at %" PRIxPTR ", cpu # 0x%x\n", cpus[i].code_start, i); - printk(BIOS_DEBUG, "%s: copying from %zx to %zx 0x%x bytes\n", + printk(BIOS_DEBUG, "%s: copying from %" PRIxPTR " to %" PRIxPTR " 0x%x bytes\n", __func__, cpus[0].code_start, cpus[i].code_start, size); } return 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/54341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32bff397c8a033fe34390e6c1a7dfe773707a4e8 Gerrit-Change-Number: 54341 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Add configurable value for UsbTcPortEn
by Tim Wawrzynczak (Code Review) 16 May '21

16 May '21

Attention is currently required from: Selma Bensaid, Sridhar Siricilla, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54334 ) Change subject: soc/intel/alderlake: Add configurable value for UsbTcPortEn ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/alderlake/chip.h: https://review.coreboot.org/c/coreboot/+/54334/comment/6b9f2e3f_97af7d81 PS2, Line 48: uint8_t UsbTcPortEn; suggestion: an array of `bool` would be a nicer interface than raw bitmask, e.g. ``` bool typec_port_enable[MAX_TYPE_C_PORTS]; ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/54334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5cd0690945b9296c105ade2d99f68bbf0ee22bd Gerrit-Change-Number: 54334 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.corp-partner.google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 16 May 2021 17:13:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add configurable value for UsbTcPortEn
by Tim Wawrzynczak (Code Review) 16 May '21

16 May '21

Attention is currently required from: Selma Bensaid, Sridhar Siricilla, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54334 ) Change subject: soc/intel/alderlake: Add configurable value for UsbTcPortEn ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/54334/comment/f1d01fb2_5614c84b PS2, Line 131: UsbTcPortEn `UsbTcPortEn` needs to be opened -- To view, visit https://review.coreboot.org/c/coreboot/+/54334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5cd0690945b9296c105ade2d99f68bbf0ee22bd Gerrit-Change-Number: 54334 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.corp-partner.google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 16 May 2021 17:11:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Enable HECI1 communication
by Tim Wawrzynczak (Code Review) 16 May '21

16 May '21

Attention is currently required from: Furquan Shaikh, Sridhar Siricilla. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54210 ) Change subject: mb/google/brya: Enable HECI1 communication ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54210 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73acdd99788f9b60b7bcea372145e9694a124174 Gerrit-Change-Number: 54210 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Sun, 16 May 2021 17:10:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/broadwell/pch: Replace ACPI device NVS
by Tim Wawrzynczak (Code Review) 16 May '21

16 May '21

Attention is currently required from: Nico Huber, Martin Roth, Angel Pons, Arthur Heymans, Kyösti Mälkki, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52520 ) Change subject: soc/intel/broadwell/pch: Replace ACPI device NVS ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89fb658fbb10a8769ebea2e6535c45cd7c212d06 Gerrit-Change-Number: 52520 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 16 May 2021 17:09:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add configurable value for UsbTcPortEn
by Sridhar Siricilla (Code Review) 16 May '21

16 May '21

Attention is currently required from: Selma Bensaid, Tim Wawrzynczak, Sridhar Siricilla, Patrick Rudolph. Hello build bot (Jenkins), Selma Bensaid, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54334 to look at the new patch set (#2). Change subject: soc/intel/alderlake: Add configurable value for UsbTcPortEn ...................................................................... soc/intel/alderlake: Add configurable value for UsbTcPortEn As a requirement of TCSS this setting needs to be correctly set to determine what Type-C ports are enabled on the platform. BUG=b:184324979 TEST=Verified on brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ic5cd0690945b9296c105ade2d99f68bbf0ee22bd --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/54334/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5cd0690945b9296c105ade2d99f68bbf0ee22bd Gerrit-Change-Number: 54334 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.corp-partner.google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/mancomb: enable DDI0-DP port
by Martin Roth (Code Review) 16 May '21

16 May '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54297 ) Change subject: mb/google/mancomb: enable DDI0-DP port ...................................................................... mb/google/mancomb: enable DDI0-DP port Configure DDI-0 connector type to DP. BUG=b:187856682 TEST=Build and boot into OS Signed-off-by: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Change-Id: Ic8af14509b0d246c5c2da6e1a48991384471e69f Reviewed-on: https://review.coreboot.org/c/coreboot/+/54297 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/google/mancomb/port_descriptors.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/mainboard/google/mancomb/port_descriptors.c b/src/mainboard/google/mancomb/port_descriptors.c index b894cb2..b992906 100644 --- a/src/mainboard/google/mancomb/port_descriptors.c +++ b/src/mainboard/google/mancomb/port_descriptors.c @@ -79,8 +79,8 @@ /* TODO: verify the DDI table, since this is mostly an educated guess right now */ static const fsp_ddi_descriptor mancomb_czn_ddi_descriptors[] = { - { /* DDI0 - eDP */ - .connector_type = DDI_UNUSED_TYPE, + { /* DDI0 - DP */ + .connector_type = DDI_DP, .aux_index = DDI_AUX1, .hdp_index = DDI_HDP1 }, -- To view, visit https://review.coreboot.org/c/coreboot/+/54297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8af14509b0d246c5c2da6e1a48991384471e69f Gerrit-Change-Number: 54297 Gerrit-PatchSet: 2 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/mancomb: enable DDI0-DP port
by Martin Roth (Code Review) 16 May '21

16 May '21

Attention is currently required from: Ivy Jian. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54297 ) Change subject: mb/google/mancomb: enable DDI0-DP port ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8af14509b0d246c5c2da6e1a48991384471e69f Gerrit-Change-Number: 54297 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Sun, 16 May 2021 16:35:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/asus/p8x7x: Turn P8Z77-V LX2 into a variant of P8x7x baseboard
by Bill XIE (Code Review) 16 May '21

16 May '21

Attention is currently required from: Angel Pons. Hello build bot (Jenkins), Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54337 to look at the new patch set (#2). Change subject: mb/asus/p8x7x: Turn P8Z77-V LX2 into a variant of P8x7x baseboard ...................................................................... mb/asus/p8x7x: Turn P8Z77-V LX2 into a variant of P8x7x baseboard Other variants would be added later. Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Change-Id: Id9a7f1069233b43eb4a046f2e61c7a72fec7e960 --- M src/mainboard/asus/p8x7x/Kconfig M src/mainboard/asus/p8x7x/Kconfig.name M src/mainboard/asus/p8x7x/variants/z77-m_pro/overridetree.cb R src/mainboard/asus/p8x7x/variants/z77-v_lx2/acpi_tables.c A src/mainboard/asus/p8x7x/variants/z77-v_lx2/board_info.txt R src/mainboard/asus/p8x7x/variants/z77-v_lx2/data.vbt R src/mainboard/asus/p8x7x/variants/z77-v_lx2/early_init.c R src/mainboard/asus/p8x7x/variants/z77-v_lx2/gma-mainboard.ads R src/mainboard/asus/p8x7x/variants/z77-v_lx2/gpio.c R src/mainboard/asus/p8x7x/variants/z77-v_lx2/hda_verb.c A src/mainboard/asus/p8x7x/variants/z77-v_lx2/mainboard.c A src/mainboard/asus/p8x7x/variants/z77-v_lx2/overridetree.cb D src/mainboard/asus/p8z77-v_lx2/Kconfig D src/mainboard/asus/p8z77-v_lx2/Kconfig.name D src/mainboard/asus/p8z77-v_lx2/Makefile.inc D src/mainboard/asus/p8z77-v_lx2/acpi/ec.asl D src/mainboard/asus/p8z77-v_lx2/acpi/platform.asl D src/mainboard/asus/p8z77-v_lx2/acpi/superio.asl D src/mainboard/asus/p8z77-v_lx2/board_info.txt D src/mainboard/asus/p8z77-v_lx2/cmos.default D src/mainboard/asus/p8z77-v_lx2/cmos.layout D src/mainboard/asus/p8z77-v_lx2/devicetree.cb D src/mainboard/asus/p8z77-v_lx2/dsdt.asl 23 files changed, 53 insertions(+), 274 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/54337/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54337 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9a7f1069233b43eb4a046f2e61c7a72fec7e960 Gerrit-Change-Number: 54337 Gerrit-PatchSet: 2 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit May 2021