coreboot-gerrit May 2021

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Change in coreboot[master]: sb/intel: Drop outdated SMBus I/O BAR comment
by David Hendricks (Code Review) 16 May '21

16 May '21

David Hendricks has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54329 ) Change subject: sb/intel: Drop outdated SMBus I/O BAR comment ...................................................................... sb/intel: Drop outdated SMBus I/O BAR comment The SMBus I/O bar is not relocated because it's reported to the allocator as a fixed resource. Drop these out-of-date comments. Change-Id: I0149764fd231b3a4e56a5a9b7f4ae61f7954cf7a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54329 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/lynxpoint/pch.h 4 files changed, 0 insertions(+), 32 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, approved diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index fa0f712..15d908a 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -17,14 +17,6 @@ #define PCH_STEP_B2 4 #define PCH_STEP_B3 5 -/* - * It does not matter where we put the SMBus I/O base, as long as we - * keep it consistent and don't interfere with other devices. Stage2 - * will relocate this anyways. - * Our solution is to have SMB initialization move the I/O to CONFIG_FIXED_SMBUS_IO_BASE - * again. But handling static BARs is a generic problem that should be - * solved in the device allocator. - */ #define SMBUS_SLAVE_ADDR 0x24 /* TODO Make sure these don't get changed by stage2 */ #define DEFAULT_GPIOBASE 0x0480 diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 86330f8..f2ec1c6 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -3,14 +3,6 @@ #ifndef SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H #define SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H -/* - * It does not matter where we put the SMBus I/O base, as long as we - * keep it consistent and don't interfere with other devices. Stage2 - * will relocate this anyways. - * Our solution is to have SMB initialization move the I/O to CONFIG_FIXED_SMBUS_IO_BASE - * again. But handling static BARs is a generic problem that should be - * solved in the device allocator. - */ /* TODO Make sure these don't get changed by stage2 */ #define DEFAULT_GPIOBASE 0x0480 #define DEFAULT_PMBASE 0x0500 diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 94f927a..6565cd1 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -18,14 +18,6 @@ #define PCH_STEP_B2 4 #define PCH_STEP_B3 5 -/* - * It does not matter where we put the SMBus I/O base, as long as we - * keep it consistent and don't interfere with other devices. Stage2 - * will relocate this anyways. - * Our solution is to have SMB initialization move the I/O to CONFIG_FIXED_SMBUS_IO_BASE - * again. But handling static BARs is a generic problem that should be - * solved in the device allocator. - */ #define SMBUS_SLAVE_ADDR 0x24 /* TODO Make sure these don't get changed by stage2 */ #define DEFAULT_GPIOBASE 0x0480 diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 763a6ca..c095298 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -43,14 +43,6 @@ #define LPT_LP_STEP_B1 0x03 #define LPT_LP_STEP_B2 0x04 -/* - * It does not matter where we put the SMBus I/O base, as long as we - * keep it consistent and don't interfere with other devices. Stage2 - * will relocate this anyways. - * Our solution is to have SMB initialization move the I/O to CONFIG_FIXED_SMBUS_IO_BASE - * again. But handling static BARs is a generic problem that should be - * solved in the device allocator. - */ #define SMBUS_SLAVE_ADDR 0x24 #if CONFIG(INTEL_LYNXPOINT_LP) -- To view, visit https://review.coreboot.org/c/coreboot/+/54329 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0149764fd231b3a4e56a5a9b7f4ae61f7954cf7a Gerrit-Change-Number: 54329 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Documentation/distributions: List System76
by Patrick Georgi (Code Review) 16 May '21

16 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54273 ) Change subject: Documentation/distributions: List System76 ...................................................................... Documentation/distributions: List System76 Copy the text from the [Web site](https://coreboot.org/users.html). Change-Id: I805f558514eb50580b5bd79bd4f964e66a15158d Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54273 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M Documentation/distributions.md 1 file changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Tim Crawford: Looks good to me, but someone else must approve diff --git a/Documentation/distributions.md b/Documentation/distributions.md index d4500a6..5740527 100644 --- a/Documentation/distributions.md +++ b/Documentation/distributions.md @@ -29,6 +29,13 @@ third party, [3mdeb](https://3mdeb.com). They provide current and tested firmware binaries on [GitHub](https://pcengines.github.io). +### System76 + +[System76](https://system76.com/) manufactures Linux laptops, desktops, and +servers. Some models are sold with [System76 Open +Firmware](https://github.com/system76/firmware-open), an open source +distribution of coreboot, EDK2, and System76 firmware applications. + ### Purism [Purism](https://www.puri.sm) sells laptops with a focus on user privacy and -- To view, visit https://review.coreboot.org/c/coreboot/+/54273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I805f558514eb50580b5bd79bd4f964e66a15158d Gerrit-Change-Number: 54273 Gerrit-PatchSet: 5 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: vboot/secdata_tpm: Create FWMP space in coreboot
by Patrick Georgi (Code Review) 16 May '21

16 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52919 ) Change subject: vboot/secdata_tpm: Create FWMP space in coreboot ...................................................................... vboot/secdata_tpm: Create FWMP space in coreboot This commit has coreboot create the Chrome OS Firmware Management Parameters (FWMP) space in the TPM. The space will be defined and the contents initialized to the defaults. BUG=b:184677625 BRANCH=None TEST=emerge-keeby coreboot Signed-off-by: Aseda Aboagye <aaboagye(a)google.com> Change-Id: I1f566e00f11046ff9a9891c65660af50fbb83675 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52919 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Andrey Pronin <apronin(a)chromium.org> --- M src/security/vboot/secdata_tpm.c 1 file changed, 20 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Andrey Pronin: Looks good to me, but someone else must approve diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 93a172d..dd36796 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -10,6 +10,7 @@ #include <security/tpm/tspi.h> #include <security/tpm/tss.h> #include <security/tpm/tss/tcg-1.2/tss_structures.h> +#include <security/tpm/tss/tcg-2.0/tss_structures.h> #include <vb2_api.h> #include <console/console.h> @@ -108,6 +109,14 @@ .TPMA_NV_PLATFORMCREATE = 1, }; +static const TPMA_NV fwmp_attr = { + .TPMA_NV_PLATFORMCREATE = 1, + .TPMA_NV_OWNERWRITE = 1, + .TPMA_NV_AUTHREAD = 1, + .TPMA_NV_PPREAD = 1, + .TPMA_NV_PPWRITE = 1, +}; + /* * This policy digest was obtained using TPM2_PolicyOR on 3 digests * corresponding to a sequence of @@ -188,6 +197,14 @@ sizeof(pcr0_allowed_policy)); } +static uint32_t setup_fwmp_space(struct vb2_context *ctx) +{ + uint32_t fwmp_space_size = vb2api_secdata_fwmp_create(ctx); + + return setup_space("FWMP", FWMP_NV_INDEX, ctx->secdata_fwmp, fwmp_space_size, + fwmp_attr, NULL, 0); +} + static uint32_t setup_kernel_space(struct vb2_context *ctx) { uint32_t kernel_space_size = vb2api_secdata_kernel_create(ctx); @@ -230,6 +247,9 @@ if (CONFIG(VBOOT_HAS_REC_HASH_SPACE)) RETURN_ON_FAILURE(set_mrc_hash_space(MRC_REC_HASH_NV_INDEX, mrc_hash_data)); + /* Define and write firmware management parameters space. */ + RETURN_ON_FAILURE(setup_fwmp_space(ctx)); + RETURN_ON_FAILURE(setup_firmware_space(ctx)); return TPM_SUCCESS; -- To view, visit https://review.coreboot.org/c/coreboot/+/52919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f566e00f11046ff9a9891c65660af50fbb83675 Gerrit-Change-Number: 52919 Gerrit-PatchSet: 9 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: vboot/secdata_tpm: Rename set_space()
by Patrick Georgi (Code Review) 16 May '21

16 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54308 ) Change subject: vboot/secdata_tpm: Rename set_space() ...................................................................... vboot/secdata_tpm: Rename set_space() The name `set_space()` seems to imply that it's writing to a TPM space when actually, the function can create a space and write to it. This commit attempts to make that a bit more clear. Additionally, in order to use the correct sizes when creating the space, this commit also refactors the functions slightly to incorporate the vboot context object such that the correct sizes are used. The various vboot APIs will return the size of the created object that we can then create the space with. BUG=b:184677625 BRANCH=None TEST=`emerge-keeby coreboot` Signed-off-by: Aseda Aboagye <aaboagye(a)google.com> Change-Id: I80a8342c51d7bfaa0cb2eb3fd37240425d5901be Reviewed-on: https://review.coreboot.org/c/coreboot/+/54308 Reviewed-by: Julius Werner <jwerner(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/security/vboot/secdata_tpm.c 1 file changed, 21 insertions(+), 18 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index db5f2e7..93a172d 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -151,9 +151,9 @@ return tlcl_write(index, data, length); } -static uint32_t set_space(const char *name, uint32_t index, const void *data, - uint32_t length, const TPMA_NV nv_attributes, - const uint8_t *nv_policy, size_t nv_policy_size) +static uint32_t setup_space(const char *name, uint32_t index, const void *data, + uint32_t length, const TPMA_NV nv_attributes, + const uint8_t *nv_policy, size_t nv_policy_size) { uint32_t rv; @@ -178,35 +178,38 @@ return safe_write(index, data, length); } -static uint32_t set_firmware_space(const void *firmware_blob) +static uint32_t setup_firmware_space(struct vb2_context *ctx) { - return set_space("firmware", FIRMWARE_NV_INDEX, firmware_blob, - VB2_SECDATA_FIRMWARE_SIZE, ro_space_attributes, - pcr0_allowed_policy, sizeof(pcr0_allowed_policy)); + uint32_t firmware_space_size = vb2api_secdata_firmware_create(ctx); + + return setup_space("firmware", FIRMWARE_NV_INDEX, + ctx->secdata_firmware, firmware_space_size, + ro_space_attributes, pcr0_allowed_policy, + sizeof(pcr0_allowed_policy)); } -static uint32_t set_kernel_space(const void *kernel_blob) +static uint32_t setup_kernel_space(struct vb2_context *ctx) { - return set_space("kernel", KERNEL_NV_INDEX, kernel_blob, - VB2_SECDATA_KERNEL_SIZE, rw_space_attributes, NULL, 0); + uint32_t kernel_space_size = vb2api_secdata_kernel_create(ctx); + + return setup_space("kernel", KERNEL_NV_INDEX, ctx->secdata_kernel, + kernel_space_size, rw_space_attributes, NULL, 0); } static uint32_t set_mrc_hash_space(uint32_t index, const uint8_t *data) { if (index == MRC_REC_HASH_NV_INDEX) { - return set_space("RO MRC Hash", index, data, HASH_NV_SIZE, - ro_space_attributes, pcr0_allowed_policy, + return setup_space("RO MRC Hash", index, data, HASH_NV_SIZE, + ro_space_attributes, pcr0_allowed_policy, sizeof(pcr0_allowed_policy)); } else { - return set_space("RW MRC Hash", index, data, HASH_NV_SIZE, - rw_space_attributes, NULL, 0); + return setup_space("RW MRC Hash", index, data, HASH_NV_SIZE, + rw_space_attributes, NULL, 0); } } static uint32_t _factory_initialize_tpm(struct vb2_context *ctx) { - vb2api_secdata_kernel_create(ctx); - RETURN_ON_FAILURE(tlcl_force_clear()); /* @@ -215,7 +218,7 @@ * indication that TPM factory initialization was successfully * completed. */ - RETURN_ON_FAILURE(set_kernel_space(ctx->secdata_kernel)); + RETURN_ON_FAILURE(setup_kernel_space(ctx)); /* * Define and set rec hash space, if available. No need to @@ -227,7 +230,7 @@ if (CONFIG(VBOOT_HAS_REC_HASH_SPACE)) RETURN_ON_FAILURE(set_mrc_hash_space(MRC_REC_HASH_NV_INDEX, mrc_hash_data)); - RETURN_ON_FAILURE(set_firmware_space(ctx->secdata_firmware)); + RETURN_ON_FAILURE(setup_firmware_space(ctx)); return TPM_SUCCESS; } -- To view, visit https://review.coreboot.org/c/coreboot/+/54308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80a8342c51d7bfaa0cb2eb3fd37240425d5901be Gerrit-Change-Number: 54308 Gerrit-PatchSet: 4 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Update vboot submodule to upstream/main (e681c37)
by Patrick Georgi (Code Review) 16 May '21

16 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54307 ) Change subject: Update vboot submodule to upstream/main (e681c37) ...................................................................... Update vboot submodule to upstream/main (e681c37) This commit updates the vboot submodule from commit 57c0c5b: cgpt: Move all GPT on SPI-NOR infra behind a flag to e681c37: change node locked version expectations Signed-off-by: Aseda Aboagye <aaboagye(a)google.com> Change-Id: Ifd130e3f66f1819f59f00703f0ad0c2278b544bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/54307 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M 3rdparty/vboot 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/3rdparty/vboot b/3rdparty/vboot index 57c0c5b..e681c37 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 57c0c5be50767c3f86c648bf33e15955cc349f25 +Subproject commit e681c371484b50c0cc35d91123b176acdc2449eb -- To view, visit https://review.coreboot.org/c/coreboot/+/54307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd130e3f66f1819f59f00703f0ad0c2278b544bf Gerrit-Change-Number: 54307 Gerrit-PatchSet: 3 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/gm45: Guard even more macro parameters
by Patrick Georgi (Code Review) 16 May '21

16 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54280 ) Change subject: nb/intel/gm45: Guard even more macro parameters ...................................................................... nb/intel/gm45: Guard even more macro parameters Add brackets around the parameters to avoid operation order problems. Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: Icb9d6e8bdafdac7ad820b1629d04e7bdfbcd4b3f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54280 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/northbridge/intel/gm45/raminit_read_write_training.c M src/northbridge/intel/gm45/raminit_receive_enable_calibration.c 2 files changed, 12 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve diff --git a/src/northbridge/intel/gm45/raminit_read_write_training.c b/src/northbridge/intel/gm45/raminit_read_write_training.c index 544c523..be614ae 100644 --- a/src/northbridge/intel/gm45/raminit_read_write_training.c +++ b/src/northbridge/intel/gm45/raminit_read_write_training.c @@ -12,13 +12,13 @@ } address_bunch_t; /* Read Training. */ -#define CxRDTy_MCHBAR(ch, bl) (0x14b0 + (ch * 0x0100) + ((7 - bl) * 4)) +#define CxRDTy_MCHBAR(ch, bl) (0x14b0 + ((ch) * 0x0100) + ((7 - (bl)) * 4)) #define CxRDTy_T_SHIFT 20 #define CxRDTy_T_MASK (0xf << CxRDTy_T_SHIFT) -#define CxRDTy_T(t) ((t << CxRDTy_T_SHIFT) & CxRDTy_T_MASK) +#define CxRDTy_T(t) (((t) << CxRDTy_T_SHIFT) & CxRDTy_T_MASK) #define CxRDTy_P_SHIFT 16 #define CxRDTy_P_MASK (0x7 << CxRDTy_P_SHIFT) -#define CxRDTy_P(p) ((p << CxRDTy_P_SHIFT) & CxRDTy_P_MASK) +#define CxRDTy_P(p) (((p) << CxRDTy_P_SHIFT) & CxRDTy_P_MASK) static const u32 read_training_schedule[] = { 0xfefefefe, 0x7f7f7f7f, 0xbebebebe, 0xdfdfdfdf, 0xeeeeeeee, 0xf7f7f7f7, 0xfafafafa, 0xfdfdfdfd, @@ -276,13 +276,13 @@ /* Write Training. */ #define CxWRTy_T_SHIFT 28 #define CxWRTy_T_MASK (0xf << CxWRTy_T_SHIFT) -#define CxWRTy_T(t) ((t << CxWRTy_T_SHIFT) & CxWRTy_T_MASK) +#define CxWRTy_T(t) (((t) << CxWRTy_T_SHIFT) & CxWRTy_T_MASK) #define CxWRTy_P_SHIFT 24 #define CxWRTy_P_MASK (0x7 << CxWRTy_P_SHIFT) -#define CxWRTy_P(p) ((p << CxWRTy_P_SHIFT) & CxWRTy_P_MASK) +#define CxWRTy_P(p) (((p) << CxWRTy_P_SHIFT) & CxWRTy_P_MASK) #define CxWRTy_F_SHIFT 18 #define CxWRTy_F_MASK (0x3 << CxWRTy_F_SHIFT) -#define CxWRTy_F(f) ((f << CxWRTy_F_SHIFT) & CxWRTy_F_MASK) +#define CxWRTy_F(f) (((f) << CxWRTy_F_SHIFT) & CxWRTy_F_MASK) #define CxWRTy_D_SHIFT 16 #define CxWRTy_D_MASK (0x3 << CxWRTy_D_SHIFT) #define CxWRTy_BELOW_D (0x3 << CxWRTy_D_SHIFT) diff --git a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c index 0b1c789..1d20746 100644 --- a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c +++ b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c @@ -5,29 +5,29 @@ #include <console/console.h> #include "gm45.h" -#define CxRECy_MCHBAR(x, y) (0x14a0 + (x * 0x0100) + ((3 - y) * 4)) +#define CxRECy_MCHBAR(x, y) (0x14a0 + ((x) * 0x0100) + ((3 - (y)) * 4)) #define CxRECy_SHIFT_L 0 #define CxRECy_MASK_L (3 << CxRECy_SHIFT_L) #define CxRECy_SHIFT_H 16 #define CxRECy_MASK_H (3 << CxRECy_SHIFT_H) #define CxRECy_T_SHIFT 28 #define CxRECy_T_MASK (0xf << CxRECy_T_SHIFT) -#define CxRECy_T(t) ((t << CxRECy_T_SHIFT) & CxRECy_T_MASK) +#define CxRECy_T(t) (((t) << CxRECy_T_SHIFT) & CxRECy_T_MASK) #define CxRECy_P_SHIFT 24 #define CxRECy_P_MASK (0x7 << CxRECy_P_SHIFT) -#define CxRECy_P(p) ((p << CxRECy_P_SHIFT) & CxRECy_P_MASK) +#define CxRECy_P(p) (((p) << CxRECy_P_SHIFT) & CxRECy_P_MASK) #define CxRECy_PH_SHIFT 22 #define CxRECy_PH_MASK (0x3 << CxRECy_PH_SHIFT) -#define CxRECy_PH(p) ((p << CxRECy_PH_SHIFT) & CxRECy_PH_MASK) +#define CxRECy_PH(p) (((p) << CxRECy_PH_SHIFT) & CxRECy_PH_MASK) #define CxRECy_PM_SHIFT 20 #define CxRECy_PM_MASK (0x3 << CxRECy_PM_SHIFT) -#define CxRECy_PM(p) ((p << CxRECy_PM_SHIFT) & CxRECy_PM_MASK) +#define CxRECy_PM(p) (((p) << CxRECy_PM_SHIFT) & CxRECy_PM_MASK) #define CxRECy_TIMING_MASK (CxRECy_T_MASK | CxRECy_P_MASK | \ CxRECy_PH_MASK | CxRECy_PM_MASK) #define CxDRT3_C_SHIFT 7 #define CxDRT3_C_MASK (0xf << CxDRT3_C_SHIFT) -#define CxDRT3_C(c) ((c << CxDRT3_C_SHIFT) & CxDRT3_C_MASK) +#define CxDRT3_C(c) (((c) << CxDRT3_C_SHIFT) & CxDRT3_C_MASK) /* group to byte-lane mapping: (cardF X group X 2 per group) */ static const char bytelane_map[2][4][2] = { /* A,B,C */{ { 0, 1 }, { 2, 3 }, { 4, 5 }, { 6, 7 } }, -- To view, visit https://review.coreboot.org/c/coreboot/+/54280 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb9d6e8bdafdac7ad820b1629d04e7bdfbcd4b3f Gerrit-Change-Number: 54280 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mainboard: Add Star Labs labtop series
by Star Labs (Code Review) 16 May '21

16 May '21

Attention is currently required from: Patrick Rudolph. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52798 to look at the new patch set (#16). Change subject: soc/mainboard: Add Star Labs labtop series ...................................................................... soc/mainboard: Add Star Labs labtop series Add support for LabTop Mk III (kblr) and LabTop Mk IV (cml) Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I37c74d03d86fb124ed96e45d1bf137eb2ec57251 --- M Documentation/distributions.md M Documentation/mainboard/index.md A src/mainboard/starlabs/Kconfig A src/mainboard/starlabs/Kconfig.name A src/mainboard/starlabs/labtop/Kconfig A src/mainboard/starlabs/labtop/Kconfig.name A src/mainboard/starlabs/labtop/Makefile.inc A src/mainboard/starlabs/labtop/acpi/ec.asl A src/mainboard/starlabs/labtop/acpi/mainboard.asl A src/mainboard/starlabs/labtop/acpi/sleep.asl A src/mainboard/starlabs/labtop/acpi/superio.asl A src/mainboard/starlabs/labtop/board_info.txt A src/mainboard/starlabs/labtop/bootblock.c A src/mainboard/starlabs/labtop/cmos.default A src/mainboard/starlabs/labtop/cmos.layout A src/mainboard/starlabs/labtop/dsdt.asl A src/mainboard/starlabs/labtop/hda_verb.c A src/mainboard/starlabs/labtop/mainboard.c A src/mainboard/starlabs/labtop/ramstage.c A src/mainboard/starlabs/labtop/spd/Makefile.inc A src/mainboard/starlabs/labtop/spd/empty_ddr4.spd.hex A src/mainboard/starlabs/labtop/spd/gskill-F4-3200C22S.hex A src/mainboard/starlabs/labtop/spd/micron-MT40A1G16KD-062E-E.spd.hex A src/mainboard/starlabs/labtop/spd/micron_dimm_MT40A1G16KD-062EE.spd.hex A src/mainboard/starlabs/labtop/spd/samsung-K4A8G165WB-BCRC.spd.hex A src/mainboard/starlabs/labtop/spd/spd.h A src/mainboard/starlabs/labtop/spd/spd_util.c A src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/memory.h A src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/romstage.h A src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/variants.h A src/mainboard/starlabs/labtop/variants/cml/Makefile.inc A src/mainboard/starlabs/labtop/variants/cml/board.fmd A src/mainboard/starlabs/labtop/variants/cml/data.vbt A src/mainboard/starlabs/labtop/variants/cml/devicetree.cb A src/mainboard/starlabs/labtop/variants/cml/gma-mainboard.ads A src/mainboard/starlabs/labtop/variants/cml/include/variant/gpio.h A src/mainboard/starlabs/labtop/variants/cml/include/variant/hda_verb.h A src/mainboard/starlabs/labtop/variants/cml/romstage.c A src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc A src/mainboard/starlabs/labtop/variants/kbl/board.fmd A src/mainboard/starlabs/labtop/variants/kbl/data.vbt A src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb A src/mainboard/starlabs/labtop/variants/kbl/gma-mainboard.ads A src/mainboard/starlabs/labtop/variants/kbl/include/variant/gpio.h A src/mainboard/starlabs/labtop/variants/kbl/include/variant/hda_verb.h A src/mainboard/starlabs/labtop/variants/kbl/romstage.c 46 files changed, 2,066 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/52798/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/52798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37c74d03d86fb124ed96e45d1bf137eb2ec57251 Gerrit-Change-Number: 52798 Gerrit-PatchSet: 16 Gerrit-Owner: Star Labs <admin(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/x86/smm: Fix u32 type mismatch in print statement
by Paul Menzel (Code Review) 16 May '21

16 May '21

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54343 ) Change subject: cpu/x86/smm: Fix u32 type mismatch in print statement ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Hmm, worked on my system: ``` CC ramstage/cpu/x86/smm/smm_module_loader.o src/cpu/x86/smm/smm_module_loader.c: In function 'smm_module_setup_stub': src/cpu/x86/smm/smm_module_loader.c:415:21: error: format '%u' expects argument of type 'unsigned int', but argument 4 has type 'long unsigned int' [-Werror=format=] printk(BIOS_DEBUG, "%s: stack_end = 0x%" PRIu32 "\n", ^~~~~~~~~~~~~~~~~~~~~ __func__, stub_params->stack_top - total_stack_size); ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ In file included from src/cpu/x86/smm/smm_module_loader.c:4: src/include/inttypes.h:27:18: note: format string is defined here #define PRIu32 "u" src/cpu/x86/smm/smm_module_loader.c: At top level: cc1: error: unrecognized command line option '-Wno-address-of-packed-member' [-Werror] ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/54343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib504bc5e5b19f62d4702b7f485522a2ee3d26685 Gerrit-Change-Number: 54343 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 16 May 2021 18:58:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add configurable value for UsbTcPortEn
by Sridhar Siricilla (Code Review) 16 May '21

16 May '21

Attention is currently required from: Selma Bensaid, Tim Wawrzynczak, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54334 ) Change subject: soc/intel/alderlake: Add configurable value for UsbTcPortEn ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/54334/comment/cb2fcd7d_1732465f PS2, Line 131: UsbTcPortEn > `UsbTcPortEn` […] The UsbTcPortEn mask is implemented in the FSPv2172. Hence, it will be available when the FSPv2172 is integrated. -- To view, visit https://review.coreboot.org/c/coreboot/+/54334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5cd0690945b9296c105ade2d99f68bbf0ee22bd Gerrit-Change-Number: 54334 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.corp-partner.google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 16 May 2021 18:38:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/smm: Fix u32 type mismatch in print statement
by Paul Menzel (Code Review) 16 May '21

16 May '21

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54343 ) Change subject: cpu/x86/smm: Fix u32 type mismatch in print statement ...................................................................... cpu/x86/smm: Fix u32 type mismatch in print statement CC ramstage/cpu/x86/smm/smm_module_loader.o src/cpu/x86/smm/smm_module_loader.c:415:42: error: format '%lx' expects argument of type 'long unsigned int', but argument 4 has type 'u32' {aka 'unsigned int'} [-Werror=format=] 415 | printk(BIOS_DEBUG, "%s: stack_end = 0x%lx\n", | ~~^ | | | long unsigned int | %x 416 | __func__, stub_params->stack_top - total_stack_size); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | | | u32 {aka unsigned int} Fixes: afb7a814 ("cpu/x86/smm: Introduce SMM module loader version 2") Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Change-Id: Ib504bc5e5b19f62d4702b7f485522a2ee3d26685 --- M src/cpu/x86/smm/smm_module_loader.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/54343/1 diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index ecdd493..1ca60a6 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -412,7 +412,7 @@ const size_t total_stack_size = params->num_concurrent_stacks * params->per_cpu_stack_size; - printk(BIOS_DEBUG, "%s: stack_end = 0x%lx\n", + printk(BIOS_DEBUG, "%s: stack_end = 0x%" PRIu32 "\n", __func__, stub_params->stack_top - total_stack_size); printk(BIOS_DEBUG, "%s: stack_top = 0x%x\n", __func__, stub_params->stack_top); -- To view, visit https://review.coreboot.org/c/coreboot/+/54343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib504bc5e5b19f62d4702b7f485522a2ee3d26685 Gerrit-Change-Number: 54343 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newchange

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