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Change in coreboot[master]: mb/asus/p8x7x: Turn P8Z77-M PRO into a variant of P8x7x baseboard
by Bill XIE (Code Review) 16 May '21

16 May '21

Attention is currently required from: Bill XIE. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54335 to look at the new patch set (#2). Change subject: mb/asus/p8x7x: Turn P8Z77-M PRO into a variant of P8x7x baseboard ...................................................................... mb/asus/p8x7x: Turn P8Z77-M PRO into a variant of P8x7x baseboard Other variants would be added later. MAINBOARD_HAS_TPM1 should not be selected, since the module is replaceable. Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Change-Id: Iaf0bd4c993debe4d5d7ca695473438bd4c954290 --- A src/mainboard/asus/p8x7x/Kconfig R src/mainboard/asus/p8x7x/Kconfig.name A src/mainboard/asus/p8x7x/Makefile.inc R src/mainboard/asus/p8x7x/acpi/ec.asl R src/mainboard/asus/p8x7x/acpi/platform.asl R src/mainboard/asus/p8x7x/acpi/superio.asl A src/mainboard/asus/p8x7x/board_info.txt R src/mainboard/asus/p8x7x/cmos.default R src/mainboard/asus/p8x7x/cmos.layout A src/mainboard/asus/p8x7x/devicetree.cb R src/mainboard/asus/p8x7x/dsdt.asl A src/mainboard/asus/p8x7x/hda_verb.c R src/mainboard/asus/p8x7x/variants/z77-m_pro/acpi_tables.c A src/mainboard/asus/p8x7x/variants/z77-m_pro/board_info.txt R src/mainboard/asus/p8x7x/variants/z77-m_pro/data.vbt R src/mainboard/asus/p8x7x/variants/z77-m_pro/early_init.c R src/mainboard/asus/p8x7x/variants/z77-m_pro/gma-mainboard.ads R src/mainboard/asus/p8x7x/variants/z77-m_pro/gpio.c R src/mainboard/asus/p8x7x/variants/z77-m_pro/hda_verb.c R src/mainboard/asus/p8x7x/variants/z77-m_pro/mainboard.c A src/mainboard/asus/p8x7x/variants/z77-m_pro/overridetree.cb D src/mainboard/asus/p8z77-m_pro/Kconfig D src/mainboard/asus/p8z77-m_pro/Makefile.inc D src/mainboard/asus/p8z77-m_pro/board_info.txt D src/mainboard/asus/p8z77-m_pro/devicetree.cb 25 files changed, 184 insertions(+), 139 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/54335/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54335 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf0bd4c993debe4d5d7ca695473438bd4c954290 Gerrit-Change-Number: 54335 Gerrit-PatchSet: 2 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/asus/p8x7x: Add P8Z77-V as a variant of P8x7x
by Bill XIE (Code Review) 16 May '21

16 May '21

Attention is currently required from: Bill XIE. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54338 to look at the new patch set (#2). Change subject: mb/asus/p8x7x: Add P8Z77-V as a variant of P8x7x ...................................................................... mb/asus/p8x7x: Add P8Z77-V as a variant of P8x7x Tested: - PS/2 keyboard with SeaBIOS - Integrated NIC - S3 Suspend to RAM - USB2 on rear - USB3 (Z77's and Asmedia's works) - Integrated SATA - CPU Temp sensors (tested PSensor on GNU/Linux) - TPM on TPM-header (tested tpm-tools with TPM 1.2 Infineon SLB9635TT12) - Native raminit - Integrated graphics with both libgfxinit (VGA/DVI-D/HDMI tested and working) - PCIe GPU in PCIe-16x/8x slots (tested using an S3 Matrix) - Debug output from serial port - Atheros AR9485 adapted with Wi-Fi Go! Adapter - Default PCIe config Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Change-Id: Ic56ac0e5f93a6e818ef0666e41996718471b1cf6 --- A Documentation/mainboard/asus/p8z77-v.jpg A Documentation/mainboard/asus/p8z77-v.md M Documentation/mainboard/index.md M src/mainboard/asus/p8x7x/Kconfig M src/mainboard/asus/p8x7x/Kconfig.name A src/mainboard/asus/p8x7x/variants/z77-v/acpi_tables.c A src/mainboard/asus/p8x7x/variants/z77-v/board_info.txt A src/mainboard/asus/p8x7x/variants/z77-v/data.vbt A src/mainboard/asus/p8x7x/variants/z77-v/early_init.c A src/mainboard/asus/p8x7x/variants/z77-v/gma-mainboard.ads A src/mainboard/asus/p8x7x/variants/z77-v/gpio.c A src/mainboard/asus/p8x7x/variants/z77-v/hda_verb.c A src/mainboard/asus/p8x7x/variants/z77-v/mainboard.c A src/mainboard/asus/p8x7x/variants/z77-v/overridetree.cb 14 files changed, 514 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/54338/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54338 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic56ac0e5f93a6e818ef0666e41996718471b1cf6 Gerrit-Change-Number: 54338 Gerrit-PatchSet: 2 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/asus/p8x7x: Use native ram init and depricate mrc.bin code
by Bill XIE (Code Review) 16 May '21

16 May '21

Attention is currently required from: Bill XIE. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54336 to look at the new patch set (#2). Change subject: mb/asus/p8x7x: Use native ram init and depricate mrc.bin code ...................................................................... mb/asus/p8x7x: Use native ram init and depricate mrc.bin code Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Change-Id: I79dc64c25cb36c630bf9994bf04a0dfe8654eb3c --- M src/mainboard/asus/p8x7x/Kconfig M src/mainboard/asus/p8x7x/cmos.default M src/mainboard/asus/p8x7x/cmos.layout M src/mainboard/asus/p8x7x/variants/z77-m_pro/early_init.c 4 files changed, 45 insertions(+), 214 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/54336/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54336 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79dc64c25cb36c630bf9994bf04a0dfe8654eb3c Gerrit-Change-Number: 54336 Gerrit-PatchSet: 2 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/asus/p8z77: Add P8Z77-V as a variant of P8x7x
by Bill XIE (Code Review) 16 May '21

16 May '21

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54338 ) Change subject: mb/asus/p8z77: Add P8Z77-V as a variant of P8x7x ...................................................................... mb/asus/p8z77: Add P8Z77-V as a variant of P8x7x Tested: - PS/2 keyboard with SeaBIOS - Integrated NIC - S3 Suspend to RAM - USB2 on rear - USB3 (Z77's and Asmedia's works) - Integrated SATA - CPU Temp sensors (tested PSensor on GNU/Linux) - TPM on TPM-header (tested tpm-tools with TPM 1.2 Infineon SLB9635TT12) - Native raminit - Integrated graphics with both libgfxinit (VGA/DVI-D/HDMI tested and working) - PCIe GPU in PCIe-16x/8x slots (tested using an S3 Matrix) - Debug output from serial port - Atheros AR9485 adapted with Wi-Fi Go! Adapter - Default PCIe config Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Change-Id: Ic56ac0e5f93a6e818ef0666e41996718471b1cf6 --- A Documentation/mainboard/asus/p8z77-v.jpg A Documentation/mainboard/asus/p8z77-v.md M Documentation/mainboard/index.md M src/mainboard/asus/p8x7x/Kconfig M src/mainboard/asus/p8x7x/Kconfig.name A src/mainboard/asus/p8x7x/variants/z77-v/acpi_tables.c A src/mainboard/asus/p8x7x/variants/z77-v/board_info.txt A src/mainboard/asus/p8x7x/variants/z77-v/data.vbt A src/mainboard/asus/p8x7x/variants/z77-v/early_init.c A src/mainboard/asus/p8x7x/variants/z77-v/gma-mainboard.ads A src/mainboard/asus/p8x7x/variants/z77-v/gpio.c A src/mainboard/asus/p8x7x/variants/z77-v/hda_verb.c A src/mainboard/asus/p8x7x/variants/z77-v/mainboard.c A src/mainboard/asus/p8x7x/variants/z77-v/overridetree.cb 14 files changed, 514 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/54338/1 diff --git a/Documentation/mainboard/asus/p8z77-v.jpg b/Documentation/mainboard/asus/p8z77-v.jpg new file mode 100644 index 0000000..00f3c68 --- /dev/null +++ b/Documentation/mainboard/asus/p8z77-v.jpg Binary files differ diff --git a/Documentation/mainboard/asus/p8z77-v.md b/Documentation/mainboard/asus/p8z77-v.md new file mode 100644 index 0000000..0f4b649 --- /dev/null +++ b/Documentation/mainboard/asus/p8z77-v.md @@ -0,0 +1,120 @@ +# ASUS P8Z77-V + +This page describes how to run coreboot on the [ASUS P8Z77-V] + +## Flashing coreboot + +```eval_rst ++---------------------+----------------+ +| Type | Value | ++=====================+================+ +| Socketed flash | yes | ++---------------------+----------------+ +| Model | W25Q64FVA1Q | ++---------------------+----------------+ +| Size | 8 MiB | ++---------------------+----------------+ +| Package | DIP-8 | ++---------------------+----------------+ +| Write protection | yes | ++---------------------+----------------+ +| Dual BIOS feature | no | ++---------------------+----------------+ +| Internal flashing | yes | ++---------------------+----------------+ +``` + +The flash IC is located between the black and white PCI Express x16 slots (circled): +![](p8z77-v.jpg) + +### Internal programming + +The main SPI flash cannot be written because Asus disables BIOSWE and +enables BLE/SMM_BWP flags in BIOS_CNTL for their latest bioses. +An external programmer is required. You must flash standalone, +flashing in-circuit doesn't work. The flash chip is socketed, so it's +easy to remove and reflash. + +## Working + +- PS/2 keyboard with SeaBIOS + +- Integrated NIC + +- S3 Suspend to RAM + +- USB2 on rear + +- USB3 (Z77's and Asmedia's works) + +- Integrated SATA + +- CPU Temp sensors (tested PSensor on GNU/Linux) + +- TPM on TPM-header (tested tpm-tools with TPM 1.2 Infineon SLB9635TT12) + +- Native raminit + +- Integrated graphics with both libgfxinit (VGA/DVI-D/HDMI tested and working) + +- PCIe GPU in PCIe-16x/8x slots (tested using an S3 Matrix) + +- Debug output from serial port + +- Atheros AR9485 half-height mini PCIe WNIC adapted with Wi-Fi Go! Adapter + +- Default PCIe config (PCIEX_16_3 as 1x, PCIe Port 4 to ASM1061 SATA, see below + for other potential options) + +## Untested + +- EHCI debugging +- S/PDIF audio +- PS/2 mouse + +## Not working + +- PCIEX_1_2 (expected under default PCIe config) +- Other PCIe configs (see below) + +## PCIe config +On asus vendor firmware, other than the default config already supported here, +there remain another two configs: "PCIEX_16_3 as x4, with PCIEX_1_1, PCIEX_1_2 +and onboard ASM1061 disabled" and "PCIEX_16_3 as x1, but PCIe Port 4 to PCIEX_1_2, +with onboard ASM1061 disabled". + +Configuring PCIEX_16_3 as x4 needs to program 0x3 to the LSB of PCHSTRP9, but +also needs to config GPIOs in the superio chip different than the default config +in this board's override tree. + +Configuring PCIe Port 4 to PCIEX_1_2 needs to config GPIOs in the superio chip +different than the default config. + +I have tried a lot, but sadly I am unable to produce the same result as the vendor +firmware. + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | ++------------------+--------------------------------------------------+ +| Southbridge | bd82x6x | ++------------------+--------------------------------------------------+ +| CPU | model_206ax | ++------------------+--------------------------------------------------+ +| Super I/O | Nuvoton NCT6779D | ++------------------+--------------------------------------------------+ +| EC | None | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +## Extra resources + +- [Flash chip datasheet][W25Q64FVA1Q] + +[ASUS P8Z77-V]: https://www.asus.com/supportonly/p8z77v/helpdesk_knowledge/ +[W25Q64FVA1Q]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf +[flashrom]: https://flashrom.org/Flashrom diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 3307271..06286d4 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -22,6 +22,7 @@ - [P8H61-M LX](asus/p8h61-m_lx.md) - [P8H61-M Pro](asus/p8h61-m_pro.md) - [P8Z77-M Pro](asus/p8z77-m_pro.md) +- [P8Z77-V](asus/p8z77-v.md) ## Cavium diff --git a/src/mainboard/asus/p8x7x/Kconfig b/src/mainboard/asus/p8x7x/Kconfig index 163e337..c758ff7 100644 --- a/src/mainboard/asus/p8x7x/Kconfig +++ b/src/mainboard/asus/p8x7x/Kconfig @@ -1,6 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only -if BOARD_ASUS_P8Z77_M_PRO || BOARD_ASUS_P8Z77_V_LX2 +if BOARD_ASUS_P8Z77_M_PRO || BOARD_ASUS_P8Z77_V_LX2 || BOARD_ASUS_P8Z77_V config BOARD_SPECIFIC_OPTIONS def_bool y @@ -11,7 +11,7 @@ select NORTHBRIDGE_INTEL_SANDYBRIDGE select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 - select MAINBOARD_HAS_LPC_TPM if BOARD_ASUS_P8Z77_M_PRO + select MAINBOARD_HAS_LPC_TPM if BOARD_ASUS_P8Z77_M_PRO || BOARD_ASUS_P8Z77_V select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select MAINBOARD_HAS_LIBGFXINIT @@ -19,7 +19,8 @@ select SUPERIO_NUVOTON_NCT6779D select USE_NATIVE_RAMINIT # for ASM1061 eSATA - select DRIVERS_ASMEDIA_ASPM_BLACKLIST if BOARD_ASUS_P8Z77_M_PRO + select DRIVERS_ASMEDIA_ASPM_BLACKLIST if BOARD_ASUS_P8Z77_M_PRO || BOARD_ASUS_P8Z77_V + select MAINBOARD_USES_IFD_GBE_REGION if BOARD_ASUS_P8Z77_V config MAINBOARD_DIR string @@ -29,14 +30,16 @@ string default "z77-m_pro" if BOARD_ASUS_P8Z77_M_PRO default "z77-v_lx2" if BOARD_ASUS_P8Z77_V_LX2 + default "z77-v" if BOARD_ASUS_P8Z77_V config MAINBOARD_PART_NUMBER string default "P8Z77-M PRO" if BOARD_ASUS_P8Z77_M_PRO default "P8Z77-V LX2" if BOARD_ASUS_P8Z77_V_LX2 + default "P8Z77-V" if BOARD_ASUS_P8Z77_V config OVERRIDE_DEVICETREE string default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" -endif # BOARD_ASUS_P8Z77_M_PRO || BOARD_ASUS_P8Z77_V_LX2 +endif # BOARD_ASUS_P8Z77_M_PRO || BOARD_ASUS_P8Z77_V_LX2 || BOARD_ASUS_P8Z77_V diff --git a/src/mainboard/asus/p8x7x/Kconfig.name b/src/mainboard/asus/p8x7x/Kconfig.name index 2777435..fca045a 100644 --- a/src/mainboard/asus/p8x7x/Kconfig.name +++ b/src/mainboard/asus/p8x7x/Kconfig.name @@ -5,3 +5,6 @@ config BOARD_ASUS_P8Z77_V_LX2 bool "P8Z77-V LX2" + +config BOARD_ASUS_P8Z77_V + bool "P8Z77-V" diff --git a/src/mainboard/asus/p8x7x/variants/z77-v/acpi_tables.c b/src/mainboard/asus/p8x7x/variants/z77-v/acpi_tables.c new file mode 100644 index 0000000..8f4f83b --- /dev/null +++ b/src/mainboard/asus/p8x7x/variants/z77-v/acpi_tables.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_gnvs.h> +#include <soc/nvs.h> + +void mainboard_fill_gnvs(struct global_nvs *gnvs) +{ + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; +} diff --git a/src/mainboard/asus/p8x7x/variants/z77-v/board_info.txt b/src/mainboard/asus/p8x7x/variants/z77-v/board_info.txt new file mode 100644 index 0000000..135878b --- /dev/null +++ b/src/mainboard/asus/p8x7x/variants/z77-v/board_info.txt @@ -0,0 +1,3 @@ +Board name: ASUS P8Z77-V +Board URL: https://www.asus.com/supportonly/p8z77v/helpdesk_knowledge/ +Release year: 2013 diff --git a/src/mainboard/asus/p8x7x/variants/z77-v/data.vbt b/src/mainboard/asus/p8x7x/variants/z77-v/data.vbt new file mode 100644 index 0000000..37fa165 --- /dev/null +++ b/src/mainboard/asus/p8x7x/variants/z77-v/data.vbt Binary files differ diff --git a/src/mainboard/asus/p8x7x/variants/z77-v/early_init.c b/src/mainboard/asus/p8x7x/variants/z77-v/early_init.c new file mode 100644 index 0000000..825da64 --- /dev/null +++ b/src/mainboard/asus/p8x7x/variants/z77-v/early_init.c @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/pnp_ops.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6779d/nct6779d.h> +#include <option.h> + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI) + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 2, 0 }, + { 1, 2, 0 }, + { 1, 2, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 2, 2 }, + { 1, 2, 3 }, + { 1, 2, 3 }, + { 1, 2, 4 }, + { 1, 0, 4 }, + { 1, 2, 6 }, + { 1, 2, 5 }, + { 1, 2, 5 }, + { 1, 2, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin states */ + pnp_write_config(GLOBAL_DEV, 0x1a, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x40); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x00); + + /* Power RAM in S3 */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x10); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Enable UART */ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/asus/p8x7x/variants/z77-v/gma-mainboard.ads b/src/mainboard/asus/p8x7x/variants/z77-v/gma-mainboard.ads new file mode 100644 index 0000000..83a87be --- /dev/null +++ b/src/mainboard/asus/p8x7x/variants/z77-v/gma-mainboard.ads @@ -0,0 +1,19 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + HDMI1, + HDMI2, + HDMI3, + Analog, + Others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/p8x7x/variants/z77-v/gpio.c b/src/mainboard/asus/p8x7x/variants/z77-v/gpio.c new file mode 100644 index 0000000..5d5e4e7 --- /dev/null +++ b/src/mainboard/asus/p8x7x/variants/z77-v/gpio.c @@ -0,0 +1,181 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio48 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/p8x7x/variants/z77-v/hda_verb.c b/src/mainboard/asus/p8x7x/variants/z77-v/hda_verb.c new file mode 100644 index 0000000..e431593 --- /dev/null +++ b/src/mainboard/asus/p8x7x/variants/z77-v/hda_verb.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0892, /* Codec Vendor / Device ID: Realtek ALC892 */ + 0x104384fb, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x104384fb), + AZALIA_PIN_CFG(0, 0x11, 0x99430140), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, 0x01012014), + AZALIA_PIN_CFG(0, 0x18, 0x01a19850), + AZALIA_PIN_CFG(0, 0x19, 0x02a19c60), + AZALIA_PIN_CFG(0, 0x1a, 0x0181305f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4005e601), + AZALIA_PIN_CFG(0, 0x1e, 0x01456130), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + + 0x80862806, /* Codec Vendor / Device ID: Intel HDMI */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x58560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/p8x7x/variants/z77-v/mainboard.c b/src/mainboard/asus/p8x7x/variants/z77-v/mainboard.c new file mode 100644 index 0000000..ac992f6 --- /dev/null +++ b/src/mainboard/asus/p8x7x/variants/z77-v/mainboard.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, + 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable +}; diff --git a/src/mainboard/asus/p8x7x/variants/z77-v/overridetree.cb b/src/mainboard/asus/p8x7x/variants/z77-v/overridetree.cb new file mode 100644 index 0000000..2a3fec7 --- /dev/null +++ b/src/mainboard/asus/p8x7x/variants/z77-v/overridetree.cb @@ -0,0 +1,57 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/sandybridge + device domain 0x0 on + device pci 01.1 on end # PCIEX_16_2 + chip southbridge/intel/bd82x6x + register "pcie_port_coalesce" = "1" + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1c.0 on end # PCIe Port 1 PCIEX_16_3 (electrical x4) + device pci 1c.1 on end # PCIe Port 2 PCIEX_1_1 + device pci 1c.3 on end # PCIe Port 4 ASM1061 SATA or PCIEX_1_2 + device pci 1c.4 on end # PCIe Port 5 ASM1083 PCI Bridge + device pci 1c.6 on end # PCIe Port 7 Wi-Fi Go! + device pci 1c.7 on end # PCIe Port 8 ASM1042 USB3 + device pci 1f.0 on # LPC bridge + chip superio/nuvoton/nct6779d + device pnp 2e.2 on # UART A + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 on # PS2 KBC + # KBC 12Mhz/A20 speed/sw KBRST + drq 0xf0 = 0x82 + end + device pnp 2e.7 off end # GPIOs 6-8 + device pnp 2e.8 off end # WDT1 GPIO 0-1 + device pnp 2e.108 on end # GPIO0-1 + device pnp 2e.109 on end # GPIO1 + device pnp 2e.209 on # GPIO2 + drq 0xe0 = 0xdf + end + device pnp 2e.309 on end # GPIO3 + device pnp 2e.509 on # GPIO5 + drq 0xf4 = 0xfc + end + device pnp 2e.a on # ACPI + drq 0xe3 = 0x04 # Thermal shutdown event issued + drq 0xe7 = 0x11 # Enable 3VSBS to power RAM on S3 + drq 0xf2 = 0x5d # Enable PME + end + device pnp 2e.b on # H/W Monitor, FP LED + io 0x60 = 0x290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.f on # Push-pull/Open-drain + drq 0xe4 = 0xfc # GP5 PP + drq 0xe6 = 0x7f # GP7 PP + end + end + chip drivers/pc80/tpm + device pnp c31.0 on end # TPM + end + end + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/54338 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic56ac0e5f93a6e818ef0666e41996718471b1cf6 Gerrit-Change-Number: 54338 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asus/p8z77: Turn P8Z77-V LX2 into a variant of P8x7x baseboard
by Bill XIE (Code Review) 16 May '21

16 May '21

Attention is currently required from: Angel Pons. Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54337 ) Change subject: mb/asus/p8z77: Turn P8Z77-V LX2 into a variant of P8x7x baseboard ...................................................................... mb/asus/p8z77: Turn P8Z77-V LX2 into a variant of P8x7x baseboard Other variants would be added later. Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Change-Id: Id9a7f1069233b43eb4a046f2e61c7a72fec7e960 --- M src/mainboard/asus/p8x7x/Kconfig M src/mainboard/asus/p8x7x/Kconfig.name M src/mainboard/asus/p8x7x/variants/z77-m_pro/overridetree.cb R src/mainboard/asus/p8x7x/variants/z77-v_lx2/acpi_tables.c A src/mainboard/asus/p8x7x/variants/z77-v_lx2/board_info.txt R src/mainboard/asus/p8x7x/variants/z77-v_lx2/data.vbt R src/mainboard/asus/p8x7x/variants/z77-v_lx2/early_init.c R src/mainboard/asus/p8x7x/variants/z77-v_lx2/gma-mainboard.ads R src/mainboard/asus/p8x7x/variants/z77-v_lx2/gpio.c R src/mainboard/asus/p8x7x/variants/z77-v_lx2/hda_verb.c A src/mainboard/asus/p8x7x/variants/z77-v_lx2/mainboard.c A src/mainboard/asus/p8x7x/variants/z77-v_lx2/overridetree.cb D src/mainboard/asus/p8z77-v_lx2/Kconfig D src/mainboard/asus/p8z77-v_lx2/Kconfig.name D src/mainboard/asus/p8z77-v_lx2/Makefile.inc D src/mainboard/asus/p8z77-v_lx2/acpi/ec.asl D src/mainboard/asus/p8z77-v_lx2/acpi/platform.asl D src/mainboard/asus/p8z77-v_lx2/acpi/superio.asl D src/mainboard/asus/p8z77-v_lx2/board_info.txt D src/mainboard/asus/p8z77-v_lx2/cmos.default D src/mainboard/asus/p8z77-v_lx2/cmos.layout D src/mainboard/asus/p8z77-v_lx2/devicetree.cb D src/mainboard/asus/p8z77-v_lx2/dsdt.asl 23 files changed, 53 insertions(+), 274 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/54337/1 diff --git a/src/mainboard/asus/p8x7x/Kconfig b/src/mainboard/asus/p8x7x/Kconfig index 4cfd3c4..163e337 100644 --- a/src/mainboard/asus/p8x7x/Kconfig +++ b/src/mainboard/asus/p8x7x/Kconfig @@ -1,6 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only -if BOARD_ASUS_P8Z77_M_PRO +if BOARD_ASUS_P8Z77_M_PRO || BOARD_ASUS_P8Z77_V_LX2 config BOARD_SPECIFIC_OPTIONS def_bool y @@ -28,13 +28,15 @@ config VARIANT_DIR string default "z77-m_pro" if BOARD_ASUS_P8Z77_M_PRO + default "z77-v_lx2" if BOARD_ASUS_P8Z77_V_LX2 config MAINBOARD_PART_NUMBER string default "P8Z77-M PRO" if BOARD_ASUS_P8Z77_M_PRO + default "P8Z77-V LX2" if BOARD_ASUS_P8Z77_V_LX2 config OVERRIDE_DEVICETREE string default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" -endif # BOARD_ASUS_P8Z77_M_PRO +endif # BOARD_ASUS_P8Z77_M_PRO || BOARD_ASUS_P8Z77_V_LX2 diff --git a/src/mainboard/asus/p8x7x/Kconfig.name b/src/mainboard/asus/p8x7x/Kconfig.name index 372ec4a..2777435 100644 --- a/src/mainboard/asus/p8x7x/Kconfig.name +++ b/src/mainboard/asus/p8x7x/Kconfig.name @@ -2,3 +2,6 @@ config BOARD_ASUS_P8Z77_M_PRO bool "P8Z77-M PRO" + +config BOARD_ASUS_P8Z77_V_LX2 + bool "P8Z77-V LX2" diff --git a/src/mainboard/asus/p8x7x/variants/z77-m_pro/overridetree.cb b/src/mainboard/asus/p8x7x/variants/z77-m_pro/overridetree.cb index e85e647..0edc99b 100644 --- a/src/mainboard/asus/p8x7x/variants/z77-m_pro/overridetree.cb +++ b/src/mainboard/asus/p8x7x/variants/z77-m_pro/overridetree.cb @@ -5,7 +5,7 @@ chip southbridge/intel/bd82x6x register "gen4_dec" = "0x0000ff29" register "pcie_port_coalesce" = "1" - device pci 1c.0 on end # PCIe Port 1 PCIEX_16_3 + device pci 1c.0 on end # PCIe Port 1 PCIEX_16_3 (electrical x4) device pci 1c.1 on end # PCIe Port 2 RTL8111F device pci 1c.5 on end # PCIe Port 6 ASM1042 USB3 device pci 1c.6 on end # PCIe Port 7 ASM1061 eSATA diff --git a/src/mainboard/asus/p8z77-v_lx2/acpi_tables.c b/src/mainboard/asus/p8x7x/variants/z77-v_lx2/acpi_tables.c similarity index 100% rename from src/mainboard/asus/p8z77-v_lx2/acpi_tables.c rename to src/mainboard/asus/p8x7x/variants/z77-v_lx2/acpi_tables.c diff --git a/src/mainboard/asus/p8x7x/variants/z77-v_lx2/board_info.txt b/src/mainboard/asus/p8x7x/variants/z77-v_lx2/board_info.txt new file mode 100644 index 0000000..1c08708 --- /dev/null +++ b/src/mainboard/asus/p8x7x/variants/z77-v_lx2/board_info.txt @@ -0,0 +1,3 @@ +Board name: ASUS P8Z77-V LX2 +Board URL: https://www.asus.com/uk/Motherboards/P8Z77V_LX2/ +Release year: 2013 diff --git a/src/mainboard/asus/p8z77-v_lx2/data.vbt b/src/mainboard/asus/p8x7x/variants/z77-v_lx2/data.vbt similarity index 100% rename from src/mainboard/asus/p8z77-v_lx2/data.vbt rename to src/mainboard/asus/p8x7x/variants/z77-v_lx2/data.vbt Binary files differ diff --git a/src/mainboard/asus/p8z77-v_lx2/early_init.c b/src/mainboard/asus/p8x7x/variants/z77-v_lx2/early_init.c similarity index 100% rename from src/mainboard/asus/p8z77-v_lx2/early_init.c rename to src/mainboard/asus/p8x7x/variants/z77-v_lx2/early_init.c diff --git a/src/mainboard/asus/p8z77-v_lx2/gma-mainboard.ads b/src/mainboard/asus/p8x7x/variants/z77-v_lx2/gma-mainboard.ads similarity index 100% rename from src/mainboard/asus/p8z77-v_lx2/gma-mainboard.ads rename to src/mainboard/asus/p8x7x/variants/z77-v_lx2/gma-mainboard.ads diff --git a/src/mainboard/asus/p8z77-v_lx2/gpio.c b/src/mainboard/asus/p8x7x/variants/z77-v_lx2/gpio.c similarity index 100% rename from src/mainboard/asus/p8z77-v_lx2/gpio.c rename to src/mainboard/asus/p8x7x/variants/z77-v_lx2/gpio.c diff --git a/src/mainboard/asus/p8z77-v_lx2/hda_verb.c b/src/mainboard/asus/p8x7x/variants/z77-v_lx2/hda_verb.c similarity index 100% rename from src/mainboard/asus/p8z77-v_lx2/hda_verb.c rename to src/mainboard/asus/p8x7x/variants/z77-v_lx2/hda_verb.c diff --git a/src/mainboard/asus/p8x7x/variants/z77-v_lx2/mainboard.c b/src/mainboard/asus/p8x7x/variants/z77-v_lx2/mainboard.c new file mode 100644 index 0000000..ac992f6 --- /dev/null +++ b/src/mainboard/asus/p8x7x/variants/z77-v_lx2/mainboard.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, + 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable +}; diff --git a/src/mainboard/asus/p8x7x/variants/z77-v_lx2/overridetree.cb b/src/mainboard/asus/p8x7x/variants/z77-v_lx2/overridetree.cb new file mode 100644 index 0000000..da8d1ff --- /dev/null +++ b/src/mainboard/asus/p8x7x/variants/z77-v_lx2/overridetree.cb @@ -0,0 +1,26 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/sandybridge + device domain 0x0 on + chip southbridge/intel/bd82x6x + device pci 1c.0 on end # PCIe Port 1 PCIEX_16_2 (electrical x4) + device pci 1c.4 on end # PCIe Port 5 RTL8111 GbE NIC + device pci 1c.5 on end # RP #6: ASM1083 PCI Bridge + device pci 1c.6 on end # RP #7: PCIEX1_1 + device pci 1c.7 on end # RP #8: PCIEX1_2 + device pci 1f.0 on # LPC bridge + chip superio/nuvoton/nct6779d + device pnp 2e.2 on # UART A + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.209 on # GPIO2 + irq 0xe0 = 0xff + end + device pnp 2e.a on # ACPI + end + end + end + end + end +end diff --git a/src/mainboard/asus/p8z77-v_lx2/Kconfig b/src/mainboard/asus/p8z77-v_lx2/Kconfig deleted file mode 100644 index 108d61a..0000000 --- a/src/mainboard/asus/p8z77-v_lx2/Kconfig +++ /dev/null @@ -1,29 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -if BOARD_ASUS_P8Z77_V_LX2 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select BOARD_ROMSIZE_KB_8192 - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select HAVE_CMOS_DEFAULT - select HAVE_OPTION_TABLE - select INTEL_GMA_HAVE_VBT - select MAINBOARD_HAS_LIBGFXINIT - select NORTHBRIDGE_INTEL_SANDYBRIDGE - select REALTEK_8168_RESET - select SERIRQ_CONTINUOUS_MODE - select SOUTHBRIDGE_INTEL_C216 - select SUPERIO_NUVOTON_NCT6779D - select USE_NATIVE_RAMINIT - -config MAINBOARD_DIR - string - default "asus/p8z77-v_lx2" - -config MAINBOARD_PART_NUMBER - string - default "P8Z77-V LX2" - -endif diff --git a/src/mainboard/asus/p8z77-v_lx2/Kconfig.name b/src/mainboard/asus/p8z77-v_lx2/Kconfig.name deleted file mode 100644 index 0dec75f..0000000 --- a/src/mainboard/asus/p8z77-v_lx2/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_ASUS_P8Z77_V_LX2 - bool "P8Z77-V LX2" diff --git a/src/mainboard/asus/p8z77-v_lx2/Makefile.inc b/src/mainboard/asus/p8z77-v_lx2/Makefile.inc deleted file mode 100644 index 7167e10..0000000 --- a/src/mainboard/asus/p8z77-v_lx2/Makefile.inc +++ /dev/null @@ -1,7 +0,0 @@ -bootblock-y += early_init.c -bootblock-y += gpio.c - -romstage-y += early_init.c -romstage-y += gpio.c - -ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/p8z77-v_lx2/acpi/ec.asl b/src/mainboard/asus/p8z77-v_lx2/acpi/ec.asl deleted file mode 100644 index e69de29..0000000 --- a/src/mainboard/asus/p8z77-v_lx2/acpi/ec.asl +++ /dev/null diff --git a/src/mainboard/asus/p8z77-v_lx2/acpi/platform.asl b/src/mainboard/asus/p8z77-v_lx2/acpi/platform.asl deleted file mode 100644 index 7da03bf..0000000 --- a/src/mainboard/asus/p8z77-v_lx2/acpi/platform.asl +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Method(_PTS, 1) -{ -} - -Method(_WAK, 1) -{ - Return(Package(){0, 0}) -} diff --git a/src/mainboard/asus/p8z77-v_lx2/acpi/superio.asl b/src/mainboard/asus/p8z77-v_lx2/acpi/superio.asl deleted file mode 100644 index f2b35ba..0000000 --- a/src/mainboard/asus/p8z77-v_lx2/acpi/superio.asl +++ /dev/null @@ -1 +0,0 @@ -#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/asus/p8z77-v_lx2/board_info.txt b/src/mainboard/asus/p8z77-v_lx2/board_info.txt deleted file mode 100644 index 79c36d6..0000000 --- a/src/mainboard/asus/p8z77-v_lx2/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Category: desktop -Board URL: https://www.asus.com/uk/Motherboards/P8Z77V_LX2/ -ROM package: DIP-8 -ROM protocol: SPI -ROM socketed: y -Flashrom support: y -Release year: 2013 diff --git a/src/mainboard/asus/p8z77-v_lx2/cmos.default b/src/mainboard/asus/p8z77-v_lx2/cmos.default deleted file mode 100644 index c7aa620..0000000 --- a/src/mainboard/asus/p8z77-v_lx2/cmos.default +++ /dev/null @@ -1,6 +0,0 @@ -boot_option=Fallback -debug_level=Debug -nmi=Disable -power_on_after_fail=Disable -sata_mode=AHCI -gfx_uma_size=64M diff --git a/src/mainboard/asus/p8z77-v_lx2/cmos.layout b/src/mainboard/asus/p8z77-v_lx2/cmos.layout deleted file mode 100644 index 0f9de5e..0000000 --- a/src/mainboard/asus/p8z77-v_lx2/cmos.layout +++ /dev/null @@ -1,86 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -# ----------------------------------------------------------------- -entries - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 2 boot_option -388 4 h 0 reboot_counter - -# ----------------------------------------------------------------- -# coreboot config options: console -395 4 e 3 debug_level - -# coreboot config options: southbridge -408 1 e 1 nmi - -409 2 e 4 power_on_after_fail -411 2 e 5 sata_mode - -# coreboot config options: northbridge -416 5 e 6 gfx_uma_size - -# coreboot config options: check sums -984 16 h 0 check_sum - -# ----------------------------------------------------------------- - -enumerations -#ID value text - -# Generic on/off enum -1 0 Disable -1 1 Enable - -# boot_option -2 0 Fallback -2 1 Normal - -# debug_level -3 0 Emergency -3 1 Alert -3 2 Critical -3 3 Error -3 4 Warning -3 5 Notice -3 6 Info -3 7 Debug -3 8 Spew - -# power_on_after_fail -4 0 Disable -4 1 Enable -4 2 Keep - -# sata_mode -5 0 AHCI -5 1 Compatible -5 2 Legacy - -# gfx_uma_size (Intel IGP Video RAM size) -6 0 32M -6 1 64M -6 2 96M -6 3 128M -6 4 160M -6 5 192M -6 6 224M -6 7 256M -6 8 288M -6 9 320M -6 10 352M -6 11 384M -6 12 416M -6 13 448M -6 14 480M -6 15 512M -6 16 1024M - -# ----------------------------------------------------------------- -checksums - -checksum 392 423 984 diff --git a/src/mainboard/asus/p8z77-v_lx2/devicetree.cb b/src/mainboard/asus/p8z77-v_lx2/devicetree.cb deleted file mode 100644 index 40f8e6d..0000000 --- a/src/mainboard/asus/p8z77-v_lx2/devicetree.cb +++ /dev/null @@ -1,97 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -chip northbridge/intel/sandybridge - device cpu_cluster 0 on - chip cpu/intel/model_206ax - register "acpi_c1" = "1" - register "acpi_c2" = "3" - register "acpi_c3" = "5" - device lapic 0 on end - device lapic 0xacac off end - end - end - device domain 0 on - subsystemid 0x1043 0x84ca inherit - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIEX16_1 - device pci 02.0 on end # iGPU - - chip southbridge/intel/bd82x6x - register "c2_latency" = "0x0065" - register "gen1_dec" = "0x000c0291" - register "sata_interface_speed_support" = "0x3" - register "sata_port_map" = "0x3f" - register "spi_lvscc" = "0x2005" - register "spi_uvscc" = "0x2005" - register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" - register "xhci_switchable_ports" = "0x0000000f" - - device pci 14.0 on end # xHCI - device pci 16.0 on end # MEI #1 - device pci 16.1 off end # MEI #2 - device pci 16.2 off end # ME IDE-R - device pci 16.3 off end # ME KT - device pci 19.0 off end # Intel GbE - device pci 1a.0 on end # EHCI #2 - device pci 1b.0 on end # HD Audio - - device pci 1c.0 on end # RP #1: PCIEX16_2 (electrical x4) - device pci 1c.1 off end # RP #2: - device pci 1c.2 off end # RP #3: - device pci 1c.3 off end # RP #4: - device pci 1c.4 on end # RP #5: RTL8111 GbE NIC - device pci 1c.5 on end # RP #6: ASM1083 PCI Bridge - device pci 1c.6 on end # RP #7: PCIEX1_1 - device pci 1c.7 on end # RP #8: PCIEX1_2 - - device pci 1d.0 on end # EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge - chip superio/nuvoton/nct6779d - device pnp 2e.1 off end # Parallel - device pnp 2e.2 on # UART A - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off end # UART B, IR - device pnp 2e.5 on # Keyboard - io 0x60 = 0x0060 - io 0x62 = 0x0064 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off end # CIR - device pnp 2e.7 off end # GPIO6-8 - device pnp 2e.8 off end # WDT1, GPIO0, GPIO1 - device pnp 2e.108 off end # GPIO0 - device pnp 2e.9 off end # GPIO8 - device pnp 2e.109 off end # GPIO1 - device pnp 2e.209 on # GPIO2 - irq 0xe0 = 0xff - end - device pnp 2e.309 off end # GPIO3 - device pnp 2e.409 off end # GPIO4 - device pnp 2e.509 off end # GPIO5 - device pnp 2e.609 off end # GPIO6 - device pnp 2e.709 off end # GPIO7 - device pnp 2e.a on end # ACPI - device pnp 2e.b on # H/W Monitor, FP LED - io 0x60 = 0x0290 - io 0x62 = 0 - irq 0x70 = 0 - end - device pnp 2e.d off end # WDT1 - device pnp 2e.e off end # CIR Wake-up - device pnp 2e.f off end # Push-pull/Open-drain - device pnp 2e.14 off end # Port 80 UART - device pnp 2e.16 off end # Deep Sleep - end - end - device pci 1f.2 on end # SATA (AHCI) - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA (Legacy) - device pci 1f.6 off end # Thermal - end - end -end diff --git a/src/mainboard/asus/p8z77-v_lx2/dsdt.asl b/src/mainboard/asus/p8z77-v_lx2/dsdt.asl deleted file mode 100644 index e8e2b3a..0000000 --- a/src/mainboard/asus/p8z77-v_lx2/dsdt.asl +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi.h> - -DefinitionBlock( - "dsdt.aml", - "DSDT", - ACPI_DSDT_REV_2, - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20141018 /* OEM revision */ -) -{ - #include <acpi/dsdt_top.asl> - #include "acpi/platform.asl" - #include <cpu/intel/common/acpi/cpu.asl> - #include <southbridge/intel/common/acpi/platform.asl> - #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <southbridge/intel/common/acpi/sleepstates.asl> - - Device (\_SB.PCI0) - { - #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> - #include <southbridge/intel/bd82x6x/acpi/pch.asl> - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/54337 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9a7f1069233b43eb4a046f2e61c7a72fec7e960 Gerrit-Change-Number: 54337 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/asus/p8z77: Use native ram init and depricate mrc.bin code
by Bill XIE (Code Review) 16 May '21

16 May '21

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54336 ) Change subject: mb/asus/p8z77: Use native ram init and depricate mrc.bin code ...................................................................... mb/asus/p8z77: Use native ram init and depricate mrc.bin code Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Change-Id: I79dc64c25cb36c630bf9994bf04a0dfe8654eb3c --- M src/mainboard/asus/p8x7x/Kconfig M src/mainboard/asus/p8x7x/cmos.default M src/mainboard/asus/p8x7x/cmos.layout M src/mainboard/asus/p8x7x/variants/z77-m_pro/early_init.c 4 files changed, 45 insertions(+), 214 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/54336/1 diff --git a/src/mainboard/asus/p8x7x/Kconfig b/src/mainboard/asus/p8x7x/Kconfig index e6e9bf7..4cfd3c4 100644 --- a/src/mainboard/asus/p8x7x/Kconfig +++ b/src/mainboard/asus/p8x7x/Kconfig @@ -17,6 +17,7 @@ select MAINBOARD_HAS_LIBGFXINIT select INTEL_GMA_HAVE_VBT select SUPERIO_NUVOTON_NCT6779D + select USE_NATIVE_RAMINIT # for ASM1061 eSATA select DRIVERS_ASMEDIA_ASPM_BLACKLIST if BOARD_ASUS_P8Z77_M_PRO diff --git a/src/mainboard/asus/p8x7x/cmos.default b/src/mainboard/asus/p8x7x/cmos.default index 6811b0b..c7aa620 100644 --- a/src/mainboard/asus/p8x7x/cmos.default +++ b/src/mainboard/asus/p8x7x/cmos.default @@ -1,11 +1,6 @@ -## SPDX-License-Identifier: GPL-2.0-only - boot_option=Fallback debug_level=Debug -gfx_uma_size=224M -nmi=Enable +nmi=Disable +power_on_after_fail=Disable sata_mode=AHCI -#usb3_xxxx options are only used with MRC blob, ignored else -usb3_mode=Enable -usb3_drv=Enable -usb3_streams=Enable +gfx_uma_size=64M diff --git a/src/mainboard/asus/p8x7x/cmos.layout b/src/mainboard/asus/p8x7x/cmos.layout index 3d717b4..0f9de5e 100644 --- a/src/mainboard/asus/p8x7x/cmos.layout +++ b/src/mainboard/asus/p8x7x/cmos.layout @@ -8,60 +8,24 @@ # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 3 boot_option +384 1 e 2 boot_option 388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 4 debug_level -#400 8 r 0 reserved for century byte +395 4 e 3 debug_level -# ----------------------------------------------------------------- # coreboot config options: southbridge - -# Non Maskable Interrupt(NMI) support, which is an interrupt that may -# occur on a RAM or unrecoverable error. 408 1 e 1 nmi -409 2 e 5 power_on_after_fail -411 1 e 6 sata_mode +409 2 e 4 power_on_after_fail +411 2 e 5 sata_mode -# ----------------------------------------------------------------- # coreboot config options: northbridge +416 5 e 6 gfx_uma_size -# gfx_uma_size -# Quantity of shared video memory the IGP can use -# -416 5 e 7 gfx_uma_size - -# ----------------------------------------------------------------- -# coreboot config options: usb3 - -# usb3_mode -# Controls how the motherboard's USB3 ports act at boot time -421 2 e 8 usb3_mode - -# usb3_drv -# Load (or not) pre-OS xHCI USB3 BIOS driver -# -423 1 e 1 usb3_drv - -# usb3_streams -# Streams can provide more speed (as they can use 64Kb packets), -# but they might cause incompatibilities with some devices. -# -424 1 e 1 usb3_streams - -# ----------------------------------------------------------------- -# Sandy/Ivy Bridge MRC Scrambler Seed values -# note: MUST NOT be covered by checksum! -464 32 r 0 mrc_scrambler_seed -496 32 r 0 mrc_scrambler_seed_s3 -528 16 r 0 mrc_scrambler_seed_chk - -# ----------------------------------------------------------------- # coreboot config options: check sums -544 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- @@ -73,78 +37,50 @@ 1 1 Enable # boot_option -3 0 Fallback -3 1 Normal +2 0 Fallback +2 1 Normal # debug_level -4 0 Emergency -4 1 Alert -4 2 Critical -4 3 Error -4 4 Warning -4 5 Notice -4 6 Info -4 7 Debug -4 8 Spew +3 0 Emergency +3 1 Alert +3 2 Critical +3 3 Error +3 4 Warning +3 5 Notice +3 6 Info +3 7 Debug +3 8 Spew # power_on_after_fail -5 0 Disable -5 1 Enable -5 2 Keep +4 0 Disable +4 1 Enable +4 2 Keep # sata_mode -6 0 AHCI -6 1 Compatible +5 0 AHCI +5 1 Compatible +5 2 Legacy # gfx_uma_size (Intel IGP Video RAM size) -7 0 32M -7 1 64M -7 2 96M -7 3 128M -7 4 160M -7 5 192M -7 6 224M -7 7 256M -7 8 288M -7 9 320M -7 10 352M -7 11 384M -7 12 416M -7 13 448M -7 14 480M -7 15 512M -7 16 544M -7 17 576M -7 18 608M -7 19 640M -7 20 672M -7 21 704M -7 22 736M -7 23 768M -7 24 800M -7 25 832M -7 26 864M -7 27 896M -7 28 928M -7 29 960M -7 30 992M - -# usb3_mode -# Disable = Use the port always as USB 2.0 for compatibility -# Enable = Use the port always as USB 3.0 for speed -# Auto = Initialize the port as USB 2.0, until the OS loads -# xHCI USB 3.0 driver -# SmartAuto = Same as Auto but, if the OS loads the xHCI USB 3.0 driver -# and the computer is reset, keep the USB 3.0 mode. -# -8 0 Disable -8 1 Enable -8 2 Auto -8 3 SmartAuto +6 0 32M +6 1 64M +6 2 96M +6 3 128M +6 4 160M +6 5 192M +6 6 224M +6 7 256M +6 8 288M +6 9 320M +6 10 352M +6 11 384M +6 12 416M +6 13 448M +6 14 480M +6 15 512M +6 16 1024M # ----------------------------------------------------------------- -# <startBit[must be byte-aligned]> <endBit[must be byte aligned]> -# <bit where to start storing checksum[must be 16bits-aligned]> checksums -checksum 392 431 544 +checksum 392 423 984 diff --git a/src/mainboard/asus/p8x7x/variants/z77-m_pro/early_init.c b/src/mainboard/asus/p8x7x/variants/z77-m_pro/early_init.c index 78ad877..a6916c2 100644 --- a/src/mainboard/asus/p8x7x/variants/z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8x7x/variants/z77-m_pro/early_init.c @@ -53,104 +53,3 @@ read_spd(&spd[2], 0x52, id_only); read_spd(&spd[3], 0x53, id_only); } - -int mainboard_should_reset_usb(int s3resume) -{ - return !s3resume; -} - -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ - /* - * USB3 mode: - * 0 = Disable: work always as USB 2.0(ehci) - * 1 = Enable: work always as USB 3.0(xhci) - * 2 = Auto: work as USB2.0(ehci) until OS loads USB3 xhci driver - * 3 = Smart Auto : same than Auto, but if OS loads USB3 driver - * and reboots, it will keep the USB3.0 speed - */ - unsigned int usb3_mode = get_uint_option("usb3_mode", 1); - usb3_mode &= 0x3; /* ensure it's 0/1/2/3 only */ - - /* Load USB3 pre-OS xHCI driver */ - unsigned int usb3_drv = get_uint_option("usb3_drv", 1); - usb3_drv &= 0x1; /* ensure it's 0/1 only */ - - /* Use USB3 xHCI streams */ - unsigned int usb3_streams = get_uint_option("usb3_streams", 1); - usb3_streams &= 0x1; /* ensure it's 0/1 only */ - - struct pei_data pd = { - .pei_version = PEI_VERSION, - .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, - .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, - .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 1, /* 0=Mobile, 1=Desktop/Server */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* SMBus mul 2 */ - .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 0, /* Asus 2203 BIOS shows XUECA016, but no EC */ - .gbe_enable = 0, /* Board uses no Intel GbE but a RTL8111F */ - .max_ddr3_freq = 1600, /* 1333=Sandy; 1600=Ivy */ - .usb_port_config = { - /* {enabled, oc_pin, cable len 0x0080=<8inches/20cm} */ - { 1, 0, 0x0080 }, /* USB3 front internal header */ - { 1, 0, 0x0080 }, /* USB3 front internal header */ - { 1, 1, 0x0080 }, /* USB3 ETH top connector */ - { 1, 1, 0x0080 }, /* USB3 ETH botton connector */ - { 1, 2, 0x0080 }, /* USB2 PS2 top connector */ - { 1, 2, 0x0080 }, /* USB2 PS2 botton connector */ - { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */ - { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */ - { 1, 4, 0x0080 }, /* USB2 internal header (USB910) */ - { 1, 4, 0x0080 }, /* USB2 internal header (USB910) */ - { 1, 6, 0x0080 }, /* USB2 internal header (USB1112) */ - { 1, 5, 0x0080 }, /* USB2 internal header (USB1112) */ - { 0, 5, 0x0080 }, /* Unused. Asus DEBUG_PORT ??? */ - { 0, 6, 0x0080 } /* Unused. Asus DEBUG_PORT ??? */ - }, - .usb3 = { - /* 0=Disable; 1=Enable (start at USB3 speed) - * 2=Auto (start as USB2 speed until OS loads) - * 3=Smart Auto (like Auto but keep speed on reboot) - */ - usb3_mode, - /* 4 bit switch mask. 0=not switchable, 1=switchable - * Means once it's loaded the OS, it can swap ports - * from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf - */ - 0xf, - usb3_drv, /* 1=Load xHCI pre-OS drv */ - /* 0=Don't use xHCI streams for better compatibility - * 1=use xHCI streams for better speed - */ - usb3_streams - }, - /* ASUS P8Z77-M PRO manual says 1.35v DIMMs are supported */ - .ddr3lv_support = 1, - /* PCIe 3.0 support. As we use Ivy Bridge, let's enable it, - * but might cause some system instability ! - */ - .pcie_init = 1, - /* Command Rate. 0=Auto; 1=1N; 2=2N. - * Leave it always at Auto for compatibility & stability - */ - .nmode = 0, - /* DDR refresh rate. 0=Auto based on DRAM's temperature; - * 1=Normal rate for speed; 2=Double rate for stability - */ - .ddr_refresh_rate_config = 0 - }; - - /* copy the data to output PEI */ - *pei_data = pd; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/54336 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79dc64c25cb36c630bf9994bf04a0dfe8654eb3c Gerrit-Change-Number: 54336 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asus/p8z77: Turn P8Z77-M PRO into a variant of P8x7x baseboard
by Bill XIE (Code Review) 16 May '21

16 May '21

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54335 ) Change subject: mb/asus/p8z77: Turn P8Z77-M PRO into a variant of P8x7x baseboard ...................................................................... mb/asus/p8z77: Turn P8Z77-M PRO into a variant of P8x7x baseboard Other variants would be added later. MAINBOARD_HAS_TPM1 should not be selected, since the module is replaceable. Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Change-Id: Iaf0bd4c993debe4d5d7ca695473438bd4c954290 --- A src/mainboard/asus/p8x7x/Kconfig R src/mainboard/asus/p8x7x/Kconfig.name A src/mainboard/asus/p8x7x/Makefile.inc R src/mainboard/asus/p8x7x/acpi/ec.asl R src/mainboard/asus/p8x7x/acpi/platform.asl R src/mainboard/asus/p8x7x/acpi/superio.asl A src/mainboard/asus/p8x7x/board_info.txt R src/mainboard/asus/p8x7x/cmos.default R src/mainboard/asus/p8x7x/cmos.layout A src/mainboard/asus/p8x7x/devicetree.cb R src/mainboard/asus/p8x7x/dsdt.asl A src/mainboard/asus/p8x7x/hda_verb.c R src/mainboard/asus/p8x7x/variants/z77-m_pro/acpi_tables.c A src/mainboard/asus/p8x7x/variants/z77-m_pro/board_info.txt R src/mainboard/asus/p8x7x/variants/z77-m_pro/data.vbt R src/mainboard/asus/p8x7x/variants/z77-m_pro/early_init.c R src/mainboard/asus/p8x7x/variants/z77-m_pro/gma-mainboard.ads R src/mainboard/asus/p8x7x/variants/z77-m_pro/gpio.c R src/mainboard/asus/p8x7x/variants/z77-m_pro/hda_verb.c R src/mainboard/asus/p8x7x/variants/z77-m_pro/mainboard.c A src/mainboard/asus/p8x7x/variants/z77-m_pro/overridetree.cb D src/mainboard/asus/p8z77-m_pro/Kconfig D src/mainboard/asus/p8z77-m_pro/Makefile.inc D src/mainboard/asus/p8z77-m_pro/board_info.txt D src/mainboard/asus/p8z77-m_pro/devicetree.cb 25 files changed, 184 insertions(+), 139 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/54335/1 diff --git a/src/mainboard/asus/p8x7x/Kconfig b/src/mainboard/asus/p8x7x/Kconfig new file mode 100644 index 0000000..e6e9bf7 --- /dev/null +++ b/src/mainboard/asus/p8x7x/Kconfig @@ -0,0 +1,39 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_ASUS_P8Z77_M_PRO + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select MAINBOARD_HAS_LPC_TPM if BOARD_ASUS_P8Z77_M_PRO + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select MAINBOARD_HAS_LIBGFXINIT + select INTEL_GMA_HAVE_VBT + select SUPERIO_NUVOTON_NCT6779D + # for ASM1061 eSATA + select DRIVERS_ASMEDIA_ASPM_BLACKLIST if BOARD_ASUS_P8Z77_M_PRO + +config MAINBOARD_DIR + string + default "asus/p8x7x" + +config VARIANT_DIR + string + default "z77-m_pro" if BOARD_ASUS_P8Z77_M_PRO + +config MAINBOARD_PART_NUMBER + string + default "P8Z77-M PRO" if BOARD_ASUS_P8Z77_M_PRO + +config OVERRIDE_DEVICETREE + string + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + +endif # BOARD_ASUS_P8Z77_M_PRO diff --git a/src/mainboard/asus/p8z77-m_pro/Kconfig.name b/src/mainboard/asus/p8x7x/Kconfig.name similarity index 100% rename from src/mainboard/asus/p8z77-m_pro/Kconfig.name rename to src/mainboard/asus/p8x7x/Kconfig.name diff --git a/src/mainboard/asus/p8x7x/Makefile.inc b/src/mainboard/asus/p8x7x/Makefile.inc new file mode 100644 index 0000000..728c213 --- /dev/null +++ b/src/mainboard/asus/p8x7x/Makefile.inc @@ -0,0 +1,10 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +bootblock-y += variants/$(VARIANT_DIR)/early_init.c +bootblock-y += variants/$(VARIANT_DIR)/gpio.c +romstage-y += variants/$(VARIANT_DIR)/early_init.c +romstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c +ramstage-y += variants/$(VARIANT_DIR)/mainboard.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads + diff --git a/src/mainboard/asus/p8z77-m_pro/acpi/ec.asl b/src/mainboard/asus/p8x7x/acpi/ec.asl similarity index 100% rename from src/mainboard/asus/p8z77-m_pro/acpi/ec.asl rename to src/mainboard/asus/p8x7x/acpi/ec.asl diff --git a/src/mainboard/asus/p8z77-m_pro/acpi/platform.asl b/src/mainboard/asus/p8x7x/acpi/platform.asl similarity index 100% rename from src/mainboard/asus/p8z77-m_pro/acpi/platform.asl rename to src/mainboard/asus/p8x7x/acpi/platform.asl diff --git a/src/mainboard/asus/p8z77-m_pro/acpi/superio.asl b/src/mainboard/asus/p8x7x/acpi/superio.asl similarity index 100% rename from src/mainboard/asus/p8z77-m_pro/acpi/superio.asl rename to src/mainboard/asus/p8x7x/acpi/superio.asl diff --git a/src/mainboard/asus/p8x7x/board_info.txt b/src/mainboard/asus/p8x7x/board_info.txt new file mode 100644 index 0000000..8fd3401 --- /dev/null +++ b/src/mainboard/asus/p8x7x/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board name: ASUS P8x7x baseboard +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/asus/p8z77-m_pro/cmos.default b/src/mainboard/asus/p8x7x/cmos.default similarity index 100% rename from src/mainboard/asus/p8z77-m_pro/cmos.default rename to src/mainboard/asus/p8x7x/cmos.default diff --git a/src/mainboard/asus/p8z77-m_pro/cmos.layout b/src/mainboard/asus/p8x7x/cmos.layout similarity index 100% rename from src/mainboard/asus/p8z77-m_pro/cmos.layout rename to src/mainboard/asus/p8x7x/cmos.layout diff --git a/src/mainboard/asus/p8x7x/devicetree.cb b/src/mainboard/asus/p8x7x/devicetree.cb new file mode 100644 index 0000000..c66f601 --- /dev/null +++ b/src/mainboard/asus/p8x7x/devicetree.cb @@ -0,0 +1,89 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/sandybridge + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" + device lapic 0x0 on end + device lapic 0xacac off end + end + end + device domain 0x0 on + subsystemid 0x1043 0x84ca inherit + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 on end # Internal graphics VGA controller + + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + register "c2_latency" = "0x65" + register "gen1_dec" = "0xc0291" + register "sata_interface_speed_support" = "0x3" # 0x3=SATAIII + register "sata_port_map" = "0x3f" # Enable the six SATA ports + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0xf" + register "xhci_overcurrent_mapping" = "0xc03" + register "xhci_switchable_ports" = "0xf" # the 4 ports + + device pci 14.0 on end # USB 3.0 Controller + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI 2 + device pci 1b.0 on end # High Definition Audio controller + device pci 1c.0 off end # PCIe Port 1 + device pci 1c.1 off end # PCIe Port 2 + device pci 1c.2 off end # PCIe Port 3 + device pci 1c.3 off end # PCIe Port 4 + device pci 1c.4 off end # PCIe Port 5 + device pci 1c.5 off end # PCIe Port 6 + device pci 1c.6 off end # PCIe Port 7 + device pci 1c.7 off end # PCIe Port 8 + device pci 1d.0 on end # USB2 EHCI 1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/nuvoton/nct6779d + device pnp 2e.1 off end # Parallel + device pnp 2e.2 off end # UART A + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # PS2 KBC + io 0x60 = 0x0060 # KBC1 base + io 0x62 = 0x0064 # KBC2 base + irq 0x70 = 1 # Keyboard IRQ + irq 0x72 = 12 # Mouse IRQ + + # KBC 12Mhz/A20 speed/sw KBRST + drq 0xf0 = 0x82 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIOs 6-8 + device pnp 2e.8 off end # WDT1 GPIO 0-1 + device pnp 2e.108 off end # GPIO0 + device pnp 2e.109 off end # GPIO1 + device pnp 2e.209 off end # GPIO2 + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 off end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 off end # GPIO7 + device pnp 2e.9 off end # GPIO8 + device pnp 2e.a off end # ACPI + device pnp 2e.b off end # H/W Monitor, FP LED + device pnp 2e.d off end # WDT1 + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # Push-pull/Open-drain + device pnp 2e.14 off end # Port 80 UART + device pnp 2e.16 off end # Deep sleep + end + end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asus/p8z77-m_pro/dsdt.asl b/src/mainboard/asus/p8x7x/dsdt.asl similarity index 100% rename from src/mainboard/asus/p8z77-m_pro/dsdt.asl rename to src/mainboard/asus/p8x7x/dsdt.asl diff --git a/src/mainboard/asus/p8x7x/hda_verb.c b/src/mainboard/asus/p8x7x/hda_verb.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/p8x7x/hda_verb.c diff --git a/src/mainboard/asus/p8z77-m_pro/acpi_tables.c b/src/mainboard/asus/p8x7x/variants/z77-m_pro/acpi_tables.c similarity index 100% rename from src/mainboard/asus/p8z77-m_pro/acpi_tables.c rename to src/mainboard/asus/p8x7x/variants/z77-m_pro/acpi_tables.c diff --git a/src/mainboard/asus/p8x7x/variants/z77-m_pro/board_info.txt b/src/mainboard/asus/p8x7x/variants/z77-m_pro/board_info.txt new file mode 100644 index 0000000..9325e98 --- /dev/null +++ b/src/mainboard/asus/p8x7x/variants/z77-m_pro/board_info.txt @@ -0,0 +1,3 @@ +Board name: ASUS P8Z77-M PRO +Board URL: https://www.asus.com/Motherboards/P8Z77M_PRO/ +Release year: 2013 diff --git a/src/mainboard/asus/p8z77-m_pro/data.vbt b/src/mainboard/asus/p8x7x/variants/z77-m_pro/data.vbt similarity index 100% rename from src/mainboard/asus/p8z77-m_pro/data.vbt rename to src/mainboard/asus/p8x7x/variants/z77-m_pro/data.vbt Binary files differ diff --git a/src/mainboard/asus/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8x7x/variants/z77-m_pro/early_init.c similarity index 100% rename from src/mainboard/asus/p8z77-m_pro/early_init.c rename to src/mainboard/asus/p8x7x/variants/z77-m_pro/early_init.c diff --git a/src/mainboard/asus/p8z77-m_pro/gma-mainboard.ads b/src/mainboard/asus/p8x7x/variants/z77-m_pro/gma-mainboard.ads similarity index 100% rename from src/mainboard/asus/p8z77-m_pro/gma-mainboard.ads rename to src/mainboard/asus/p8x7x/variants/z77-m_pro/gma-mainboard.ads diff --git a/src/mainboard/asus/p8z77-m_pro/gpio.c b/src/mainboard/asus/p8x7x/variants/z77-m_pro/gpio.c similarity index 100% rename from src/mainboard/asus/p8z77-m_pro/gpio.c rename to src/mainboard/asus/p8x7x/variants/z77-m_pro/gpio.c diff --git a/src/mainboard/asus/p8z77-m_pro/hda_verb.c b/src/mainboard/asus/p8x7x/variants/z77-m_pro/hda_verb.c similarity index 100% rename from src/mainboard/asus/p8z77-m_pro/hda_verb.c rename to src/mainboard/asus/p8x7x/variants/z77-m_pro/hda_verb.c diff --git a/src/mainboard/asus/p8z77-m_pro/mainboard.c b/src/mainboard/asus/p8x7x/variants/z77-m_pro/mainboard.c similarity index 100% rename from src/mainboard/asus/p8z77-m_pro/mainboard.c rename to src/mainboard/asus/p8x7x/variants/z77-m_pro/mainboard.c diff --git a/src/mainboard/asus/p8x7x/variants/z77-m_pro/overridetree.cb b/src/mainboard/asus/p8x7x/variants/z77-m_pro/overridetree.cb new file mode 100644 index 0000000..e85e647 --- /dev/null +++ b/src/mainboard/asus/p8x7x/variants/z77-m_pro/overridetree.cb @@ -0,0 +1,37 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/sandybridge + device domain 0x0 on + chip southbridge/intel/bd82x6x + register "gen4_dec" = "0x0000ff29" + register "pcie_port_coalesce" = "1" + device pci 1c.0 on end # PCIe Port 1 PCIEX_16_3 + device pci 1c.1 on end # PCIe Port 2 RTL8111F + device pci 1c.5 on end # PCIe Port 6 ASM1042 USB3 + device pci 1c.6 on end # PCIe Port 7 ASM1061 eSATA + device pci 1f.0 on # LPC bridge + chip superio/nuvoton/nct6779d + device pnp 2e.3 on # UART B, IR + io 0x60 = 0x2f8 # COM2 address + end + device pnp 2e.5 on # PS2 KBC + # KBC 12Mhz/A20 speed/sw KBRST + drq 0xf0 = 0x82 + end + device pnp 2e.7 on end # GPIOs 6-8 + device pnp 2e.a off + drq 0xe4 = 0x10 # Enable 3VSBS to power RAM on S3 + drq 0xe7 = 0x10 # 0.5s S3 delay for compatibility + end + device pnp 2e.f on # Push-pull/Open-drain + drq 0xe6 = 0x7f # GP7 PP + end + device pnp 2e.14 on end # Port 80 UART + end + chip drivers/pc80/tpm + device pnp 4e.0 on end # TPM + end + end + end + end +end diff --git a/src/mainboard/asus/p8z77-m_pro/Kconfig b/src/mainboard/asus/p8z77-m_pro/Kconfig deleted file mode 100644 index 19a1fe1..0000000 --- a/src/mainboard/asus/p8z77-m_pro/Kconfig +++ /dev/null @@ -1,31 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -if BOARD_ASUS_P8Z77_M_PRO - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select BOARD_ROMSIZE_KB_8192 - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select INTEL_INT15 - select NORTHBRIDGE_INTEL_SANDYBRIDGE - select SERIRQ_CONTINUOUS_MODE - select SOUTHBRIDGE_INTEL_C216 - select MAINBOARD_HAS_LPC_TPM - select MAINBOARD_HAS_TPM1 - select HAVE_OPTION_TABLE - select HAVE_CMOS_DEFAULT - select MAINBOARD_HAS_LIBGFXINIT - select INTEL_GMA_HAVE_VBT - select SUPERIO_NUVOTON_NCT6779D - select DRIVERS_ASMEDIA_ASPM_BLACKLIST # for ASM1061 eSATA - -config MAINBOARD_DIR - string - default "asus/p8z77-m_pro" - -config MAINBOARD_PART_NUMBER - string - default "P8Z77-M PRO" - -endif # BOARD_ASUS_P8Z77_M_PRO diff --git a/src/mainboard/asus/p8z77-m_pro/Makefile.inc b/src/mainboard/asus/p8z77-m_pro/Makefile.inc deleted file mode 100644 index 26b20d7..0000000 --- a/src/mainboard/asus/p8z77-m_pro/Makefile.inc +++ /dev/null @@ -1,8 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-or-later - -bootblock-y += gpio.c -romstage-y += gpio.c - -ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -bootblock-y += early_init.c -romstage-y += early_init.c diff --git a/src/mainboard/asus/p8z77-m_pro/board_info.txt b/src/mainboard/asus/p8z77-m_pro/board_info.txt deleted file mode 100644 index 66e6f0d..0000000 --- a/src/mainboard/asus/p8z77-m_pro/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Category: desktop -Board URL: https://www.asus.com/Motherboards/P8Z77M_PRO/ -ROM package: DIP-8 -ROM protocol: SPI -ROM socketed: y -Flashrom support: y -Release year: 2013 diff --git a/src/mainboard/asus/p8z77-m_pro/devicetree.cb b/src/mainboard/asus/p8z77-m_pro/devicetree.cb deleted file mode 100644 index 1d1a244..0000000 --- a/src/mainboard/asus/p8z77-m_pro/devicetree.cb +++ /dev/null @@ -1,93 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -chip northbridge/intel/sandybridge - device cpu_cluster 0x0 on - chip cpu/intel/model_206ax - register "acpi_c1" = "1" - register "acpi_c2" = "3" - register "acpi_c3" = "5" - device lapic 0x0 on end - device lapic 0xacac off end - end - end - device domain 0x0 on - subsystemid 0x1043 0x84ca inherit - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Internal graphics VGA controller - - chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" - register "gen1_dec" = "0x000c0291" - register "gen4_dec" = "0x0000ff29" - register "pcie_port_coalesce" = "1" - register "sata_interface_speed_support" = "0x3" # 0x3=SATAIII - register "sata_port_map" = "0x3f" # Enable the six SATA ports - register "spi_lvscc" = "0x2005" - register "spi_uvscc" = "0x2005" - register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" - register "xhci_switchable_ports" = "0x0000000f" # the 4 ports - - device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI 2 - device pci 1b.0 on end # High Definition Audio controller - device pci 1c.0 on end # PCIe Port 1 PCIEX_16_3 - device pci 1c.1 on end # PCIe Port 2 RTL8111F - device pci 1c.2 off end # PCIe Port 3 unused - device pci 1c.3 off end # PCIe Port 4 unused - device pci 1c.4 off end # PCIe Port 5 unused - device pci 1c.5 on end # PCIe Port 6 ASM1042 USB3 - device pci 1c.6 on end # PCIe Port 7 ASM1061 eSATA - device pci 1c.7 off end # PCIe Port 8 unused - device pci 1d.0 on end # USB2 EHCI 1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge - chip superio/nuvoton/nct6779d - device pnp 2e.1 off end # Parallel - device pnp 2e.2 off end # UART A - device pnp 2e.3 on # UART B, IR - io 0x60 = 0x2f8 # COM2 address - end - device pnp 2e.5 on # PS2 KBC - io 0x60 = 0x0060 # KBC1 base - io 0x62 = 0x0064 # KBC2 base - irq 0x70 = 1 # Keyboard IRQ - irq 0x72 = 12 # Mouse IRQ - - # KBC 12Mhz/A20 speed/sw KBRST - drq 0xf0 = 0x82 - end - device pnp 2e.6 off end # CIR - device pnp 2e.7 on end # GPIOs 6-8 - device pnp 2e.8 off end # WDT1 GPIO 0-1 - device pnp 2e.9 off end # GPIO 1-8 - device pnp 2e.a on # ACPI - drq 0xe4 = 0x10 # Enable 3VSBS to power RAM on S3 - drq 0xe7 = 0x10 # 0.5s S3 delay for compatibility - end - device pnp 2e.b off end # HWM, LED - device pnp 2e.d off end # WDT1 - device pnp 2e.e off end # CIR wake-up - device pnp 2e.f on # GPIO PP/OD - drq 0xe6 = 0x7f # GP7 PP - end - device pnp 2e.14 on end # Port 80 UART - device pnp 2e.16 off end # Deep sleep - end - chip drivers/pc80/tpm - device pnp 4e.0 on end # TPM - end - end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal - end - end -end -- To view, visit https://review.coreboot.org/c/coreboot/+/54335 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf0bd4c993debe4d5d7ca695473438bd4c954290 Gerrit-Change-Number: 54335 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Add configurable value for UsbTcPortEn
by build bot (Jenkins) (Code Review) 16 May '21

16 May '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54334 ) Change subject: soc/intel/alderlake: Add configurable value for UsbTcPortEn ...................................................................... Patch Set 1: (6 comments) File src/soc/intel/alderlake/chip.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119381): https://review.coreboot.org/c/coreboot/+/54334/comment/9cafc16f_4283d43a PS1, Line 44: * Specifies which Type-C Ports are enabled on the system code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119381): https://review.coreboot.org/c/coreboot/+/54334/comment/c3f1b92b_e976ba34 PS1, Line 45: * each bit represents a port starting at 0 code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119381): https://review.coreboot.org/c/coreboot/+/54334/comment/bb7d57d0_4ac4c002 PS1, Line 46: * Example: set value to 0x3 for ports 0 and 1 to be enabled code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119381): https://review.coreboot.org/c/coreboot/+/54334/comment/f2d66be8_84fc221d PS1, Line 47: */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119381): https://review.coreboot.org/c/coreboot/+/54334/comment/d216df58_1a597977 PS1, Line 48: uint8_t UsbTcPortEn; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119381): https://review.coreboot.org/c/coreboot/+/54334/comment/d3f5a1f7_417864e3 PS1, Line 48: uint8_t UsbTcPortEn; please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/54334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5cd0690945b9296c105ade2d99f68bbf0ee22bd Gerrit-Change-Number: 54334 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 16 May 2021 13:56:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add configurable value for UsbTcPortEn
by Sridhar Siricilla (Code Review) 16 May '21

16 May '21

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54334 ) Change subject: soc/intel/alderlake: Add configurable value for UsbTcPortEn ...................................................................... soc/intel/alderlake: Add configurable value for UsbTcPortEn As a requirement of TCSS this setting needs to be correctly set to determine what Type-C ports are enabled on the platform. BUG=b:184324979 TEST=Verified on brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ic5cd0690945b9296c105ade2d99f68bbf0ee22bd --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/54334/1 diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index fb9dd73..d433a00 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -39,6 +39,14 @@ /* Enable S0iX support */ int s0ix_enable; + + /* + * Specifies which Type-C Ports are enabled on the system + * each bit represents a port starting at 0 + * Example: set value to 0x3 for ports 0 and 1 to be enabled + */ + uint8_t UsbTcPortEn; + /* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */ uint8_t TcssD3HotDisable; /* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */ diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 2ab1825..03173b3 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -128,6 +128,7 @@ params->D3HotEnable = !config->TcssD3HotDisable; params->D3ColdEnable = !config->TcssD3ColdDisable; + params->UsbTcPortEn = config->UsbTcPortEn; params->TcssAuxOri = config->TcssAuxOri; for (i = 0; i < 8; i++) params->IomTypeCPortPadCfg[i] = config->IomTypeCPortPadCfg[i]; -- To view, visit https://review.coreboot.org/c/coreboot/+/54334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5cd0690945b9296c105ade2d99f68bbf0ee22bd Gerrit-Change-Number: 54334 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/puff/var/dooly: Add gpio_keys for mic mute switch
by Ben Zhang (Code Review) 16 May '21

16 May '21

Attention is currently required from: Tim Wawrzynczak. Ben Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54333 ) Change subject: mb/google/puff/var/dooly: Add gpio_keys for mic mute switch ...................................................................... mb/google/puff/var/dooly: Add gpio_keys for mic mute switch UI monitors this input event and sends global mic mute command to CRAS when the physical switch is toggled. BUG=b:184593945 BRANCH=puff TEST=build image and verify with evtest on DUT. Apply crrev.com/c/2870806 with chrome cmdline flag and verify global mute is triggered. Verify sequences of switch toggle and suspend/resume. Change-Id: Id89947885fdd96c5b5d598bda6db127daf298dc3 Signed-off-by: Ben Zhang <benzh(a)google.com> --- M src/mainboard/google/hatch/variants/dooly/gpio.c M src/mainboard/google/hatch/variants/dooly/overridetree.cb 2 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/54333/1 diff --git a/src/mainboard/google/hatch/variants/dooly/gpio.c b/src/mainboard/google/hatch/variants/dooly/gpio.c index 5fd88c2..eabd2c6 100644 --- a/src/mainboard/google/hatch/variants/dooly/gpio.c +++ b/src/mainboard/google/hatch/variants/dooly/gpio.c @@ -42,7 +42,7 @@ PAD_NC(GPP_C19, NONE), /* D16 : DMIC_ON_OFF MIC_SWITCH_L */ - PAD_CFG_GPI(GPP_D16, NONE, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_D16, NONE, PLTRST), /* E2 : EN_PP_MST_OD */ PAD_CFG_GPO(GPP_E2, 1, DEEP), diff --git a/src/mainboard/google/hatch/variants/dooly/overridetree.cb b/src/mainboard/google/hatch/variants/dooly/overridetree.cb index 3d7a4a5..1276ed8 100644 --- a/src/mainboard/google/hatch/variants/dooly/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dooly/overridetree.cb @@ -348,6 +348,17 @@ register "property_list[0].integer" = "1" device i2c 1a on end end + chip drivers/generic/gpio_keys + register "name" = ""MUTE"" + register "label" = ""mic_mute_switch"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_D16)" + register "key.wakeup_route" = "WAKEUP_ROUTE_DISABLED" + register "key.dev_name" = ""MMSW"" + register "key.linux_code" = "SW_MUTE_DEVICE" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""mic_mute_switch_key"" + device generic 0 on end + end end #I2C #4 device pci 1a.0 on end # eMMC device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) -- To view, visit https://review.coreboot.org/c/coreboot/+/54333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id89947885fdd96c5b5d598bda6db127daf298dc3 Gerrit-Change-Number: 54333 Gerrit-PatchSet: 1 Gerrit-Owner: Ben Zhang <benzh(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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