coreboot-gerrit May 2021

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Change in coreboot[master]: drivers/gpio_keys: Add label and SW_MUTE_DEVICE
by Ben Zhang (Code Review) 16 May '21

16 May '21

Ben Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54332 ) Change subject: drivers/gpio_keys: Add label and SW_MUTE_DEVICE ...................................................................... drivers/gpio_keys: Add label and SW_MUTE_DEVICE Added the label field to the gpio_keys DSD so that the kernel driver can use a meaningful name instead of the generic _HID PRP0001. Added SW_MUTE_DEVICE event type for mic mute switch. BUG=b:184593945 TEST=build image and verify with evtest on puff: /dev/input/event3: mic_mute_switch UI event_device_info receives the proper name. Change-Id: I0377851b9cf23bab31930aed6e7de91b4ac3505b Signed-off-by: Ben Zhang <benzh(a)google.com> --- M src/drivers/generic/gpio_keys/chip.h M src/drivers/generic/gpio_keys/gpio_keys.c 2 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/54332/1 diff --git a/src/drivers/generic/gpio_keys/chip.h b/src/drivers/generic/gpio_keys/chip.h index a2ff59d..88dfe2e 100644 --- a/src/drivers/generic/gpio_keys/chip.h +++ b/src/drivers/generic/gpio_keys/chip.h @@ -14,6 +14,7 @@ /* Switch events type (Linux code emitted for EV_SW) */ enum { + SW_MUTE_DEVICE = 0xe, SW_PEN_INSERTED = 0xf, }; @@ -74,6 +75,8 @@ struct drivers_generic_gpio_keys_config { /* Device name of the parent gpio-keys node */ const char *name; + /* Name of the input device - Optional */ + const char *label; /* GPIO line providing the key - Mandatory */ struct acpi_gpio gpio; /* Is this a polled GPIO button? - Optional */ diff --git a/src/drivers/generic/gpio_keys/gpio_keys.c b/src/drivers/generic/gpio_keys/gpio_keys.c index 3d273a0..75ce09f 100644 --- a/src/drivers/generic/gpio_keys/gpio_keys.c +++ b/src/drivers/generic/gpio_keys/gpio_keys.c @@ -76,6 +76,8 @@ /* DSD */ dsd = acpi_dp_new_table("_DSD"); acpi_dp_add_string(dsd, "compatible", drv_string); + if (config->label) + acpi_dp_add_string(dsd, "label", config->label); if (config->is_polled) acpi_dp_add_integer(dsd, "poll-interval", config->poll_interval); -- To view, visit https://review.coreboot.org/c/coreboot/+/54332 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0377851b9cf23bab31930aed6e7de91b4ac3505b Gerrit-Change-Number: 54332 Gerrit-PatchSet: 1 Gerrit-Owner: Ben Zhang <benzh(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/adlrvp: Enable TCSS USB ports
by Sridhar Siricilla (Code Review) 16 May '21

16 May '21

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54331 ) Change subject: mb/intel/adlrvp: Enable TCSS USB ports ...................................................................... mb/intel/adlrvp: Enable TCSS USB ports This patch enables TCSS USB ports. BUG=b:184324979 TEST=Verified on ADL-P RVP Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I92bf30a56f3befad3f806bff5d29d39b6754b079 --- M src/mainboard/intel/adlrvp/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/54331/1 diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 23913cc..c94c8c3 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -15,6 +15,9 @@ # Enable HECI1 interface register "HeciEnabled" = "1" + # TCSS USB port enable + register "UsbTcPortEn" = "0x7" + # FSP configuration # Enable CNVi BT -- To view, visit https://review.coreboot.org/c/coreboot/+/54331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92bf30a56f3befad3f806bff5d29d39b6754b079 Gerrit-Change-Number: 54331 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: Enable TCSS USB ports
by Sridhar Siricilla (Code Review) 16 May '21

16 May '21

Attention is currently required from: Tim Wawrzynczak. Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54330 ) Change subject: mb/google/brya: Enable TCSS USB ports ...................................................................... mb/google/brya: Enable TCSS USB ports This patch enables TCSS USB ports and undo the workaround to enable the TCSS USB ports. TEST=Verified on brya BUG=b:184324979 DEPENDS ON=FSPv2172 Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ibb4f3f4ce154c73d766df21079c1a9ad8bfc2f0d --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb 1 file changed, 3 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/54330/1 diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index 5f73671..07ef897 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -17,6 +17,9 @@ # S0ix enable register "s0ix_enable" = "1" + # TCSS USB port enable + register "UsbTcPortEn" = "0x7" + # DPTF enable register "dptf_enable" = "1" @@ -50,12 +53,6 @@ register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0 - # TODO(b/184324979): Workaround to enable TCSS ports. FSP v2081 - # uses port enable for south XHCI ports to determine if TCSS - # ports should be enabled. Until FSP is fixed, enable south - # XHCI ports 1 and 2. - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)" -- To view, visit https://review.coreboot.org/c/coreboot/+/54330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb4f3f4ce154c73d766df21079c1a9ad8bfc2f0d Gerrit-Change-Number: 54330 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: Enable HECI1 communication
by Sridhar Siricilla (Code Review) 16 May '21

16 May '21

Attention is currently required from: Furquan Shaikh. Hello build bot (Jenkins), Jamie Ryu, Furquan Shaikh, Tim Wawrzynczak, Rizwan Qureshi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54210 to look at the new patch set (#3). Change subject: mb/google/brya: Enable HECI1 communication ...................................................................... mb/google/brya: Enable HECI1 communication The patch enables HECI1 interface to allow OS applications to communicate with CSE. TEST=Verify PCI device 0:16.0 exposed in the lspci output Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I73acdd99788f9b60b7bcea372145e9694a124174 --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/54210/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/54210 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73acdd99788f9b60b7bcea372145e9694a124174 Gerrit-Change-Number: 54210 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sb/intel: Drop outdated SMBus I/O BAR comment
by Paul Menzel (Code Review) 16 May '21

16 May '21

Attention is currently required from: Nico Huber, Angel Pons, Arthur Heymans, Kyösti Mälkki, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54329 ) Change subject: sb/intel: Drop outdated SMBus I/O BAR comment ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54329 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0149764fd231b3a4e56a5a9b7f4ae61f7954cf7a Gerrit-Change-Number: 54329 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 16 May 2021 12:32:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel: Drop outdated SMBus I/O BAR comment
by Angel Pons (Code Review) 16 May '21

16 May '21

Attention is currently required from: Nico Huber, Paul Menzel, Angel Pons, Arthur Heymans, Kyösti Mälkki, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54329 ) Change subject: sb/intel: Drop outdated SMBus I/O BAR comment ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/54329/comment/97c1d34e_67385e17 PS1, Line 7: sb/intel > Nit: Missing colon after prefix. Done https://review.coreboot.org/c/coreboot/+/54329/comment/5f7fc880_54a653eb PS1, Line 9: The SMBus I/O bar is not relocated because it's reported to the : allocator as a fixed resource. > If you investigated since when, it’d be great, if you mentioned the commit. If not, also fine. I didn't, and I don't think it matters. -- To view, visit https://review.coreboot.org/c/coreboot/+/54329 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0149764fd231b3a4e56a5a9b7f4ae61f7954cf7a Gerrit-Change-Number: 54329 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 16 May 2021 11:40:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel: Drop outdated SMBus I/O BAR comment
by Angel Pons (Code Review) 16 May '21

16 May '21

Attention is currently required from: Nico Huber, Angel Pons, Arthur Heymans, Kyösti Mälkki, Patrick Rudolph. Hello Nico Huber, Paul Menzel, Arthur Heymans, Kyösti Mälkki, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54329 to look at the new patch set (#2). Change subject: sb/intel: Drop outdated SMBus I/O BAR comment ...................................................................... sb/intel: Drop outdated SMBus I/O BAR comment The SMBus I/O bar is not relocated because it's reported to the allocator as a fixed resource. Drop these out-of-date comments. Change-Id: I0149764fd231b3a4e56a5a9b7f4ae61f7954cf7a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/lynxpoint/pch.h 4 files changed, 0 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/54329/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54329 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0149764fd231b3a4e56a5a9b7f4ae61f7954cf7a Gerrit-Change-Number: 54329 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sb/intel Drop outdated SMBus I/O BAR comment
by Paul Menzel (Code Review) 16 May '21

16 May '21

Attention is currently required from: Nico Huber, Angel Pons, Arthur Heymans, Kyösti Mälkki, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54329 ) Change subject: sb/intel Drop outdated SMBus I/O BAR comment ...................................................................... Patch Set 1: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/54329/comment/dca8d9f6_443995ca PS1, Line 7: sb/intel Nit: Missing colon after prefix. https://review.coreboot.org/c/coreboot/+/54329/comment/f581dd06_0a9a03cd PS1, Line 9: The SMBus I/O bar is not relocated because it's reported to the : allocator as a fixed resource. If you investigated since when, it’d be great, if you mentioned the commit. If not, also fine. -- To view, visit https://review.coreboot.org/c/coreboot/+/54329 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0149764fd231b3a4e56a5a9b7f4ae61f7954cf7a Gerrit-Change-Number: 54329 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 16 May 2021 11:36:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/hp: Add Compal LA-A992P
by build bot (Jenkins) (Code Review) 16 May '21

16 May '21

Attention is currently required from: Martin Roth. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52475 ) Change subject: mb/hp: Add Compal LA-A992P ...................................................................... Patch Set 12: (17 comments) File src/mainboard/hp/hp_15_notebook_pc/mainboard.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119372): https://review.coreboot.org/c/coreboot/+/52475/comment/d8e1f40a_a480e775 PS12, Line 15: /* 00 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0xff, 0x04, 0x00, 0x00, 0x12, 0x01, line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119372): https://review.coreboot.org/c/coreboot/+/52475/comment/f53a638b_862b9d2f PS12, Line 16: /* 10 */ 0x01, 0x1b, 0x33, 0x1b, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x04, 0x03, 0x00, line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119372): https://review.coreboot.org/c/coreboot/+/52475/comment/2e50e056_761f03bc PS12, Line 17: /* 20 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119372): https://review.coreboot.org/c/coreboot/+/52475/comment/8211d410_9ef0c63a PS12, Line 18: /* 30 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119372): https://review.coreboot.org/c/coreboot/+/52475/comment/a460f626_fc5d0bf2 PS12, Line 19: /* 40 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119372): https://review.coreboot.org/c/coreboot/+/52475/comment/8745c633_4e19433c PS12, Line 20: /* 50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119372): https://review.coreboot.org/c/coreboot/+/52475/comment/80dd2b10_4dd367a5 PS12, Line 21: /* 60 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119372): https://review.coreboot.org/c/coreboot/+/52475/comment/b73df123_ec652f36 PS12, Line 22: /* 70 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119372): https://review.coreboot.org/c/coreboot/+/52475/comment/b16d3f3b_400bbe3d PS12, Line 23: /* 80 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119372): https://review.coreboot.org/c/coreboot/+/52475/comment/6655898e_6acfbd2d PS12, Line 24: /* 90 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119372): https://review.coreboot.org/c/coreboot/+/52475/comment/a208cbf3_2be91eab PS12, Line 25: /* a0 */ 0x00, 0x04, 0x00, 0x86, 0xc1, 0x00, 0x00, 0x61, 0x63, 0x00, 0x00, 0x08, 0x64, 0x1a, 0x00, 0xf0, line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119372): https://review.coreboot.org/c/coreboot/+/52475/comment/d8a83946_8cd629dc PS12, Line 26: /* b0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x32, 0x02, 0x00, 0x00, line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119372): https://review.coreboot.org/c/coreboot/+/52475/comment/d8dde716_0ba7c0de PS12, Line 27: /* c0 */ 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119372): https://review.coreboot.org/c/coreboot/+/52475/comment/a591901f_4ead8347 PS12, Line 28: /* d0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119372): https://review.coreboot.org/c/coreboot/+/52475/comment/860f856e_eb5455f3 PS12, Line 29: /* e0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119372): https://review.coreboot.org/c/coreboot/+/52475/comment/f791c8b8_3e281ba2 PS12, Line 30: /* f0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119372): https://review.coreboot.org/c/coreboot/+/52475/comment/a485a554_8dc3a17c PS12, Line 35: ec_write (i, dmp[i]); space prohibited between function name and open parenthesis '(' -- To view, visit https://review.coreboot.org/c/coreboot/+/52475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I121ed4c1a9ba78abb1560d48c57105fd36d8b587 Gerrit-Change-Number: 52475 Gerrit-PatchSet: 12 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Sun, 16 May 2021 11:31:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/lynxpoint: Add SerialIO UART console support
by build bot (Jenkins) (Code Review) 16 May '21

16 May '21

Attention is currently required from: Nico Huber, Martin Roth, Arthur Heymans, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52489 ) Change subject: sb/intel/lynxpoint: Add SerialIO UART console support ...................................................................... Patch Set 9: (1 comment) File src/southbridge/intel/lynxpoint/uart_init.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119368): https://review.coreboot.org/c/coreboot/+/52489/comment/2baddcf1_01d0a313 PS9, Line 16: switch (CONFIG_UART_FOR_CONSOLE) { switch and case should be at the same indent -- To view, visit https://review.coreboot.org/c/coreboot/+/52489 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb3460dd50ed03421a38f03c80f91ae9fd604022 Gerrit-Change-Number: 52489 Gerrit-PatchSet: 9 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 16 May 2021 11:14:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit May 2021