coreboot-gerrit May 2021

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Change in coreboot[master]: [TEST]: adln local changes to allign with working recipe
by Usha P (Code Review) 17 May '21

17 May '21

Usha P has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54351 ) Change subject: [TEST]: adln local changes to allign with working recipe ...................................................................... [TEST]: adln local changes to allign with working recipe This patch has the following changes 1. Chromeos.fmd allignment to 10MB 2. devicetree changes to diable TBT and PEG 3. ASPM for NVME boot 4. Allign FSP UPD with IFWI Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: Ie87944868bf2d6a1b6b6c1e42f14d5b45b5bda02 --- M src/mainboard/intel/adlrvp/chromeos.fmd M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 4 files changed, 55 insertions(+), 53 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/54351/1 diff --git a/src/mainboard/intel/adlrvp/chromeos.fmd b/src/mainboard/intel/adlrvp/chromeos.fmd index 5c9ef47..1905fae 100644 --- a/src/mainboard/intel/adlrvp/chromeos.fmd +++ b/src/mainboard/intel/adlrvp/chromeos.fmd @@ -1,48 +1,42 @@ -FLASH 32M { - SI_ALL 6M { - SI_DESC 4K - SI_EC 512K +FLASH@0xfe000001 32M { + SI_ALL@0x0 0x1600000 { + SI_DESC 0x1000 + SI_EC 0x80000 SI_ME } - SI_BIOS 26M { - RW_SECTION_A 8M { - VBLOCK_A 64K - FW_MAIN_A(CBFS) - RW_FWID_A 64 - ME_RW_A(CBFS) 3M + SI_BIOS { + RW_SECTION_A 0x2E8000 { + VBLOCK_A 0x10000 + FW_MAIN_A(CBFS) 0x2d7fc0 + RW_FWID_A 0x40 } - RW_LEGACY(CBFS) 1M - RW_MISC 1M { - UNIFIED_MRC_CACHE(PRESERVE) 192K { - RECOVERY_MRC_CACHE 64K - RW_MRC_CACHE 128K + RW_SECTION_B 0x2E8000 { + VBLOCK_B 0x10000 + FW_MAIN_B(CBFS) 0x2d7fc0 + RW_FWID_B 0x40 + } + RW_MISC 0x30000 { + UNIFIED_MRC_CACHE(PRESERVE) 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 } - RW_ELOG(PRESERVE) 16K - RW_SHARED 16K { - SHARED_DATA 8K - VBLOCK_DEV 8K + RW_ELOG(PRESERVE) 0x4000 + RW_SHARED 0x4000 { + SHARED_DATA 0x2000 + VBLOCK_DEV 0x2000 } - RW_VPD(PRESERVE) 8K - RW_NVRAM(PRESERVE) 24K + RW_VPD(PRESERVE) 0x2000 + RW_NVRAM(PRESERVE) 0x6000 } - # This section starts at the 16M boundary in SPI flash. - # ADL does not support a region crossing this boundary, - # because the SPI flash is memory-mapped into two non- - # contiguous windows. - RW_SECTION_B 8M { - VBLOCK_B 64K - FW_MAIN_B(CBFS) - RW_FWID_B 64 - ME_RW_B(CBFS) 3M - } - # Make WP_RO region align with SPI vendor - # memory protected range specification. - WP_RO 8M { - RO_VPD(PRESERVE) 16K + # RW_LEGACY needs to be minimum of 1MB + # RW_LEGACY(CBFS) 0x500000 + WP_RO { + RO_VPD(PRESERVE) 0x4000 RO_SECTION { - FMAP 2K - RO_FRID 64 - GBB@4K 448K + FMAP 0x800 + RO_FRID 0x40 + RO_FRID_PAD 0x7c0 + GBB 0x3000 COREBOOT(CBFS) } } diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 23913cc..bdbf1fe1 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -205,7 +205,7 @@ device domain 0 on device pci 00.0 on end # Host Bridge - device pci 01.0 on end # PEG10 + device pci 01.0 off end # PEG10 device pci 02.0 on end # Graphics device pci 04.0 on chip drivers/intel/dptf @@ -302,20 +302,20 @@ device generic 0 on end end end # DPTF - device pci 05.0 on end # IPU - device pci 06.0 on end # PEG60 - device pci 06.2 on end # PEG62 - device pci 07.0 on end # TBT_PCIe0 - device pci 07.1 on end # TBT_PCIe1 - device pci 07.2 on end # TBT_PCIe2 - device pci 07.3 on end # TBT_PCIe3 + device pci 05.0 off end # IPU + device pci 06.0 off end # PEG60 + device pci 06.2 off end # PEG62 + device pci 07.0 off end # TBT_PCIe0 + device pci 07.1 off end # TBT_PCIe1 + device pci 07.2 off end # TBT_PCIe2 + device pci 07.3 off end # TBT_PCIe3 device pci 08.0 off end # GNA - device pci 09.0 off end # NPK + device pci 09.0 on end # NPK device pci 0a.0 off end # Crash-log SRAM - device pci 0d.0 on end # USB xHCI - device pci 0d.1 on end # USB xDCI (OTG) - device pci 0d.2 on end # TBT DMA0 - device pci 0d.3 on end # TBT DMA1 + device pci 0d.0 off end # USB xHCI + device pci 0d.1 off end # USB xDCI (OTG) + device pci 0d.2 off end # TBT DMA0 + device pci 0d.3 off end # TBT DMA1 device pci 0e.0 off end # VMD device pci 10.0 off end device pci 10.1 off end @@ -400,6 +400,6 @@ device pci 1f.4 on end # SMBus device pci 1f.5 on end # SPI device pci 1f.6 off end # GbE - device pci 1f.7 off end # TH + device pci 1f.7 on end # TH end end diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 2ab1825..7ed9dd6 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -295,6 +295,7 @@ params->Cx = 1; params->PsOnEnable = 1; + memset(params->PcieRpAspm, 0, sizeof(params->PcieRpAspm)); mainboard_silicon_init_params(params); } diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index ba6e036..fdeb06d 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -233,7 +233,7 @@ /* Skip CPU replacement check */ m_cfg->SkipCpuReplacementCheck = !config->CpuReplacementCheck; - m_cfg->TmeEnable = CONFIG(INTEL_TME); + m_cfg->TmeEnable = 0x0; /* Skip GPIO configuration from FSP */ m_cfg->GpioOverride = 0x1; @@ -243,6 +243,13 @@ m_cfg->CpuCrashLogDevice = 1; m_cfg->CpuCrashLogEnable = 1; } + + m_cfg->LpDdrDqDqsReTraining = 0; + m_cfg->DmiMaxLinkSpeed = 0x4; + m_cfg->EnableC6Dram = 0x1; + m_cfg->DdrFreqLimit = 2133; + m_cfg->WrcFeatureEnable = 0x0; + } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -- To view, visit https://review.coreboot.org/c/coreboot/+/54351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie87944868bf2d6a1b6b6c1e42f14d5b45b5bda02 Gerrit-Change-Number: 54351 Gerrit-PatchSet: 1 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asus/p8x7x: Use native ram init and depricate mrc.bin code
by Angel Pons (Code Review) 17 May '21

17 May '21

Attention is currently required from: Bill XIE. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54336 ) Change subject: mb/asus/p8x7x: Use native ram init and depricate mrc.bin code ...................................................................... Patch Set 3: Code-Review-1 (1 comment) Patchset: PS3: Some things MRC does are missing from the native codepath, such as xHCI setup. The Asus P8Z77-M PRO is the only board with CMOS options for MRC-specific settings, which suggests that the port author cares about the MRC codepath on this board. -- To view, visit https://review.coreboot.org/c/coreboot/+/54336 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79dc64c25cb36c630bf9994bf04a0dfe8654eb3c Gerrit-Change-Number: 54336 Gerrit-PatchSet: 3 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Comment-Date: Mon, 17 May 2021 08:03:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: tests: code coverage improvements
by Paul Menzel (Code Review) 17 May '21

17 May '21

Attention is currently required from: Martin Roth, Paul Fagerburg, Julius Werner. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54072 ) Change subject: tests: code coverage improvements ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/54072/comment/07bcd9ad_44cb21b3 PS4, Line 7: tests: code coverage improvements Please make it a statement by using a verb (in imperative mood) [1]. Maybe: > Improve code coverage [1]: https://chris.beams.io/posts/git-commit/ -- To view, visit https://review.coreboot.org/c/coreboot/+/54072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2bd2bfdedfab291aabeaa968c10b17e9b61c9c0a Gerrit-Change-Number: 54072 Gerrit-PatchSet: 4 Gerrit-Owner: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 17 May 2021 07:18:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: intelblocks/gpio: Add NAVFWE bit to PAD_CFG_DW0 mask
by Maulik V Vaghela (Code Review) 17 May '21

17 May '21

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54350 ) Change subject: intelblocks/gpio: Add NAVFWE bit to PAD_CFG_DW0 mask ...................................................................... intelblocks/gpio: Add NAVFWE bit to PAD_CFG_DW0 mask Definition for NAV_FWE BIT was added in below CL: https://review.coreboot.org/c/coreboot/+/52782 Even if try to set this BIT it was not getting set since PAD_CFG_DW0 mask will make it 0 since this bit was not part of mask. Adding NAV_FWE to mask will resolve this issue and BIT will be set/unset as per programming in mainboard TEST=Check GPIO register dump and see if BIT is getting set properly. Change-Id: I970ae81ed36da45c3acc61814980b2e6ff889445 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/common/block/gpio/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/54350/1 diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index 8dc92ff..8f1c3a5 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -24,7 +24,7 @@ PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE | PAD_CFG0_MODE_MASK |\ PAD_CFG0_ROUTE_MASK | PAD_CFG0_RXTENCFG_MASK | \ PAD_CFG0_RXINV_MASK | PAD_CFG0_PREGFRXSEL | \ - PAD_CFG0_TRIG_MASK | PAD_CFG0_RXRAW1_MASK | \ + PAD_CFG0_TRIG_MASK | PAD_CFG0_RXRAW1_MASK | PAD_CFG0_NAFVWE_ENABLE |\ PAD_CFG0_RXPADSTSEL_MASK | PAD_CFG0_RESET_MASK) #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL) -- To view, visit https://review.coreboot.org/c/coreboot/+/54350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I970ae81ed36da45c3acc61814980b2e6ff889445 Gerrit-Change-Number: 54350 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: tests: code coverage improvements
by Jakub Czapiga (Code Review) 17 May '21

17 May '21

Attention is currently required from: Martin Roth, Paul Fagerburg, Julius Werner. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54072 ) Change subject: tests: code coverage improvements ...................................................................... Patch Set 4: Code-Review+1 (3 comments) File tests/Makefile.inc: https://review.coreboot.org/c/coreboot/+/54072/comment/df65fd3b_09e3c2cc PS3, Line 199: coverage_rpt > I had to add -tests to every target to get the main Makefile to use tests/Makefile.inc. […] I was referring to directory name, not target name :) File tests/Makefile.inc: https://review.coreboot.org/c/coreboot/+/54072/comment/86985e79_b740d656 PS4, Line 204: COV=1 $(MAKE) coverage-report nit: What about V=1? V=$(V) might be useful in some cases. https://review.coreboot.org/c/coreboot/+/54072/comment/c1ccab97_152d8884 PS4, Line 207: COV=1 $(MAKE) clean-coverage-report nit: Same as above -- To view, visit https://review.coreboot.org/c/coreboot/+/54072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2bd2bfdedfab291aabeaa968c10b17e9b61c9c0a Gerrit-Change-Number: 54072 Gerrit-PatchSet: 4 Gerrit-Owner: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 17 May 2021 07:15:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Comment-In-Reply-To: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Move "--help" to general option section
by Bao Zheng (Code Review) 17 May '21

17 May '21

Bao Zheng has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/54349 ) Change subject: amdfwtool: Move "--help" to general option section ...................................................................... Abandoned merged in other changes. -- To view, visit https://review.coreboot.org/c/coreboot/+/54349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I442be6b60ce939c110ffec4f3de8b158f4130212 Gerrit-Change-Number: 54349 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: [WIP]arch/x86: Tear down CAR in ramstage
by Arthur Heymans (Code Review) 17 May '21

17 May '21

Attention is currently required from: Jason Glenesk, Anjaneya "Reddy" Chagam, Raul Rangel, Marshall Dawson, Jonathan Zhang, Johnny Lin, Morgan Jang, Kyösti Mälkki, Aaron Durbin, Patrick Rudolph, Felix Held. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54301 ) Change subject: [WIP]arch/x86: Tear down CAR in ramstage ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/54301/comment/c57a9ca7_57d2fa58 PS2, Line 15: likely to be slow. > Yes, and among many other things. Caching teardown in general will have the same problem as all the old ones -- just this time they are sitting in ramstage. > https://review.coreboot.org/q/topic:%22WIP_wb_cache_postcar%22+(status:open… Sets up caching for cbmem and uses clflush before jumping to postcar. It seems to work well and improves bootspeed a tiny bit, mostly due to compressing postcar. > Just so the background is captured. We used to teardown cache as ram in romstage then return back into C code to load ramstage. Variable juggling is hard there because much of the code is expecting state to be maintained. That's why we added the relocatable car variable stuff; it was complicated but necessary to reuse code from areas that had SRAM that was maintained or targeting ramstage environment. > > So we put in postcar to provide a clean boundary between romstage, ramstage, and semantics of dealing w/ cache as ram backing store disappearing. postcar provides smallish, though it seems ROM space is so tight one can't afford it (would be good to see the numbers. it can be compressed as well), environment where it can be loaded in uncached DRAM, clean up cache-as-ram, enable caching for DRAM, and start running all the fancy C code we have. I don't think the assumption that the code tearing down CAR has to be in uncached DRAM is necessary. The code has to hit DRAM for sure and uncached DRAM is one way of achieving that. I experimented with caching DRAM before loading code (postcar stage) in there and use CLFLUSH afterwards to make sure it hits DRAM. It seems to work well and allows for efficient decompressing of the stage. I don't have numbers yet but I would think that this would also work well with a bigger LZMA compressed ramstage. > > Moving that to stuff to ramstage inherently means you are loading a bigger footprint into uncacheable space. And one needs to ensure that cache-as-ram teardown is done from assembly (which this CL does) and no fancy anything until caching is set up. > > Long story short, I think re-mixing things isn't the best direction because this area is pretty darn complicated to get right. I think we have a pretty good abstraction w/ postcar to where it makes many things straight forward. I would be curious to know numbers on the pressure people are seeing w.r.t. ROM footprints and if there's anything else we can do to help reduce it. -- To view, visit https://review.coreboot.org/c/coreboot/+/54301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02e5017ab2b6a6fd30b37edad19165c2531c8fd1 Gerrit-Change-Number: 54301 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 17 May 2021 07:06:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Remove the misleading option characters
by Bao Zheng (Code Review) 17 May '21

17 May '21

Attention is currently required from: Bao Zheng, Martin Roth, Zheng Bao. Hello build bot (Jenkins), Raul Rangel, Martin Roth, Zheng Bao, Eric Peers, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52657 to look at the new patch set (#6). Change subject: amdfwtool: Remove the misleading option characters ...................................................................... amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 150 insertions(+), 109 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/52657/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/52657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Gerrit-Change-Number: 52657 Gerrit-PatchSet: 6 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Zheng Bao Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/x86/smm: Fix u32 type mismatch in print statement
by Paul Menzel (Code Review) 17 May '21

17 May '21

Attention is currently required from: Werner Zeh. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54343 ) Change subject: cpu/x86/smm: Fix u32 type mismatch in print statement ...................................................................... Patch Set 1: (2 comments) Patchset: PS1: > Hmm, worked on my system: […] No idea, why in coreboot’s toolchain u32 - size_t = size_t, while with Debian sid/unstable (GCC 10.2) u32 - size_t = u32. File src/cpu/x86/smm/smm_module_loader.c: https://review.coreboot.org/c/coreboot/+/54343/comment/34d7953e_22c8ac0b PS1, Line 415: PRIu32 " > Here you make a decimal notation out of a hex but keep 0x as prefix. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/54343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib504bc5e5b19f62d4702b7f485522a2ee3d26685 Gerrit-Change-Number: 54343 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 17 May 2021 07:04:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/smm: Fix u32 type mismatch in print statement
by Paul Menzel (Code Review) 17 May '21

17 May '21

Attention is currently required from: Paul Menzel. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54343 to look at the new patch set (#2). Change subject: cpu/x86/smm: Fix u32 type mismatch in print statement ...................................................................... cpu/x86/smm: Fix u32 type mismatch in print statement CC ramstage/cpu/x86/smm/smm_module_loader.o src/cpu/x86/smm/smm_module_loader.c:415:42: error: format '%lx' expects argument of type 'long unsigned int', but argument 4 has type 'u32' {aka 'unsigned int'} [-Werror=format=] 415 | printk(BIOS_DEBUG, "%s: stack_end = 0x%lx\n", | ~~^ | | | long unsigned int | %x 416 | __func__, stub_params->stack_top - total_stack_size); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | | | u32 {aka unsigned int} Fixes: afb7a814 ("cpu/x86/smm: Introduce SMM module loader version 2") Change-Id: Ib504bc5e5b19f62d4702b7f485522a2ee3d26685 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/cpu/x86/smm/smm_module_loader.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/54343/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib504bc5e5b19f62d4702b7f485522a2ee3d26685 Gerrit-Change-Number: 54343 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit May 2021