coreboot-gerrit May 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: sc7280: cpucp loading changes
by build bot (Jenkins) (Code Review) 17 May '21

17 May '21

Attention is currently required from: Ravi kumar, Shelley Chen, Martin Roth, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49768 ) Change subject: sc7280: cpucp loading changes ...................................................................... Patch Set 36: (42 comments) File src/soc/qualcomm/sc7280/cpucp_load_reset.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/da2311ef_b6690a88 PS36, Line 15: uint32_t val = read32(EPSSTOP_SECURE_ACCESS_OVERRIDE); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/a4e5a9bc_327f2375 PS36, Line 15: uint32_t val = read32(EPSSTOP_SECURE_ACCESS_OVERRIDE); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/1c354b9a_3954f0a6 PS36, Line 16: val |= 0x1; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/938cb9a0_0e147202 PS36, Line 16: val |= 0x1; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/1d1d416e_75fbb065 PS36, Line 18: /* allow NS access to EPSS memory*/ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/5f11e3d1_da8ada12 PS36, Line 19: write32(EPSSTOP_SECURE_ACCESS_OVERRIDE, val); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/9567d82d_82a6d29a PS36, Line 19: write32(EPSSTOP_SECURE_ACCESS_OVERRIDE, val); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/575027ba_743a4fb1 PS36, Line 21: val = read32(EPSSFAST_EPSS_MUC_CLK_CTRL); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/d6b7e403_93879258 PS36, Line 21: val = read32(EPSSFAST_EPSS_MUC_CLK_CTRL); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/3bfaf0d2_b776ac9f PS36, Line 22: val |= 0x1; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/745629a8_ae5835c4 PS36, Line 22: val |= 0x1; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/a3ca8c6a_c7b740da PS36, Line 24: /* Enable subsystem clock. Required for CPUCP PDMEM access*/ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/89f85bce_bf3316e6 PS36, Line 25: write32(EPSSFAST_EPSS_MUC_CLK_CTRL, val); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/dd879b5e_335dfd65 PS36, Line 25: write32(EPSSFAST_EPSS_MUC_CLK_CTRL, val); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/f551eab4_46686c2f PS36, Line 27: while((read32(EPSSFAST_EPSS_MUC_CLK_CTRL) & 0x1) != 0x1); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/8ad885a6_c3b9affc PS36, Line 27: while((read32(EPSSFAST_EPSS_MUC_CLK_CTRL) & 0x1) != 0x1); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/3f79a1a8_0e6f6014 PS36, Line 27: while((read32(EPSSFAST_EPSS_MUC_CLK_CTRL) & 0x1) != 0x1); space required before the open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/39630e59_cbf2dbea PS36, Line 27: while((read32(EPSSFAST_EPSS_MUC_CLK_CTRL) & 0x1) != 0x1); trailing statements should be on next line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/1b3f4267_454cefbd PS36, Line 32: bool cpucp_fw_entry; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/b6f91d1f_d9a29cba PS36, Line 32: bool cpucp_fw_entry; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/adf70cfc_8e29a326 PS36, Line 33: printk(BIOS_DEBUG, "\nSOC:CPUCP image loading.\n"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/ec7f23f1_61209f0d PS36, Line 33: printk(BIOS_DEBUG, "\nSOC:CPUCP image loading.\n"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/01fc483e_4d21ce76 PS36, Line 35: struct prog cpucp_fw_prog = code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/65045b9c_8c310a16 PS36, Line 35: struct prog cpucp_fw_prog = please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/3adec6e2_139209ce PS36, Line 36: PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/cpucp"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/6ab4f102_734d89c7 PS36, Line 36: PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/cpucp"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/be7236c8_1de381c1 PS36, Line 38: cpucp_prepare(); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/4b075fe2_2b3bf777 PS36, Line 38: cpucp_prepare(); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/6258efe7_60aa2276 PS36, Line 40: if (prog_locate(&cpucp_fw_prog)) code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/e19c4466_8079f9a5 PS36, Line 40: if (prog_locate(&cpucp_fw_prog)) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/3d6924b2_722915ef PS36, Line 41: die("SOC imagpe: CPUCP_FW not found"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/3ac1472c_158942b2 PS36, Line 41: die("SOC imagpe: CPUCP_FW not found"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/0c74f6df_6f737607 PS36, Line 43: cpucp_fw_entry = selfload(&cpucp_fw_prog); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/3f9a790a_24bfe8d7 PS36, Line 43: cpucp_fw_entry = selfload(&cpucp_fw_prog); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/e2ae9215_99931b69 PS36, Line 44: if (!cpucp_fw_entry) code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/6a56a4cc_43989417 PS36, Line 44: if (!cpucp_fw_entry) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/be0aade4_39c67564 PS36, Line 45: die("SOC image: CPUCP load failed"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/d18b85aa_e4305105 PS36, Line 45: die("SOC image: CPUCP load failed"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/960014dc_39b98f07 PS36, Line 47: printk(BIOS_DEBUG, "\nSOC:CPUCP image loaded successfully.\n"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/12e291df_1e6fdb56 PS36, Line 47: printk(BIOS_DEBUG, "\nSOC:CPUCP image loaded successfully.\n"); please, no spaces at the start of a line File src/soc/qualcomm/sc7280/soc.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/b764492c_a1b56741 PS36, Line 20: REGION_SIZE(dram_cpucp) / KiB); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119423): https://review.coreboot.org/c/coreboot/+/49768/comment/1f36dfcb_7e21db47 PS36, Line 20: REGION_SIZE(dram_cpucp) / KiB); please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/49768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idac22c8cb231658616999bc577bdf49f9aa7ae74 Gerrit-Change-Number: 49768 Gerrit-PatchSet: 36 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 17 May 2021 08:48:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: aop loading changes
by build bot (Jenkins) (Code Review) 17 May '21

17 May '21

1 0

Change in coreboot[master]: sc7280: shrm.elf loading changes
by build bot (Jenkins) (Code Review) 17 May '21

17 May '21

Attention is currently required from: Ravi kumar, Shelley Chen, Martin Roth, mturney mturney, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49392 ) Change subject: sc7280: shrm.elf loading changes ...................................................................... Patch Set 37: (1 comment) File src/soc/qualcomm/sc7280/shrm_load_reset.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119421): https://review.coreboot.org/c/coreboot/+/49392/comment/9b30cb68_caac7966 PS37, Line 9: void shrm_fw_load_reset() Bad function definition - void shrm_fw_load_reset() should probably be void shrm_fw_load_reset(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/49392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44484573a829eaefbd34907c6fe78d427506a762 Gerrit-Change-Number: 49392 Gerrit-PatchSet: 37 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 17 May 2021 08:48:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: Reserve wlan & wpss dram memory regions
by build bot (Jenkins) (Code Review) 17 May '21

17 May '21

Attention is currently required from: Ravi kumar, Shelley Chen, Paul Menzel, mturney mturney, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50587 ) Change subject: sc7280: Reserve wlan & wpss dram memory regions ...................................................................... Patch Set 34: (4 comments) File src/soc/qualcomm/sc7280/soc.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119409): https://review.coreboot.org/c/coreboot/+/50587/comment/bf372511_57a56e52 PS34, Line 16: REGION_SIZE(dram_wlan) / KiB); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119409): https://review.coreboot.org/c/coreboot/+/50587/comment/bac9efa0_65d20157 PS34, Line 16: REGION_SIZE(dram_wlan) / KiB); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119409): https://review.coreboot.org/c/coreboot/+/50587/comment/ec68b572_96bd07bf PS34, Line 18: REGION_SIZE(dram_wpss) / KiB); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119409): https://review.coreboot.org/c/coreboot/+/50587/comment/f19b90ff_e4875ec1 PS34, Line 18: REGION_SIZE(dram_wpss) / KiB); please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/50587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic98b5d08a0a7b3f772582bf85d94f901a7c53010 Gerrit-Change-Number: 50587 Gerrit-PatchSet: 34 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 17 May 2021 08:35:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: DDR One-Time-Training Support
by Ravi kumar (Code Review) 17 May '21

17 May '21

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54352 ) Change subject: sc7280: DDR One-Time-Training Support ...................................................................... sc7280: DDR One-Time-Training Support Change-Id: I81038c5c7802c154f4310509c6c64710580b8ce4 Signed-off-by: Sudheer Kumar Amrabadi <samrabad(a)codeaurora.org> --- M src/mainboard/google/herobrine/chromeos.fmd M src/soc/qualcomm/sc7280/memlayout.ld 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/54352/1 diff --git a/src/mainboard/google/herobrine/chromeos.fmd b/src/mainboard/google/herobrine/chromeos.fmd index a44a638..e85271c 100644 --- a/src/mainboard/google/herobrine/chromeos.fmd +++ b/src/mainboard/google/herobrine/chromeos.fmd @@ -17,7 +17,7 @@ RW_VPD(PRESERVE) 32K RW_NVRAM(PRESERVE) 16K - RW_DDR_TRAINING(PRESERVE) 8K + RW_MRC_CACHE(PRESERVE) 32K RW_LIMITS_CFG(PRESERVE) 4K RW_ELOG(PRESERVE) 4K RW_SHARED 4K { diff --git a/src/soc/qualcomm/sc7280/memlayout.ld b/src/soc/qualcomm/sc7280/memlayout.ld index 121fd93..84c5a96 100644 --- a/src/soc/qualcomm/sc7280/memlayout.ld +++ b/src/soc/qualcomm/sc7280/memlayout.ld @@ -40,14 +40,14 @@ STACK(0x1484B000, 16K) VBOOT2_WORK(0x1484F000, 12K) DMA_COHERENT(0x14853000, 8K) - REGION(ddr_training, 0x14855000, 8K, 4K) REGION(qclib_serial_log, 0x14857000, 4K, 4K) REGION(ddr_information, 0x1485B000, 1K, 1K) FMAP_CACHE(0x1485B400, 2K) CBFS_MCACHE(0x1485BC00,8K) REGION(dcb, 0x1485E000, 32K, 4K) REGION(pmic, 0x14866000, 96K, 4K) - REGION(qclib, 0x1487E000, 840K, 4K) + REGION(ddr_training, 0x1487E000, 32K, 4K) + REGION(qclib, 0x14886000, 800K, 4K) BSRAM_END(0x14950000) DRAM_START(0x80000000) -- To view, visit https://review.coreboot.org/c/coreboot/+/54352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81038c5c7802c154f4310509c6c64710580b8ce4 Gerrit-Change-Number: 54352 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: herobrine: Enable macronix SPI config
by Ravi kumar (Code Review) 17 May '21

17 May '21

Attention is currently required from: Shelley Chen, Ravi kumar, mturney mturney, Julius Werner. Hello Shelley Chen, build bot (Jenkins), Sajida Bhanu, mturney mturney, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50583 to look at the new patch set (#36). Change subject: herobrine: Enable macronix SPI config ...................................................................... herobrine: Enable macronix SPI config Enable macronix SPI config on herobrine board. Change-Id: I505ee95d9f2ca16baf244135b3e2e8fe72f93491 Signed-off-by: Shaik Sajida Bhanu <sbhanu(a)codeaurora.org> --- M src/mainboard/google/herobrine/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/50583/36 -- To view, visit https://review.coreboot.org/c/coreboot/+/50583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I505ee95d9f2ca16baf244135b3e2e8fe72f93491 Gerrit-Change-Number: 50583 Gerrit-PatchSet: 36 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Sajida Bhanu <sbhanu(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sc7280: Initialize SPI FW for EC and TPM
by Ravi kumar (Code Review) 17 May '21

17 May '21

Attention is currently required from: Shelley Chen, Ravi kumar, mturney mturney, Julius Werner. Hello Shelley Chen, build bot (Jenkins), mturney mturney, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50581 to look at the new patch set (#35). Change subject: sc7280: Initialize SPI FW for EC and TPM ...................................................................... sc7280: Initialize SPI FW for EC and TPM Initialize SPI firmware for EC and H1/TPM instances. Load QUP FW in respective Serial Engines. Change-Id: I8cbdd1d59a0166688d52d61646db1b6764879a7c Signed-off-by: Roja Rani Yarubandi <rojay(a)codeaurora.org> --- M src/mainboard/google/herobrine/bootblock.c M src/mainboard/google/herobrine/mainboard.c 2 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/50581/35 -- To view, visit https://review.coreboot.org/c/coreboot/+/50581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8cbdd1d59a0166688d52d61646db1b6764879a7c Gerrit-Change-Number: 50581 Gerrit-PatchSet: 35 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sc7280: add qclib support
by Ravi kumar (Code Review) 17 May '21

17 May '21

Attention is currently required from: Ravi kumar, Martin Roth, mturney mturney, Julius Werner, Sudheer Amrabadi. Hello Shelley Chen, build bot (Jenkins), Patrick Georgi, Martin Roth, mturney mturney, Julius Werner, Sudheer Amrabadi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50582 to look at the new patch set (#36). Change subject: sc7280: add qclib support ...................................................................... sc7280: add qclib support * Qclib_Ver: BOOT.MXF.1.0-00745-KODIAKLC-2 * Chipcode_Release_Tag: r00003.1 Change-Id: I2d400f0ad96dbef2e45cc1f11ed17ea95fc60d16 Signed-off-by: Sudheer Kumar Amrabadi <samrabad(a)codeaurora.org> --- M src/soc/qualcomm/sc7280/Makefile.inc M src/soc/qualcomm/sc7280/memlayout.ld 2 files changed, 27 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/50582/36 -- To view, visit https://review.coreboot.org/c/coreboot/+/50582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d400f0ad96dbef2e45cc1f11ed17ea95fc60d16 Gerrit-Change-Number: 50582 Gerrit-PatchSet: 36 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sudheer Amrabadi <samrab(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Sudheer Amrabadi <samrab(a)codeaurora.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [TEST]: adln local changes to allign with working recipe
by Usha P (Code Review) 17 May '21

17 May '21

Usha P has removed Tim Wawrzynczak from this change. ( https://review.coreboot.org/c/coreboot/+/54351 ) Change subject: [TEST]: adln local changes to allign with working recipe ...................................................................... Removed reviewer Tim Wawrzynczak. -- To view, visit https://review.coreboot.org/c/coreboot/+/54351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie87944868bf2d6a1b6b6c1e42f14d5b45b5bda02 Gerrit-Change-Number: 54351 Gerrit-PatchSet: 1 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: [TEST]: adln local changes to allign with working recipe
by Usha P (Code Review) 17 May '21

17 May '21

Attention is currently required from: Tim Wawrzynczak. Usha P has removed Patrick Rudolph from this change. ( https://review.coreboot.org/c/coreboot/+/54351 ) Change subject: [TEST]: adln local changes to allign with working recipe ...................................................................... Removed reviewer Patrick Rudolph. -- To view, visit https://review.coreboot.org/c/coreboot/+/54351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie87944868bf2d6a1b6b6c1e42f14d5b45b5bda02 Gerrit-Change-Number: 54351 Gerrit-PatchSet: 1 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: deleteReviewer

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coreboot-gerrit May 2021