coreboot-gerrit May 2021

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Change in coreboot[master]: mb/google/brya: Add support for 2 new DRAM parts
by Furquan Shaikh (Code Review) 26 May '21

26 May '21

Attention is currently required from: Tim Wawrzynczak, Amanda Hwang. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54951 ) Change subject: mb/google/brya: Add support for 2 new DRAM parts ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56bfe8aa4f8d8aab2011fa8d17b3b2c8659658e3 Gerrit-Change-Number: 54951 Gerrit-PatchSet: 2 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Thu, 27 May 2021 05:42:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add new memory parts for ADL boards
by Furquan Shaikh (Code Review) 26 May '21

26 May '21

Attention is currently required from: Tim Wawrzynczak, Amanda Hwang, Patrick Rudolph. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54950 ) Change subject: soc/intel/alderlake: Add new memory parts for ADL boards ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e76a887f81d432adbcfc2f8956b44f4343db5c2 Gerrit-Change-Number: 54950 Gerrit-PatchSet: 4 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 27 May 2021 05:41:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/spd_tools: Modify MT53E1G32D2NP-046 WT:B LPDDR4 config
by Furquan Shaikh (Code Review) 26 May '21

26 May '21

Attention is currently required from: Tim Wawrzynczak, Amanda Hwang, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55000 ) Change subject: util/spd_tools: Modify MT53E1G32D2NP-046 WT:B LPDDR4 config ...................................................................... Patch Set 1: Code-Review+2 (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55000/comment/88f3d9d2_1f668c50 PS1, Line 7: Modify Fix https://review.coreboot.org/c/coreboot/+/55000/comment/2ef0f72f_9d401ffb PS1, Line 9: Correct the attributes ranksPerChannel as 2 for LP4x global config. Can you please rephrase this to provide information about the original CL that added it as well? I think that will be helpful for future references too. Probably something like: CB:52586 ("util/spd_tools: Add MT53E1G32D2NP-046 WT:B LPDDR4 config") incorrectly set ranks per channel to 1. However, MT53E1G32D2NP-046 WT:B part has 2 channels per die and 2 physical dies. Each channel in each die shares DQ-DQS lines with the channel in other die and uses separate CS lines. Thus, number of ranks per channel is 2. This change fixes the attribute ranksPerChannel for MT53E1G32D2NP-046 WT:B in LP4x global config by setting it to 2. Patchset: PS1: Martin/Karthik - Once this lands, CB:52587 will require update too so that the correct SPD file gets used by guybrush. -- To view, visit https://review.coreboot.org/c/coreboot/+/55000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba87754ca04c2e026a9cbc8ef07412b467140cba Gerrit-Change-Number: 55000 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Thu, 27 May 2021 05:41:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Create primus variant
by Scott Chao (Code Review) 26 May '21

26 May '21

Attention is currently required from: Furquan Shaikh, Paul Menzel, Tim Wawrzynczak. Scott Chao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54941 ) Change subject: mb/google/brya: Create primus variant ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Hi Googler, can you kindly help to review this CL? Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/54941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I441e4f0ebea3b9db813e321d32ca990e9c51c668 Gerrit-Change-Number: 54941 Gerrit-PatchSet: 2 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Nick Chen <nick_xr_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 27 May 2021 05:40:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Update FADT table
by Werner Zeh (Code Review) 26 May '21

26 May '21

Attention is currently required from: Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Lean Sheng Tan, Patrick Rudolph. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54958 ) Change subject: soc/intel/elkhartlake: Update FADT table ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/elkhartlake/acpi.c: https://review.coreboot.org/c/coreboot/+/54958/comment/add09f2e_644ab783 PS3, Line 165: fadt->duty_width = 0x3; /* CLK_VAL bits 3:1 */ Well, if the bits in question starts from bit 1 (and not bit 0), I would expect fadt->duty_offset to be set to 1, or? If you do not set it here it will be set to 0 instead which would be wrong. Or is the comment wrong? -- To view, visit https://review.coreboot.org/c/coreboot/+/54958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72a57bf8ec61c3eabc4522c2695ae4b16979f188 Gerrit-Change-Number: 54958 Gerrit-PatchSet: 3 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 27 May 2021 05:34:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Minor fix for SCS & XHCI devices in ACPI
by Lean Sheng Tan (Code Review) 26 May '21

26 May '21

Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54867 ) Change subject: soc/intel/elkhartlake: Minor fix for SCS & XHCI devices in ACPI ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/54867/comment/e526c386_2f8cdee8 PS3, Line 7: soc/intel/elkhartlake: Minor fix for SCS & XHCI devices in ACPI > Please use statements in the future (by using a verb in imperative mood) [1]. […] got it, thanks for the reminder! -- To view, visit https://review.coreboot.org/c/coreboot/+/54867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1906fb4e6893dc5e2b0bc8d85f4a7b2efc85c3a4 Gerrit-Change-Number: 54867 Gerrit-PatchSet: 3 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 27 May 2021 05:31:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/stoneyridge: Set missing RTC offsets for day alarm and century
by Anand K Mistry (Code Review) 26 May '21

26 May '21

Attention is currently required from: Raul Rangel. Anand K Mistry has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55001 ) Change subject: soc/amd/stoneyridge: Set missing RTC offsets for day alarm and century ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Note, I'm still running tests, and I'll post an update in a couple of days. But I've verified the kernel sees this field and uses it when setting a wake alarm >24 hours. -- To view, visit https://review.coreboot.org/c/coreboot/+/55001 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10831b982662e680fa71aa81d02935e1b7e7a7a1 Gerrit-Change-Number: 55001 Gerrit-PatchSet: 2 Gerrit-Owner: Anand K Mistry <amistry(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Thu, 27 May 2021 05:30:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S UPD related configs
by Lean Sheng Tan (Code Review) 26 May '21

26 May '21

Attention is currently required from: Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Lean Sheng Tan, Werner Zeh, Patrick Rudolph. Hello build bot (Jenkins), Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54960 to look at the new patch set (#3). Change subject: soc/intel/elkhartlake: Update FSP-S UPD related configs ...................................................................... soc/intel/elkhartlake: Update FSP-S UPD related configs Add Silicon upd settings for: - graphics & display - chipset lockdown - PAVP - legacy timer - PCH master gating control - HECI THis CL also enables HECI 1 in devicetree.cb. Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: I657f44f8506640c23049614b2db9d1837e6d44ed --- M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb M src/soc/intel/elkhartlake/fsp_params.c 2 files changed, 60 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/54960/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/54960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I657f44f8506640c23049614b2db9d1837e6d44ed Gerrit-Change-Number: 54960 Gerrit-PatchSet: 3 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: tpm: Remove USER_TPMx options, make TPM1/TPM2 menuconfig visible
by Paul Menzel (Code Review) 26 May '21

26 May '21

Attention is currently required from: Philipp Deppenwiese, Michał Żygowski, Christian Walter, Julius Werner, Aaron Durbin, Piotr Król. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54641 ) Change subject: tpm: Remove USER_TPMx options, make TPM1/TPM2 menuconfig visible ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/54641/comment/dd0b572b_13c25854 PS3, Line 19: Also fix some mainboards that selected TPM2 directly, which they're not : supposed to do (that's what MAINBOARD_HAS_TPM2 is for), and add a : missing dependency to TPM_CR50 so it is set correctly for a NO_TPM : scenario. It’d be great if you split this into a separate commit. Patchset: PS3: Thank you for cleaning this up. -- To view, visit https://review.coreboot.org/c/coreboot/+/54641 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0a73da3c42fa4e8deffecb53f29ee38cbb51a93 Gerrit-Change-Number: 54641 Gerrit-PatchSet: 3 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Thu, 27 May 2021 05:25:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Configure WWAN GPIO early
by Varshit B Pandya (Code Review) 26 May '21

26 May '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. Varshit B Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54912 ) Change subject: mb/google/brya: Configure WWAN GPIO early ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/variants/baseboard/gpio.c: https://review.coreboot.org/c/coreboot/+/54912/comment/fe525f4e_de949503 PS2, Line 396: DEEP > As Eric mentioned, I meant capturing hardware signals to ensure timings look fine. Sure, will try to do it -- To view, visit https://review.coreboot.org/c/coreboot/+/54912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6d69696b6c645eec3fa314a608c69214bafba82 Gerrit-Change-Number: 54912 Gerrit-PatchSet: 2 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 27 May 2021 05:22:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Varshit B Pandya <varshit.b.pandya(a)intel.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit May 2021