coreboot-gerrit May 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/brya: Create primus variant
by Scott Chao (Code Review) 27 May '21

27 May '21

Attention is currently required from: Furquan Shaikh, Paul Menzel, Tim Wawrzynczak, Scott Chao. Scott Chao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54941 ) Change subject: mb/google/brya: Create primus variant ...................................................................... Patch Set 3: (2 comments) File src/mainboard/google/brya/Kconfig.name: https://review.coreboot.org/c/coreboot/+/54941/comment/077ee268_67e05055 PS2, Line 11: select BOARD_GOOGLE_BASEBOARD_BRYA > You might want to add: […] Done File src/mainboard/google/brya/variants/primus/memory/Makefile.inc: https://review.coreboot.org/c/coreboot/+/54941/comment/e0351a3a_fdccfbe2 PS2, Line 5: placeholder.spd.hex > This doesn't really exist. […] With blank(only SPD_SOURCES =), I can not build coreboot successfully. -- To view, visit https://review.coreboot.org/c/coreboot/+/54941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I441e4f0ebea3b9db813e321d32ca990e9c51c668 Gerrit-Change-Number: 54941 Gerrit-PatchSet: 3 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Nick Chen <nick_xr_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Thu, 27 May 2021 06:18:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Update FADT table
by Werner Zeh (Code Review) 27 May '21

27 May '21

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Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S UPD LPSS related configs
by Lean Sheng Tan (Code Review) 27 May '21

27 May '21

Attention is currently required from: Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54959 ) Change subject: soc/intel/elkhartlake: Update FSP-S UPD LPSS related configs ...................................................................... Patch Set 6: (2 comments) File src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb: https://review.coreboot.org/c/coreboot/+/54959/comment/efabe451_1b3b656e PS6, Line 75: [PchSerialIoIndexGSPI0] = 1, : [PchSerialIoIndexGSPI1] = 1, : [PchSerialIoIndexGSPI2] = 1, > You disable or hide the GSPI-Controllers but still enable their Chip Selct. […] Yes I just checked, this is expected. https://review.coreboot.org/c/coreboot/+/54959/comment/523ac94f_d6027737 PS6, Line 87: [PchSerialIoIndexGSPI0] = 0, : [PchSerialIoIndexGSPI1] = 0, : [PchSerialIoIndexGSPI2] = 0, > You set the chip select mode to "hardware mode" in SerialIoGSpiCsMode and then set the state to 0? T […] Yes correct this is expected also. -- To view, visit https://review.coreboot.org/c/coreboot/+/54959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0c3cd1d37ff9892d09d6d86ac50e230549c7e53 Gerrit-Change-Number: 54959 Gerrit-PatchSet: 6 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 27 May 2021 06:08:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S UPD related configs
by Werner Zeh (Code Review) 27 May '21

27 May '21

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Change in coreboot[master]: soc/intel/alderlake: Add new memory parts for ADL boards
by EricR Lai (Code Review) 27 May '21

27 May '21

Attention is currently required from: Tim Wawrzynczak, Amanda Hwang, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54950 ) Change subject: soc/intel/alderlake: Add new memory parts for ADL boards ...................................................................... Patch Set 4: Code-Review+2 (1 comment) File util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt: PS3: > Sure. Separate CL here, […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/54950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e76a887f81d432adbcfc2f8956b44f4343db5c2 Gerrit-Change-Number: 54950 Gerrit-PatchSet: 4 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 27 May 2021 06:03:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: util/spd_tools: Modify MT53E1G32D2NP-046 WT:B LPDDR4 config
by EricR Lai (Code Review) 27 May '21

27 May '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Amanda Hwang. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55000 ) Change subject: util/spd_tools: Modify MT53E1G32D2NP-046 WT:B LPDDR4 config ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/55000/comment/4452f999_25b7623b PS1, Line 9: Correct the attributes ranksPerChannel as 2 for LP4x global config. > Can you please rephrase this to provide information about the original CL that added it as well? I t […] I assume not, it only use diesperpakcage. -- To view, visit https://review.coreboot.org/c/coreboot/+/55000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba87754ca04c2e026a9cbc8ef07412b467140cba Gerrit-Change-Number: 55000 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Thu, 27 May 2021 06:02:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S UPD related configs
by Werner Zeh (Code Review) 26 May '21

26 May '21

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Change in coreboot[master]: soc/intel/elkhartlake: Update FADT table
by Lean Sheng Tan (Code Review) 26 May '21

26 May '21

Attention is currently required from: Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54958 ) Change subject: soc/intel/elkhartlake: Update FADT table ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/elkhartlake/acpi.c: https://review.coreboot.org/c/coreboot/+/54958/comment/6e1887ce_a3c51e25 PS3, Line 165: fadt->duty_width = 0x3; /* CLK_VAL bits 3:1 */ > Well, if the bits in question starts from bit 1 (and not bit 0), I would expect fadt->duty_offset to […] Hi Werner, dont worry the duty offset has been set in common codes, so i dont want to replicate again here. The changes here is the delta on top of common codes: https://github.com/coreboot/coreboot/blob/master/src/soc/intel/common/block… -- To view, visit https://review.coreboot.org/c/coreboot/+/54958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72a57bf8ec61c3eabc4522c2695ae4b16979f188 Gerrit-Change-Number: 54958 Gerrit-PatchSet: 3 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 27 May 2021 05:57:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S UPD LPSS related configs
by Werner Zeh (Code Review) 26 May '21

26 May '21

Attention is currently required from: Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Lean Sheng Tan, Patrick Rudolph. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54959 ) Change subject: soc/intel/elkhartlake: Update FSP-S UPD LPSS related configs ...................................................................... Patch Set 6: (4 comments) File src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb: https://review.coreboot.org/c/coreboot/+/54959/comment/ed821cd7_391eacd1 PS6, Line 75: [PchSerialIoIndexGSPI0] = 1, : [PchSerialIoIndexGSPI1] = 1, : [PchSerialIoIndexGSPI2] = 1, You disable or hide the GSPI-Controllers but still enable their Chip Selct. Is this what you want? https://review.coreboot.org/c/coreboot/+/54959/comment/e6e1c9de_1ca7fd08 PS6, Line 87: [PchSerialIoIndexGSPI0] = 0, : [PchSerialIoIndexGSPI1] = 0, : [PchSerialIoIndexGSPI2] = 0, You set the chip select mode to "hardware mode" in SerialIoGSpiCsMode and then set the state to 0? This means that chip select is active all the time. Is this something you really want or have a got it wrong? File src/soc/intel/elkhartlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/54959/comment/181d6aa4_26ca7832 PS6, Line 65: 0x1B44AC09; Since you use constants here: Would you mind to add a comment which describes these values? https://review.coreboot.org/c/coreboot/+/54959/comment/79359f92_83c3a38e PS6, Line 102: params->SerialIoUartCtsPinMuxPolicy[0] = 0x2B01320F; : params->SerialIoUartRtsPinMuxPolicy[0] = 0x2B01220E; : params->SerialIoUartRxPinMuxPolicy[0] = 0x2B01020C; : params->SerialIoUartTxPinMuxPolicy[0] = 0x2B01120D; A comment describing the values would be nice here. -- To view, visit https://review.coreboot.org/c/coreboot/+/54959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0c3cd1d37ff9892d09d6d86ac50e230549c7e53 Gerrit-Change-Number: 54959 Gerrit-PatchSet: 6 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 27 May 2021 05:55:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Create primus variant
by Furquan Shaikh (Code Review) 26 May '21

26 May '21

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Scott Chao. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54941 ) Change subject: mb/google/brya: Create primus variant ...................................................................... Patch Set 2: (3 comments) File src/mainboard/google/brya/Kconfig.name: https://review.coreboot.org/c/coreboot/+/54941/comment/a3a0c027_b34bcc8a PS2, Line 5: select BOARD_ROMSIZE_KB_32768 Not for this change, but this should be dropped from here since it is selected by BOARD_GOOGLE_BASEBOARD_BRYA already. @Tim. https://review.coreboot.org/c/coreboot/+/54941/comment/11a52ac0_06bf579a PS2, Line 11: select BOARD_GOOGLE_BASEBOARD_BRYA You might want to add: `select BASEBOARD_BRYA_LAPTOP` File src/mainboard/google/brya/variants/primus/memory/Makefile.inc: https://review.coreboot.org/c/coreboot/+/54941/comment/8cf88d68_b6a54c86 PS2, Line 5: placeholder.spd.hex This doesn't really exist. Probably just leave this blank? -- To view, visit https://review.coreboot.org/c/coreboot/+/54941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I441e4f0ebea3b9db813e321d32ca990e9c51c668 Gerrit-Change-Number: 54941 Gerrit-PatchSet: 2 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Nick Chen <nick_xr_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Thu, 27 May 2021 05:48:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit May 2021