coreboot-gerrit May 2021

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Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S UPD LPSS related configs
by Lean Sheng Tan (Code Review) 27 May '21

27 May '21

Attention is currently required from: Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph. Hello build bot (Jenkins), Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54959 to look at the new patch set (#7). Change subject: soc/intel/elkhartlake: Update FSP-S UPD LPSS related configs ...................................................................... soc/intel/elkhartlake: Update FSP-S UPD LPSS related configs Add Silicon upd settings for LPSS (GSPI/UART/I2C). Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: Ib0c3cd1d37ff9892d09d6d86ac50e230549c7e53 --- M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/fsp_params.c 3 files changed, 136 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/54959/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/54959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0c3cd1d37ff9892d09d6d86ac50e230549c7e53 Gerrit-Change-Number: 54959 Gerrit-PatchSet: 7 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S UPD related configs
by Lean Sheng Tan (Code Review) 27 May '21

27 May '21

Attention is currently required from: Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Patrick Rudolph. Hello build bot (Jenkins), Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54960 to look at the new patch set (#4). Change subject: soc/intel/elkhartlake: Update FSP-S UPD related configs ...................................................................... soc/intel/elkhartlake: Update FSP-S UPD related configs Add Silicon upd settings for: - graphics & display - chipset lockdown - PAVP - legacy timer - PCH master gating control - HECI THis CL also enables HECI 1 in devicetree.cb. Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: I657f44f8506640c23049614b2db9d1837e6d44ed --- M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb M src/soc/intel/elkhartlake/fsp_params.c 2 files changed, 59 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/54960/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/54960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I657f44f8506640c23049614b2db9d1837e6d44ed Gerrit-Change-Number: 54960 Gerrit-PatchSet: 4 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/volteer/var/collis: Update DPTF parameters
by Frank Chu (Code Review) 27 May '21

27 May '21

Attention is currently required from: Nick Vaccaro, Zhuohao Lee. Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54858 ) Change subject: mb/google/volteer/var/collis: Update DPTF parameters ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/54858/comment/e0948951_5957c892 PS2, Line 12: coreboot > nit: remove this Done -- To view, visit https://review.coreboot.org/c/coreboot/+/54858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id14b1d0bdd48c65eafbdd2e80b4611c86781be00 Gerrit-Change-Number: 54858 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Thu, 27 May 2021 07:38:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/var/collis: Update DPTF parameters
by Frank Chu (Code Review) 27 May '21

27 May '21

Attention is currently required from: Frank Chu, Nick Vaccaro, Zhuohao Lee. Hello build bot (Jenkins), Tim Wawrzynczak, Sumeet R Pawnikar, Nick Vaccaro, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54858 to look at the new patch set (#3). Change subject: mb/google/volteer/var/collis: Update DPTF parameters ...................................................................... mb/google/volteer/var/collis: Update DPTF parameters Update the first version DPTF parameters received from the thermal team. BUG=b:188936764 TEST=emerge-volteer coreboot chromeos-bootimage Cq-Depend: chrome-internal:3851737 Signed-off-by: FrankChu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: Id14b1d0bdd48c65eafbdd2e80b4611c86781be00 --- M src/mainboard/google/volteer/variants/collis/overridetree.cb 1 file changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/54858/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/54858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id14b1d0bdd48c65eafbdd2e80b4611c86781be00 Gerrit-Change-Number: 54858 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: amdfwtool: Set the region_type as 0 for entry "BIOS level 2"
by Bao Zheng (Code Review) 27 May '21

27 May '21

Attention is currently required from: Raul Rangel, Paul Menzel, Zheng Bao. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54871 ) Change subject: amdfwtool: Set the region_type as 0 for entry "BIOS level 2" ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/54871/comment/40bdd473_c2e81317 PS2, Line 9: But we need to set it explicitly as : a known value. > Why? According to some specification? Please document that. It should be set as something, FF or 0. Both seem to be OK. It means nothing in the type 40h entry(pointer to L2). It really is not in any documents. -- To view, visit https://review.coreboot.org/c/coreboot/+/54871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b914f9f02beecce707aba86248826cd9208e6c0 Gerrit-Change-Number: 54871 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Thu, 27 May 2021 07:00:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: acpi: Add support for reporting CrashLog in BERT table
by Francois Toguo Fotso (Code Review) 27 May '21

27 May '21

Francois Toguo Fotso has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49799 ) Change subject: acpi: Add support for reporting CrashLog in BERT table ...................................................................... Patch Set 10: (5 comments) Patchset: PS10: This picture has to be used as reference to fully understand the changes. They are valid, as fully verified in the CrashLog flow. Explanations are provided below. I still believe updating your data offset would be a more sounds approach; however we will move the raw data tracking to the Intel SOC common code. Which is one of several possible WA to unblocking you. +-------------------------------------------------------------------+ | Boot Error Region (ACPI 6.3 - Table 18-381) | | +---------------------------------------------------------------+ | | | Generic Error Status Block (ACPI 6.3 - Table 18-391) | | | | +-----------------------------------------------------------+ | | | | | Generic Data Error Data Entry (ACPI 6.3 - Table 18-392) | | | | | | +-------------------------------------------------------+ | | | | | | | CPER FW Error Record Reference (UEFI 2.8 - N.2.10) | | | | | | | | +---------------------------------------------------+ | | | | | | | | | Crash Log Region #1 | | | | | | | | | +---------------------------------------------------+ | | | | | | | +-------------------------------------------------------+ | | | | | +-----------------------------------------------------------+ | | | | | Generic Data Error Data Entry (ACPI 6.3 - Table 18-392) | | | | | | +-------------------------------------------------------+ | | | | | | | CPER FW Error Record Reference (UEFI 2.8 - N.2.10) | | | | | | | | +---------------------------------------------------+ | | | | | | | | | Crash Log Region #2 | | | | | | | | | +---------------------------------------------------+ | | | | | | | +-------------------------------------------------------+ | | | | | +-----------------------------------------------------------+ | | | | | ... | | | | | +-----------------------------------------------------------+ | | | | | Generic Data Error Data Entry (ACPI 6.3 - Table 18-392) | | | | | | +-------------------------------------------------------+ | | | | | | | CPER FW Error Record Reference (UEFI 2.8 - N.2.10) | | | | | | | | +---------------------------------------------------+ | | | | | | | | | Crash Log Region #n | | | | | | | | | +---------------------------------------------------+ | | | | | | | +-------------------------------------------------------+ | | | | | +-----------------------------------------------------------+ | | | +---------------------------------------------------------------+ | +-------------------------------------------------------------------+ File src/arch/x86/acpi_bert_storage.c: PS10: > It was also part of the 6.2 spec that was active when the code was written. […] Correct, there is no requirement to report this, but it is used in the by the Intel SOC decoding flow. For the "common good" we will tentatively be using another reporting work around in the Intel SOC specific code. https://review.coreboot.org/c/coreboot/+/49799/comment/8a2f545d_b5257acf PS10, Line 109: status->raw_data_length += size; > This doesn't seem right. […] Actually this is right ant makes sense. The size applies to both because the "raw data" are part (sub-section) of the generic section. And in the case there are additional (non register) info in the generic section, they are also "raw data" since there contains IP level info. The picture below captures this well and should remove the confusion. +-------------------------------------------------------------------+ | Boot Error Region (ACPI 6.3 - Table 18-381) | | +---------------------------------------------------------------+ | | | Generic Error Status Block (ACPI 6.3 - Table 18-391) | | | | +-----------------------------------------------------------+ | | | | | Generic Data Error Data Entry (ACPI 6.3 - Table 18-392) | | | | | | +-------------------------------------------------------+ | | | | | | | CPER FW Error Record Reference (UEFI 2.8 - N.2.10) | | | | | | | | +---------------------------------------------------+ | | | | | | | | | Crash Log Region #1 | | | | | | | | | +---------------------------------------------------+ | | | | | | | +-------------------------------------------------------+ | | | | | +-----------------------------------------------------------+ | | | | | Generic Data Error Data Entry (ACPI 6.3 - Table 18-392) | | | | | | +-------------------------------------------------------+ | | | | | | | CPER FW Error Record Reference (UEFI 2.8 - N.2.10) | | | | | | | | +---------------------------------------------------+ | | | | | | | | | Crash Log Region #2 | | | | | | | | | +---------------------------------------------------+ | | | | | | | +-------------------------------------------------------+ | | | | | +-----------------------------------------------------------+ | | | | | ... | | | | | +-----------------------------------------------------------+ | | | | | Generic Data Error Data Entry (ACPI 6.3 - Table 18-392) | | | | | | +-------------------------------------------------------+ | | | | | | | CPER FW Error Record Reference (UEFI 2.8 - N.2.10) | | | | | | | | +---------------------------------------------------+ | | | | | | | | | Crash Log Region #n | | | | | | | | | +---------------------------------------------------+ | | | | | | | +-------------------------------------------------------+ | | | | | +-----------------------------------------------------------+ | | | +---------------------------------------------------------------+ | +-------------------------------------------------------------------+ That change is valid, an working just fine with Chrome. But to prevent disturbance/noises to your AMD flow with linux flow, it will be pulled into the intel SOC common code. https://review.coreboot.org/c/coreboot/+/49799/comment/af3438cb_1db519d3 PS10, Line 178: status->raw_data_length += sizeof(*entry); > This is a generic error entry. Raw data length doesn't come into play here. Same explanations above applies here. Raw data are part/section of the generic error entry. https://review.coreboot.org/c/coreboot/+/49799/comment/6fa0295a_2dd11882 PS10, Line 531: status->raw_data_length = sizeof(*status); > I don't understand this. […] These 20 bytes need to be accounted for during the data analysis in the Intel decoder. Once again this will tracked at the intel SOC common code level. so for now you can proceed with CB:54738 -- To view, visit https://review.coreboot.org/c/coreboot/+/49799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00e390d735d61beac2e89a726e39119d9b06b3df Gerrit-Change-Number: 49799 Gerrit-PatchSet: 10 Gerrit-Owner: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nikunj Dadhania <nikunj.dadhania(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Comment-Date: Thu, 27 May 2021 06:44:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: src/intel/microcode: Add support for extended signature table
by Werner Zeh (Code Review) 27 May '21

27 May '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54734 ) Change subject: src/intel/microcode: Add support for extended signature table ...................................................................... src/intel/microcode: Add support for extended signature table Microcode header supports advertising support for only one CPU signature and processor flags. If there are multiple processor families supported by this microcode blob, they are mentioned in the extended signature table. Add support to parse the extended processor signature table to determine if the microcode blob supports the currently running CPU. BUG=b:182234962 TEST=Booted ADL brya system with a processor whose signature/pf are in the extended signature table of a microcode patch. Was able to match and load the patch appropriately. Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Change-Id: I1466caf4a4ba1f9a0214bdde19cce57dd65dacbd Reviewed-on: https://review.coreboot.org/c/coreboot/+/54734 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/cpu/intel/microcode/microcode.c 1 file changed, 50 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Arthur Heymans: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 51823ca..45996df 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -29,6 +29,18 @@ u32 reserved[3]; }; +struct ext_sig_table { + u32 ext_sig_cnt; + u32 ext_tbl_chksm; + u32 res[3]; +}; + +struct ext_sig_entry { + u32 sig; + u32 pf; + u32 chksm; +}; + static inline u32 read_microcode_rev(void) { /* Some Intel CPUs can be very finicky about the @@ -117,9 +129,31 @@ return ((struct microcode *)microcode)->cksum; } + +static struct ext_sig_table *ucode_get_ext_sig_table(const struct microcode *ucode) +{ + struct ext_sig_table *ext_tbl; + /* header + ucode data blob size */ + u32 size = ucode->data_size + sizeof(struct microcode); + + size_t ext_tbl_len = ucode->total_size - size; + + if (ext_tbl_len < sizeof(struct ext_sig_table)) + return NULL; + + ext_tbl = (struct ext_sig_table *)((uintptr_t)ucode + size); + + if (ext_tbl_len < (sizeof(struct ext_sig_table) + + ext_tbl->ext_sig_cnt * sizeof(struct ext_sig_entry))) + return NULL; + + return ext_tbl; +} + static const void *find_cbfs_microcode(void) { const struct microcode *ucode_updates; + struct ext_sig_table *ext_tbl; size_t microcode_len; u32 eax; u32 pf, rev, sig, update_size; @@ -163,6 +197,22 @@ if ((ucode_updates->sig == sig) && (ucode_updates->pf & pf)) return ucode_updates; + + /* Check if there is extended signature table */ + ext_tbl = ucode_get_ext_sig_table(ucode_updates); + + if (ext_tbl != NULL) { + int i; + struct ext_sig_entry *entry = (struct ext_sig_entry *)(ext_tbl + 1); + + for (i = 0; i < ext_tbl->ext_sig_cnt; i++, entry++) { + + if ((sig == entry->sig) && (pf & entry->pf)) { + return ucode_updates; + } + } + } + ucode_updates = (void *)((char *)ucode_updates + update_size); microcode_len -= update_size; } -- To view, visit https://review.coreboot.org/c/coreboot/+/54734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1466caf4a4ba1f9a0214bdde19cce57dd65dacbd Gerrit-Change-Number: 54734 Gerrit-PatchSet: 8 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: amdfwtool: Add a function to extract firmwares
by Bao Zheng (Code Review) 27 May '21

27 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Zheng Bao, Felix Held. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54901 ) Change subject: amdfwtool: Add a function to extract firmwares ...................................................................... Patch Set 6: (1 comment) File util/amdfwtool/extract.c: https://review.coreboot.org/c/coreboot/+/54901/comment/fb5f0234_1d9ddc4a PS6, Line 91: PspDirL10_Typex > What's the 0 there, i.e. L10? Is the plan to replace that with the subprogram value? […] L2 maybe has 2A or 2B or only L2, so an extra digit is reserved for future TODO. -- To view, visit https://review.coreboot.org/c/coreboot/+/54901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74a6c7ff56cc11530695d1068763ecdd86282a17 Gerrit-Change-Number: 54901 Gerrit-PatchSet: 6 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 27 May 2021 06:28:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: Initialize ap in `usb_debug()`
by Paul Menzel (Code Review) 27 May '21

27 May '21

Paul Menzel has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/51916 ) Change subject: libpayload: Initialize ap in `usb_debug()` ...................................................................... Abandoned Fix missing braces in Ic19db5e49951eab1b5a4fa7c50a6812e3b35e131 (https://review.coreboot.org/c/coreboot/+/51915). -- To view, visit https://review.coreboot.org/c/coreboot/+/51916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2fd0b25c8456a2e14c51ab85d67c645481d50e9 Gerrit-Change-Number: 51916 Gerrit-PatchSet: 5 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: libpayload: curses: Only call `serial_set_color()` with initialized v...
by Paul Menzel (Code Review) 27 May '21

27 May '21

Attention is currently required from: Paul Menzel, Jacob Garber. Hello build bot (Jenkins), Nico Huber, Angel Pons, Jacob Garber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51914 to look at the new patch set (#6). Change subject: libpayload: curses: Only call `serial_set_color()` with initialized values ...................................................................... libpayload: curses: Only call `serial_set_color()` with initialized values Building nvramcui with i386-elf-gcc (coreboot toolchain v2021-04-06_7014f8258e) 8.3.0 and Link Time Optimization (LTO) enabled in libpayload (`CONFIG_LP_LTO=y`) fails with the error below. LPGCC nvramcui.bin curses/PDCurses/pdcurses/refresh.c: In function 'wrefresh': curses/pdcurses-backend/pdcdisp.c:217:4: error: 'bg' may be used uninitialized in this function [-Werror=maybe-uninitialized] curses/pdcurses-backend/pdcdisp.c:214:18: note: 'bg' was declared here curses/pdcurses-backend/pdcdisp.c:217:4: error: 'fg' may be used uninitialized in this function [-Werror=maybe-uninitialized] curses/pdcurses-backend/pdcdisp.c:214:14: note: 'fg' was declared here lto1: all warnings being treated as errors lto-wrapper: fatal error: i386-elf-gcc returned 1 exit status compilation terminated. /opt/xgcc/lib/gcc/i386-elf/8.3.0/../../../../i386-elf/bin/ld.bfd: error: lto-wrapper failed collect2: error: ld returned 1 exit status `pair_content()` returns in case `PAIR_NUMBER(attr)` is invalid, so guard the usage of `serial_set_color()`. if (pair < 0 || pair >= COLOR_PAIRS || !fg || !bg) return ERR; Note, building with x86_64-linux-gnu-gcc-10 (Debian 10.2.1-6) 10.2.1 20210110 does *not* fail. Change-Id: Ic63e34f2b5bc9f826db37597bebc6b20542481d7 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M payloads/libpayload/curses/pdcurses-backend/pdcdisp.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/51914/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/51914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic63e34f2b5bc9f826db37597bebc6b20542481d7 Gerrit-Change-Number: 51914 Gerrit-PatchSet: 6 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newpatchset

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coreboot-gerrit May 2021