coreboot-gerrit May 2021

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Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S UPD related configs
by Paul Menzel (Code Review) 27 May '21

27 May '21

Attention is currently required from: Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Lean Sheng Tan, Werner Zeh, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54960 ) Change subject: soc/intel/elkhartlake: Update FSP-S UPD related configs ...................................................................... Patch Set 5: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/54960/comment/8b2edd06_73b05cff PS5, Line 2: Author: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> It’d be great if you used *Lean Sheng Tan*. $ git config --global author.name "Lean Sheng Tan" $ git commit --amend --author="Lean Sheng Tan <lean.sheng.tan(a)intel.com>" https://review.coreboot.org/c/coreboot/+/54960/comment/3b3cf203_f7841688 PS5, Line 9: Silicon upd silicon UPD https://review.coreboot.org/c/coreboot/+/54960/comment/cbc59c05_3e9fa567 PS5, Line 17: THis This https://review.coreboot.org/c/coreboot/+/54960/comment/d48e6eb7_117218fa PS5, Line 18: Did the board boot before? If not, what error is fixed? -- To view, visit https://review.coreboot.org/c/coreboot/+/54960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I657f44f8506640c23049614b2db9d1837e6d44ed Gerrit-Change-Number: 54960 Gerrit-PatchSet: 5 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 27 May 2021 08:01:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S UPD related configs
by Lean Sheng Tan (Code Review) 27 May '21

27 May '21

Attention is currently required from: Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54960 ) Change subject: soc/intel/elkhartlake: Update FSP-S UPD related configs ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/elkhartlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/54960/comment/b88071aa_d373e617 PS3, Line 102: unsigned int i; > Unused, causes build to fail! Done -- To view, visit https://review.coreboot.org/c/coreboot/+/54960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I657f44f8506640c23049614b2db9d1837e6d44ed Gerrit-Change-Number: 54960 Gerrit-PatchSet: 5 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 27 May 2021 07:58:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/{mc_apl2,...,mc_apl6}: Do early UART pad configuration
by Mario Scheithauer (Code Review) 27 May '21

27 May '21

Attention is currently required from: Paul Menzel, Werner Zeh. Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54911 ) Change subject: mb/siemens/{mc_apl2,...,mc_apl6}: Do early UART pad configuration ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/54911/comment/32776630_7132b5f7 PS1, Line 9: CB:48829 > As the tool `git` works with commit hashes, it’d be great to have these also used as reference. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/54911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If78726d9b141e4e7580cca3267f49c1a5b95d7fa Gerrit-Change-Number: 54911 Gerrit-PatchSet: 3 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Thu, 27 May 2021 07:56:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/stoneyridge: Set missing RTC offsets for day alarm and century
by Paul Menzel (Code Review) 27 May '21

27 May '21

Attention is currently required from: Raul Rangel, Martin Roth, Anand K Mistry. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55001 ) Change subject: soc/amd/stoneyridge: Set missing RTC offsets for day alarm and century ...................................................................... Patch Set 2: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55001/comment/7dec77c4_adf8b15f PS2, Line 8: Please describe the problem (summarize the bug report). It sounds like suspend/resume does not work? https://review.coreboot.org/c/coreboot/+/55001/comment/d641c255_4cbd7342 PS2, Line 12: This is a mirror of commit 041fcf59025bb1801828441e09b2f56b48e12fdc made Please abbreviate the commit hash and add the summary: > 041fcf5902 (soc/amd/picasso/acpi: Set missing RTC offsets) File src/soc/amd/stoneyridge/acpi.c: https://review.coreboot.org/c/coreboot/+/55001/comment/37412ac0_8fa97469 PS2, Line 86: fadt->mon_alrm = 0; Excuse my ignorance, but is `mon_alrm` not needed, or at offset 0? https://review.coreboot.org/c/coreboot/+/55001/comment/601caf1e_82e5f838 PS2, Line 85: fadt->day_alrm = 0x0d; : fadt->mon_alrm = 0; : For amd/cezanne defines are used (Ib6c3a01084a0de33894885b47c637a292d252ed4 [1]). It’d be great if you could do the same in a followup. [1]: https://review.coreboot.org/c/coreboot/+/50510 -- To view, visit https://review.coreboot.org/c/coreboot/+/55001 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10831b982662e680fa71aa81d02935e1b7e7a7a1 Gerrit-Change-Number: 55001 Gerrit-PatchSet: 2 Gerrit-Owner: Anand K Mistry <amistry(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Kurtz <djkurtz(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Anand K Mistry <amistry(a)google.com> Gerrit-Comment-Date: Thu, 27 May 2021 07:55:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S UPD LPSS related configs
by Lean Sheng Tan (Code Review) 27 May '21

27 May '21

Attention is currently required from: Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph. Hello build bot (Jenkins), Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54959 to look at the new patch set (#8). Change subject: soc/intel/elkhartlake: Update FSP-S UPD LPSS related configs ...................................................................... soc/intel/elkhartlake: Update FSP-S UPD LPSS related configs Add Silicon upd settings for LPSS (GSPI/UART/I2C). Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: Ib0c3cd1d37ff9892d09d6d86ac50e230549c7e53 --- M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/fsp_params.c 3 files changed, 136 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/54959/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/54959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0c3cd1d37ff9892d09d6d86ac50e230549c7e53 Gerrit-Change-Number: 54959 Gerrit-PatchSet: 8 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: amdfwtool: Set the region_type as 0 for entry "BIOS level 2"
by Paul Menzel (Code Review) 27 May '21

27 May '21

Attention is currently required from: Bao Zheng, Raul Rangel, Zheng Bao. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54871 ) Change subject: amdfwtool: Set the region_type as 0 for entry "BIOS level 2" ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/54871/comment/876650ff_3a2866db PS2, Line 9: But we need to set it explicitly as : a known value. > It should be set as something, FF or 0. Both seem to be OK. […] Thanks, though that’s unfortunate. Please amend the commit message, and describe the problem then. What does not work without this change? -- To view, visit https://review.coreboot.org/c/coreboot/+/54871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b914f9f02beecce707aba86248826cd9208e6c0 Gerrit-Change-Number: 54871 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Thu, 27 May 2021 07:44:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bao Zheng <fishbaozi(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/mc_apl{1,2,3,5,6}: Disable ACPI-support for RX6110
by Werner Zeh (Code Review) 27 May '21

27 May '21

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55004 ) Change subject: mb/siemens/mc_apl{1,2,3,5,6}: Disable ACPI-support for RX6110 ...................................................................... mb/siemens/mc_apl{1,2,3,5,6}: Disable ACPI-support for RX6110 Already released Linux versions did not have the needed ACPI-extension in the RTC driver. If the ACPI-Support is enabled for the RTC, this older Linux will not be able to use this device as it will be claimed by the PNP-drivers. As there is no way to avoid that an older Linux kernel meets a newer coreboot in the field, we need to disable the ACPI support for the RTC for the mc_apl-based mainboards. Change-Id: I9f9939ba3234dc3654a4ef8a498649453941ebdf Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig 5 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/55004/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig index 8b10a74..ae76f7b 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig @@ -5,6 +5,7 @@ def_bool y select DRIVER_INTEL_I210 select DRIVERS_I2C_RX6110SA + select RX6110SA_DISABLE_ACPI select DRIVER_SIEMENS_NC_FPGA select NC_FPGA_NOTIFY_CB_READY select APL_SKIP_SET_POWER_LIMITS diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig index 86244a2..c1ec2eb 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig @@ -5,6 +5,7 @@ def_bool y select DRIVER_INTEL_I210 select DRIVERS_I2C_RX6110SA + select RX6110SA_DISABLE_ACPI select DRIVER_SIEMENS_NC_FPGA select MAINBOARD_HAS_TPM2 select MAINBOARD_HAS_LPC_TPM diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig index 32db935b..d690157 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig @@ -5,6 +5,7 @@ def_bool y select DRIVER_INTEL_I210 select DRIVERS_I2C_RX6110SA + select RX6110SA_DISABLE_ACPI select DRIVER_SIEMENS_NC_FPGA select NC_FPGA_NOTIFY_CB_READY select APL_SKIP_SET_POWER_LIMITS diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig index 71dfa0b..c82c840 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig @@ -5,6 +5,7 @@ def_bool y select DRIVER_INTEL_I210 select DRIVERS_I2C_RX6110SA + select RX6110SA_DISABLE_ACPI select DRIVER_SIEMENS_NC_FPGA select NC_FPGA_NOTIFY_CB_READY select APL_SKIP_SET_POWER_LIMITS diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig index b34c9d8..44bff7c 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig @@ -5,6 +5,7 @@ def_bool y select DRIVER_INTEL_I210 select DRIVERS_I2C_RX6110SA + select RX6110SA_DISABLE_ACPI select DRIVER_SIEMENS_NC_FPGA select NC_FPGA_NOTIFY_CB_READY select APL_SKIP_SET_POWER_LIMITS -- To view, visit https://review.coreboot.org/c/coreboot/+/55004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f9939ba3234dc3654a4ef8a498649453941ebdf Gerrit-Change-Number: 55004 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/i2c/rx6110sa: Add a Kconfig switch to disable ACPI support
by Werner Zeh (Code Review) 27 May '21

27 May '21

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55003 ) Change subject: drivers/i2c/rx6110sa: Add a Kconfig switch to disable ACPI support ...................................................................... drivers/i2c/rx6110sa: Add a Kconfig switch to disable ACPI support In commit b64db833d6db452c28e410f869f6527fd6971228 a basic ACPI support was added to the driver. With this support an SSDT-entry is created for this RTC and it is now visible to the OS via ACPI. In Linux the PNP-devices, which are reported over ACPI, are scanned rather early and if the entry is found, the device is claimed even if there is no driver available yet. In this case, when the native RTC-driver without ACPI-support is loaded and tries to register this device, the RTC is already blocked by the PNP-drivers and cannot be used anymore. This leads to a non-usable RTC on kernels where the needed ACPI-extension is not yet merged into the RTC driver. This patch provides a way to disable the ACPI-support for the RTC if needed. Change-Id: Ic65794d409d13a78d17275c86ec14ee6f04cd2a6 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/drivers/i2c/rx6110sa/Kconfig M src/drivers/i2c/rx6110sa/rx6110sa.c 2 files changed, 9 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/55003/1 diff --git a/src/drivers/i2c/rx6110sa/Kconfig b/src/drivers/i2c/rx6110sa/Kconfig index a5608f8..7f3febc 100644 --- a/src/drivers/i2c/rx6110sa/Kconfig +++ b/src/drivers/i2c/rx6110sa/Kconfig @@ -3,3 +3,10 @@ default n help Enable support for external RTC chip RX6110 SA. + +config RX6110SA_DISABLE_ACPI + bool + default n + help + Disable the generation of an ACPI entry for this RTC. This is helpful + when the native driver for this RTC in OS does not have ACPI support enabled. diff --git a/src/drivers/i2c/rx6110sa/rx6110sa.c b/src/drivers/i2c/rx6110sa/rx6110sa.c index 2b8b9b2..3cab8fa 100644 --- a/src/drivers/i2c/rx6110sa/rx6110sa.c +++ b/src/drivers/i2c/rx6110sa/rx6110sa.c @@ -166,7 +166,7 @@ rx6110sa_write(dev, CTRL_REG, reg); } -#if CONFIG(HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) && !CONFIG(RX6110SA_DISABLE_ACPI) static void rx6110sa_fill_ssdt(const struct device *dev) { struct drivers_i2c_rx6110sa_config *config = dev->chip_info; @@ -227,7 +227,7 @@ .set_resources = noop_set_resources, .init = rx6110sa_init, .final = rx6110sa_final, -#if CONFIG(HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) && !CONFIG(RX6110SA_DISABLE_ACPI) .acpi_name = rx6110sa_acpi_name, .acpi_fill_ssdt = rx6110sa_fill_ssdt, #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/55003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic65794d409d13a78d17275c86ec14ee6f04cd2a6 Gerrit-Change-Number: 55003 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S UPD LPSS related configs
by Lean Sheng Tan (Code Review) 27 May '21

27 May '21

Attention is currently required from: Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54959 ) Change subject: soc/intel/elkhartlake: Update FSP-S UPD LPSS related configs ...................................................................... Patch Set 7: (2 comments) File src/soc/intel/elkhartlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/54959/comment/f7579cb4_d0625cd9 PS6, Line 65: 0x1B44AC09; > Since you use constants here: Would you mind to add a comment which describes these values? Done https://review.coreboot.org/c/coreboot/+/54959/comment/8fa8ee59_c8f10c91 PS6, Line 102: params->SerialIoUartCtsPinMuxPolicy[0] = 0x2B01320F; : params->SerialIoUartRtsPinMuxPolicy[0] = 0x2B01220E; : params->SerialIoUartRxPinMuxPolicy[0] = 0x2B01020C; : params->SerialIoUartTxPinMuxPolicy[0] = 0x2B01120D; > A comment describing the values would be nice here. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/54959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0c3cd1d37ff9892d09d6d86ac50e230549c7e53 Gerrit-Change-Number: 54959 Gerrit-PatchSet: 7 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 27 May 2021 07:41:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S UPD LPSS related configs
by build bot (Jenkins) (Code Review) 27 May '21

27 May '21

Attention is currently required from: Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54959 ) Change subject: soc/intel/elkhartlake: Update FSP-S UPD LPSS related configs ...................................................................... Patch Set 7: (2 comments) File src/soc/intel/elkhartlake/fsp_params.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120151): https://review.coreboot.org/c/coreboot/+/54959/comment/40f11312_1d47162c PS7, Line 104: params->SerialIoUartRxPinMuxPolicy[0] = 0x2B01020C; //GPIO pin mux for GPP_T12 line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120151): https://review.coreboot.org/c/coreboot/+/54959/comment/52105e8e_88a8816e PS7, Line 105: params->SerialIoUartTxPinMuxPolicy[0] = 0x2B01120D; //GPIO pin mux for GPP_T13 line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/54959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0c3cd1d37ff9892d09d6d86ac50e230549c7e53 Gerrit-Change-Number: 54959 Gerrit-PatchSet: 7 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 27 May 2021 07:40:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit May 2021