coreboot-gerrit May 2021

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Change in coreboot[master]: drivers/intel/fsp1_1: Drop some MMA leftovers
by Felix Held (Code Review) 27 May '21

27 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54954 ) Change subject: drivers/intel/fsp1_1: Drop some MMA leftovers ...................................................................... drivers/intel/fsp1_1: Drop some MMA leftovers Commit 736a1028fbaef97d32221cadb1f512c9a8960a76 (drivers/intel/fsp1_1: Drop dead MMA code) dropped FSP 1.1 MMA code, but missed a few things. Change-Id: I556e7125eff21c49609bb1e5e1f23e99e692756f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54954 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/drivers/intel/fsp1_1/include/fsp/romstage.h 1 file changed, 0 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index db4b352..99dd9b8 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -8,7 +8,6 @@ #include <memory_info.h> #include <fsp/car.h> #include <fsp/util.h> -#include <soc/intel/common/mma.h> #include <soc/pm.h> struct romstage_params { @@ -42,9 +41,6 @@ void soc_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *upd); void soc_pre_ram_init(struct romstage_params *params); -/* Update the SOC specific memory config param for mma. */ -void soc_update_memory_params_for_mma(MEMORY_INIT_UPD *memory_cfg, - struct mma_config_param *mma_cfg); void mainboard_after_memory_init(void); #endif /* _COMMON_ROMSTAGE_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/54954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I556e7125eff21c49609bb1e5e1f23e99e692756f Gerrit-Change-Number: 54954 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/mancomb: set PSPP policy to balanced
by Felix Held (Code Review) 27 May '21

27 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54933 ) Change subject: mb/google/mancomb: set PSPP policy to balanced ...................................................................... mb/google/mancomb: set PSPP policy to balanced Not sure which policy we should select here or if that should be done in the board-specific devicetree overrides instead of the baseboard. BUG=b:188793754 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I792d909ce75cb73571c9fec58c18f749ea3ae029 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54933 Reviewed-by: Matt Papageorge <matthewpapa07(a)gmail.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/mancomb/variants/baseboard/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Matt Papageorge: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb index 329abbe..8f89dd0 100644 --- a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb @@ -50,6 +50,8 @@ # Enable S0i3 support register "s0ix_enable" = "1" + register "pspp_policy" = "DXIO_PSPP_BALANCED" + device domain 0 on device ref gpp_bridge_0 on end # WLAN device ref gpp_bridge_1 on end # SD -- To view, visit https://review.coreboot.org/c/coreboot/+/54933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I792d909ce75cb73571c9fec58c18f749ea3ae029 Gerrit-Change-Number: 54933 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/amd/majolica: set PSPP policy to balanced
by Felix Held (Code Review) 27 May '21

27 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54932 ) Change subject: mb/amd/majolica: set PSPP policy to balanced ...................................................................... mb/amd/majolica: set PSPP policy to balanced BUG=b:188793754 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I5fd0021170777c755ecb78d339aec05ff786710f Reviewed-on: https://review.coreboot.org/c/coreboot/+/54932 Reviewed-by: Matt Papageorge <matthewpapa07(a)gmail.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/amd/majolica/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Matt Papageorge: Looks good to me, but someone else must approve diff --git a/src/mainboard/amd/majolica/devicetree.cb b/src/mainboard/amd/majolica/devicetree.cb index 0f540a1..8f4fc9b 100644 --- a/src/mainboard/amd/majolica/devicetree.cb +++ b/src/mainboard/amd/majolica/devicetree.cb @@ -15,6 +15,8 @@ register "s0ix_enable" = "true" + register "pspp_policy" = "DXIO_PSPP_BALANCED" + device domain 0 on device ref gpp_gfx_bridge_0 on end # MXM device ref gpp_bridge_0 on end # NVMe -- To view, visit https://review.coreboot.org/c/coreboot/+/54932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5fd0021170777c755ecb78d339aec05ff786710f Gerrit-Change-Number: 54932 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush: set PSPP policy to powersave
by Felix Held (Code Review) 27 May '21

27 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54931 ) Change subject: mb/google/guybrush: set PSPP policy to powersave ...................................................................... mb/google/guybrush: set PSPP policy to powersave BUG=b:188793754 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I262c4c3ae90d8d12fdfe71a3620739070a444a55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54931 Reviewed-by: Matt Papageorge <matthewpapa07(a)gmail.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Raul Rangel: Looks good to me, approved Matt Papageorge: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 3454001..18e7012 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -52,6 +52,8 @@ register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | GPIO_I2C2_SCL | GPIO_I2C3_SCL" + register "pspp_policy" = "DXIO_PSPP_POWERSAVE" + register "usb_phy_custom" = "1" register "usb_phy" = "{ .Usb2PhyPort[0] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/54931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I262c4c3ae90d8d12fdfe71a3620739070a444a55 Gerrit-Change-Number: 54931 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne: add devicetree setting for PSPP policy
by Felix Held (Code Review) 27 May '21

27 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54930 ) Change subject: soc/amd/cezanne: add devicetree setting for PSPP policy ...................................................................... soc/amd/cezanne: add devicetree setting for PSPP policy This allows boards to specify which PSPP policy (basically a dynamic trade-off between power consumption and PCIe link speed) should be used and also makes sure that the boards are using the expected PSPP policy and not just the UPD default from the FSP binary that has already changed once during the development. BUG=b:188793754 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I1b6459b2984711e72b79f5d4d90e04cb4b78d512 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54930 Reviewed-by: Matt Papageorge <matthewpapa07(a)gmail.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/chip.h M src/soc/amd/cezanne/fsp_m_params.c 2 files changed, 10 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Raul Rangel: Looks good to me, approved Matt Papageorge: Looks good to me, but someone else must approve diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index 83aff05..df2059a 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -94,6 +94,13 @@ GPP_CLK_OFF, /* GPP clk off */ } gpp_clk_config[GPP_CLK_OUTPUT_COUNT]; + /* performance policy for the PCIe links: power consumption vs. link speed */ + enum { + DXIO_PSPP_PERFORMANCE = 0, + DXIO_PSPP_BALANCED, + DXIO_PSPP_POWERSAVE, + } pspp_policy; + uint8_t usb_phy_custom; struct usb_phy_config usb_phy; }; diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index 1e6f5ac..352aeef 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -159,6 +159,9 @@ mcfg->telemetry_vddcrsocOffset = config->telemetry_vddcrsocoffset; + /* PCIe power vs. speed */ + mcfg->pspp_policy = config->pspp_policy; + mcfg->enable_nb_azalia = devtree_gfx_hda_dev_enabled(); if (config->usb_phy_custom) -- To view, visit https://review.coreboot.org/c/coreboot/+/54930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b6459b2984711e72b79f5d4d90e04cb4b78d512 Gerrit-Change-Number: 54930 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Documentation: Update real time chat options
by Felix Singer (Code Review) 27 May '21

27 May '21

Attention is currently required from: Stefan Reinauer, Angel Pons, Felix Held. Felix Singer has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/55010 ) Change subject: Documentation: Update real time chat options ...................................................................... Removed Code-Review+2 by Felix Singer <felixsinger(a)posteo.net> -- To view, visit https://review.coreboot.org/c/coreboot/+/55010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3035266c5e035b954c0d709bd2c09069128c3340 Gerrit-Change-Number: 55010 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: deleteVote

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Change in coreboot[master]: cpu/x86/smm: Fix u32 type mismatch in print statement
by Paul Menzel (Code Review) 27 May '21

27 May '21

Attention is currently required from: Rocky Phagura, Angel Pons, Arthur Heymans, Werner Zeh, Felix Held. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54343 ) Change subject: cpu/x86/smm: Fix u32 type mismatch in print statement ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: > yep %zx should be the correct one. […] stefanct suggested that in #coreboot(a)irc.libera.chat. I was mainly led on the wrong path, but the warning saying the result is u32, and wanted to use the corresponding length modifier. From fizzie in ##c: ,cc uint32_t u = 0; size_t s = 0; __typeof__(u - s) combined; ptype(u); ptype(s); ptype(combined); → u = unsigned int s = unsigned long combined = unsigned long ,cc -m32 uint32_t u = 0; size_t s = 0; __typeof__(u - s) combined; ptype(u); ptype(s); ptype(combined); → u = unsigned int s = unsigned int combined = unsigned int -- To view, visit https://review.coreboot.org/c/coreboot/+/54343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib504bc5e5b19f62d4702b7f485522a2ee3d26685 Gerrit-Change-Number: 54343 Gerrit-PatchSet: 6 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Rocky Phagura <rphagura(a)fb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 27 May 2021 15:25:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/stoneyridge: Set missing RTC offsets for day alarm and century
by Raul Rangel (Code Review) 27 May '21

27 May '21

Attention is currently required from: Martin Roth, Anand K Mistry. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55001 ) Change subject: soc/amd/stoneyridge: Set missing RTC offsets for day alarm and century ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Also see https://review.coreboot.org/c/coreboot/+/55012 -- To view, visit https://review.coreboot.org/c/coreboot/+/55001 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10831b982662e680fa71aa81d02935e1b7e7a7a1 Gerrit-Change-Number: 55001 Gerrit-PatchSet: 2 Gerrit-Owner: Anand K Mistry <amistry(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Kurtz <djkurtz(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Anand K Mistry <amistry(a)google.com> Gerrit-Comment-Date: Thu, 27 May 2021 15:16:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: 3rdparty/intel-sec-tools: Update to support Boot Guard
by Christian Walter (Code Review) 27 May '21

27 May '21

Attention is currently required from: Christopher Meis, Arthur Heymans. Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55013 ) Change subject: 3rdparty/intel-sec-tools: Update to support Boot Guard ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf34bdb65a5f067d1d632e35d340b8fc49aaf318 Gerrit-Change-Number: 55013 Gerrit-PatchSet: 5 Gerrit-Owner: Christopher Meis Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christopher Meis Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 27 May 2021 15:16:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: 3rdparty/intel-sec-tools: Update to support Boot Guard
by Christopher Meis (Code Review) 27 May '21

27 May '21

Attention is currently required from: Christian Walter, Arthur Heymans. Christopher Meis has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55013 ) Change subject: 3rdparty/intel-sec-tools: Update to support Boot Guard ...................................................................... Patch Set 5: (1 comment) Patchset: PS4: > Note: This is not ready to merge yet. Had to update the commit again, because the branch in main repo was way behind master branch -- To view, visit https://review.coreboot.org/c/coreboot/+/55013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf34bdb65a5f067d1d632e35d340b8fc49aaf318 Gerrit-Change-Number: 55013 Gerrit-PatchSet: 5 Gerrit-Owner: Christopher Meis Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 27 May 2021 15:13:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Christopher Meis Gerrit-MessageType: comment

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coreboot-gerrit May 2021