coreboot-gerrit May 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/amd/picasso: add devicetree setting for PSPP policy
by Marshall Dawson (Code Review) 27 May '21

27 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Felix Held. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54934 ) Change subject: soc/amd/picasso: add devicetree setting for PSPP policy ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0008ebb0c0f339ed3bdf24ab95a20aa83d5be2c9 Gerrit-Change-Number: 54934 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 27 May 2021 16:37:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: acpi: Add support for reporting CrashLog in BERT table
by Francois Toguo Fotso (Code Review) 27 May '21

27 May '21

Francois Toguo Fotso has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49799 ) Change subject: acpi: Add support for reporting CrashLog in BERT table ...................................................................... Patch Set 10: (1 comment) Patchset: PS10: The Key here is understanding the picture I provided to see how the raw data concept fully fit into a BERT entry. For example an entry can validly have only raw data and no other data. And in that case raw_data_length = data_length. Still raw_data_length will need to be updated. CB:55006 have been pushed already to remove any dependency you will have in linux on changes from the Intel Crashlog flow. Removing the raw data will unblock you, for now. But once again ignoring that variable is not the best approach; because at some point, any other OEMs might decide to use it and we will be back to square 1 again. I do not see the need to move the code you suggested from AMD to the common acpi. Intel already has a similar logic in the file below. It was kept at the SOC level because various OEMs might need the flexibility to check what type of data to put in a BERT; as long as the defined format of the ACPI BERT, previously provided, is followed https://review.coreboot.org/c/coreboot/+/49943/17/src/soc/intel/common/bloc… -- To view, visit https://review.coreboot.org/c/coreboot/+/49799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00e390d735d61beac2e89a726e39119d9b06b3df Gerrit-Change-Number: 49799 Gerrit-PatchSet: 10 Gerrit-Owner: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nikunj Dadhania <nikunj.dadhania(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Comment-Date: Thu, 27 May 2021 16:32:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/smm: Fix u32 type mismatch in print statement
by Felix Held (Code Review) 27 May '21

27 May '21

Attention is currently required from: Paul Menzel, Rocky Phagura, Angel Pons, Arthur Heymans, Werner Zeh. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54343 ) Change subject: cpu/x86/smm: Fix u32 type mismatch in print statement ...................................................................... Patch Set 6: Code-Review+2 (1 comment) Patchset: PS6: > stefanct suggested that in #coreboot(a)irc.libera.chat. […] yeah, the size of size_t is architecture-dependent -- To view, visit https://review.coreboot.org/c/coreboot/+/54343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib504bc5e5b19f62d4702b7f485522a2ee3d26685 Gerrit-Change-Number: 54343 Gerrit-PatchSet: 6 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rocky Phagura <rphagura(a)fb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Thu, 27 May 2021 16:11:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/ocp/deltalake: Add BIOS checksum value to SMBIOS
by Jonathan Zhang (Code Review) 27 May '21

27 May '21

Attention is currently required from: Arthur Heymans, Johnny Lin. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55005 ) Change subject: mb/ocp/deltalake: Add BIOS checksum value to SMBIOS ...................................................................... Patch Set 2: (1 comment) This change is ready for review. Commit Message: https://review.coreboot.org/c/coreboot/+/55005/comment/006f74ea_3980d944 PS2, Line 7: mb/ocp/deltalake: Add BIOS checksum value to SMBIOS Another approach is to do this in build process: a. During build, calculate checksum for of the flash image. Write the checksum to either UPD variable or cbfs. c. During boot time smbios type 1 generation, the value in the cbfs or UPD (if existing) is used to populate the value. But there is a chicken and egg problem. If a utility which checks the checksum, gets checksum of the flash image, it would not match what's reported in smbios type 1. Some research is needed to solve this chicken and egg problem. Another approach is: a. During u-root uinit, calculate the flash image checksum. b. Update smbios type 1. I do not think we update any smbios field at u-root phase at this moment, so some infrastructure work is needed for this approach to work. Since this work may turn out to have to drag the release preparation, I am okay with us deferring this work to CraterLake. -- To view, visit https://review.coreboot.org/c/coreboot/+/55005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22d41c73ffe8377c6014abe77a8921497a41bcb9 Gerrit-Change-Number: 55005 Gerrit-PatchSet: 2 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Comment-Date: Thu, 27 May 2021 15:57:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Mancomb: Add firmware config CBI definitions
by Raul Rangel (Code Review) 27 May '21

27 May '21

Attention is currently required from: Martin Roth. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54732 ) Change subject: Mancomb: Add firmware config CBI definitions ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54732 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56ddc7218688919f20f41e0f143419c39d83849d Gerrit-Change-Number: 54732 Gerrit-PatchSet: 3 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Thu, 27 May 2021 15:54:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/mancomb: Initialize DisplayPort redriver
by Martin Roth (Code Review) 27 May '21

27 May '21

Martin Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/54691 ) Change subject: mb/google/mancomb: Initialize DisplayPort redriver ...................................................................... Abandoned This is going to be initialized in the EC. -- To view, visit https://review.coreboot.org/c/coreboot/+/54691 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icca4f54fa04b69f3126a4c0218137a612062b9b8 Gerrit-Change-Number: 54691 Gerrit-PatchSet: 5 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: drivers/intel/fsp1_1: Drop empty weak functions
by Felix Held (Code Review) 27 May '21

27 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54957 ) Change subject: drivers/intel/fsp1_1: Drop empty weak functions ...................................................................... drivers/intel/fsp1_1: Drop empty weak functions The only FSP 1.1 platform is Braswell. Drop unnecessary functions which only have a weak stub definition. Change-Id: Ie60213e5a6ae67bd8b982ee505f4b512253577c6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54957 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/drivers/intel/fsp1_1/include/fsp/ramstage.h M src/drivers/intel/fsp1_1/include/fsp/romstage.h M src/drivers/intel/fsp1_1/ramstage.c M src/drivers/intel/fsp1_1/romstage.c 4 files changed, 0 insertions(+), 31 deletions(-) Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved diff --git a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h index d1b803e..77698f2 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h @@ -8,8 +8,6 @@ /* Perform Intel silicon init. */ void intel_silicon_init(void); -/* Called after the silicon init code has run. */ -void soc_after_silicon_init(void); /* Initialize UPD data before SiliconInit call. */ void soc_silicon_init_params(SILICON_INIT_UPD *params); void mainboard_silicon_init_params(SILICON_INIT_UPD *params); diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index 99dd9b8..4234ed5 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -29,9 +29,6 @@ MEMORY_INIT_UPD *memory_params); void mainboard_pre_raminit(struct romstage_params *params); void mainboard_save_dimm_info(struct romstage_params *params); -void mainboard_add_dimm_info(struct romstage_params *params, - struct memory_info *mem_info, - int channel, int dimm, int index); void raminit(struct romstage_params *params); /* Initialize memory margin analysis settings. */ void setup_mma(MEMORY_INIT_UPD *memory_upd); @@ -40,7 +37,6 @@ MEMORY_INIT_UPD *new); void soc_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *upd); -void soc_pre_ram_init(struct romstage_params *params); void mainboard_after_memory_init(void); #endif /* _COMMON_ROMSTAGE_H_ */ diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 3ae473b..dcb32c7 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -13,11 +13,6 @@ #include <timestamp.h> #include <cbmem.h> -/* SOC initialization after FSP silicon init */ -__weak void soc_after_silicon_init(void) -{ -} - static void display_hob_info(FSP_INFO_HEADER *fsp_info_header) { const EFI_GUID graphics_info_guid = EFI_PEI_GRAPHICS_INFO_HOB_GUID; @@ -141,7 +136,6 @@ } display_hob_info(fsp_info_header); - soc_after_silicon_init(); } static void fsp_load(void) diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 01d186f..ff03805 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -33,8 +33,6 @@ elog_boot_notify(s3wake); - /* Perform remaining SOC initialization */ - soc_pre_ram_init(params); post_code(0x33); /* Check recovery and MRC cache */ @@ -258,10 +256,6 @@ MEMORY_BUS_WIDTH_128; break; } - - /* Add any mainboard specific information */ - mainboard_add_dimm_info(params, mem_info, - channel, dimm, index); index++; } } @@ -269,16 +263,3 @@ mem_info->dimm_cnt = index; printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); } - -/* Add any mainboard specific information */ -__weak void mainboard_add_dimm_info( - struct romstage_params *params, - struct memory_info *mem_info, - int channel, int dimm, int index) -{ -} - -/* SOC initialization before RAM is enabled */ -__weak void soc_pre_ram_init(struct romstage_params *params) -{ -} -- To view, visit https://review.coreboot.org/c/coreboot/+/54957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie60213e5a6ae67bd8b982ee505f4b512253577c6 Gerrit-Change-Number: 54957 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: lib/hexdump: remove hexdump32 and use hexdump instead
by Felix Held (Code Review) 27 May '21

27 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54925 ) Change subject: lib/hexdump: remove hexdump32 and use hexdump instead ...................................................................... lib/hexdump: remove hexdump32 and use hexdump instead hexdump and hexdump32 do similar things, but hexdump32 is mostly a reimplementation that has additional support to configure the console log level, but has a very unexpected len parameter that isn't in bytes, but in DWORDs. With the move to hexdump() the console log level for the hexdump is changed to BIOS_DEBUG. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I6138d17f0ce8e4a14f22d132bf5c64d0c343b80d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54925 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/include/lib.h M src/lib/hexdump.c M src/northbridge/intel/sandybridge/raminit_mrc.c 3 files changed, 1 insertion(+), 20 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/include/lib.h b/src/include/lib.h index 359626c..8e8bab5 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -29,7 +29,6 @@ * https://packages.debian.org/jessie/amd64/vim-common/filelist */ void hexdump(const void *memory, size_t length); -void hexdump32(char LEVEL, const void *d, size_t len); /* * hexstrtobin - Turn a string of ASCII hex characters into binary diff --git a/src/lib/hexdump.c b/src/lib/hexdump.c index 90446c1..533411f 100644 --- a/src/lib/hexdump.c +++ b/src/lib/hexdump.c @@ -48,21 +48,3 @@ } } } - -void hexdump32(char LEVEL, const void *d, size_t len) -{ - size_t count = 0; - - while (len > 0) { - if (count % 8 == 0) { - printk(LEVEL, "\n"); - printk(LEVEL, "%p:", d); - } - printk(LEVEL, " 0x%08lx", *(unsigned long *)d); - count++; - len--; - d += 4; - } - - printk(LEVEL, "\n\n"); -} diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 21de0b2..43619cd 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -371,7 +371,7 @@ } else { printk(BIOS_ERR, "Could not parse MRC_VAR data\n"); - hexdump32(BIOS_ERR, mrc_var, sizeof(*mrc_var) / sizeof(u32)); + hexdump(mrc_var, sizeof(*mrc_var)); } const int cbmem_was_initted = !cbmem_recovery(s3resume); -- To view, visit https://review.coreboot.org/c/coreboot/+/54925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6138d17f0ce8e4a14f22d132bf5c64d0c343b80d Gerrit-Change-Number: 54925 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/intel/fsp1_1: Drop weak function definition
by Felix Held (Code Review) 27 May '21

27 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54956 ) Change subject: drivers/intel/fsp1_1: Drop weak function definition ...................................................................... drivers/intel/fsp1_1: Drop weak function definition The only FSP 1.1 platform is Braswell, which has a non-weak definition for the `soc_silicon_init_params` function. This changes the resulting BUILD_TIMELESS=1 coreboot image for Facebook fbg1701, for some reason. Change-Id: I2a1b51cda9eb21d7af8372c16a43195a4bdd9543 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54956 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/drivers/intel/fsp1_1/ramstage.c 1 file changed, 0 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 597e886..3ae473b 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -172,8 +172,3 @@ SILICON_INIT_UPD *params) { } - -/* Initialize the UPD parameters for SiliconInit */ -__weak void soc_silicon_init_params(SILICON_INIT_UPD *params) -{ -} -- To view, visit https://review.coreboot.org/c/coreboot/+/54956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a1b51cda9eb21d7af8372c16a43195a4bdd9543 Gerrit-Change-Number: 54956 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/intel/fsp1_1: Drop unused weak definitions
by Felix Held (Code Review) 27 May '21

27 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54955 ) Change subject: drivers/intel/fsp1_1: Drop unused weak definitions ...................................................................... drivers/intel/fsp1_1: Drop unused weak definitions The only FSP 1.1 platform is Braswell. Drop unused weak definitions for functions where a non-weak definition always exists. Tested with BUILD_TIMELESS=1, Facebook fbg1701 remains identical. Change-Id: Ifaf40a1cd661b123911fbeaafeb2b7002559a435 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54955 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/drivers/intel/fsp1_1/raminit.c M src/drivers/intel/fsp1_1/ramstage.c M src/drivers/intel/fsp1_1/romstage.c 3 files changed, 0 insertions(+), 50 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 44e7693..c74955e 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -249,30 +249,6 @@ } } -/* Initialize the UPD parameters for MemoryInit */ -__weak void mainboard_memory_init_params( - struct romstage_params *params, - MEMORY_INIT_UPD *upd_ptr) -{ - printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); -} - -/* Display the UPD parameters for MemoryInit */ -__weak void soc_display_memory_init_params( - const MEMORY_INIT_UPD *old, MEMORY_INIT_UPD *new) -{ - printk(BIOS_SPEW, "UPD values for MemoryInit:\n"); - hexdump32(BIOS_SPEW, new, sizeof(*new)); -} - -/* Initialize the UPD parameters for MemoryInit */ -__weak void soc_memory_init_params( - struct romstage_params *params, - MEMORY_INIT_UPD *upd) -{ - printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); -} - /* Initialize the SoC after MemoryInit */ __weak void mainboard_after_memory_init(void) { diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index b10fccd..597e886 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -171,14 +171,6 @@ __weak void mainboard_silicon_init_params( SILICON_INIT_UPD *params) { -}; - -/* Display the UPD parameters for SiliconInit */ -__weak void soc_display_silicon_init_params( - const SILICON_INIT_UPD *old, SILICON_INIT_UPD *new) -{ - printk(BIOS_SPEW, "UPD values for SiliconInit:\n"); - hexdump32(BIOS_SPEW, new, sizeof(*new)); } /* Initialize the UPD parameters for SiliconInit */ diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 1befc47..01d186f 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -136,12 +136,6 @@ post_code(0x38); } -/* Initialize the power state */ -__weak struct chipset_power_state *fill_power_state(void) -{ - return NULL; -} - /* Board initialization before and after RAM is enabled */ __weak void mainboard_pre_raminit(struct romstage_params *params) { @@ -284,18 +278,6 @@ { } -/* Save the memory configuration data */ -__weak int mrc_cache_stash_data(int type, uint32_t version, - const void *data, size_t size) -{ - return -1; -} - -/* SOC initialization after RAM is enabled */ -__weak void soc_after_ram_init(struct romstage_params *params) -{ -} - /* SOC initialization before RAM is enabled */ __weak void soc_pre_ram_init(struct romstage_params *params) { -- To view, visit https://review.coreboot.org/c/coreboot/+/54955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifaf40a1cd661b123911fbeaafeb2b7002559a435 Gerrit-Change-Number: 54955 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit May 2021