coreboot-gerrit May 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: amdfwtool: Set the region_type as 0 for entry "BIOS level 2"
by Marshall Dawson (Code Review) 27 May '21

27 May '21

Attention is currently required from: Bao Zheng, Raul Rangel, Paul Menzel, Zheng Bao. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54871 ) Change subject: amdfwtool: Set the region_type as 0 for entry "BIOS level 2" ...................................................................... Patch Set 2: -Code-Review (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/54871/comment/e770a758_d4243f44 PS2, Line 9: But we need to set it explicitly as : a known value. > Thanks, though that’s unfortunate. […] Or it's correcting an oversight first introduced in CB:33400, we're doing it for consistency, etc. Also, the spec is NDA so you can cite the number but clarify that an NDA is required. You could also point to https://doc.coreboot.org/soc/amd/psp_integration.html, however. -- To view, visit https://review.coreboot.org/c/coreboot/+/54871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b914f9f02beecce707aba86248826cd9208e6c0 Gerrit-Change-Number: 54871 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Thu, 27 May 2021 17:44:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Bao Zheng <fishbaozi(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Update real time chat options
by Patrick Georgi (Code Review) 27 May '21

27 May '21

Attention is currently required from: Stefan Reinauer, Felix Held. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55010 ) Change subject: Documentation: Update real time chat options ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > Agreed. Discord now has its own commit: CB:55018 -- To view, visit https://review.coreboot.org/c/coreboot/+/55010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3035266c5e035b954c0d709bd2c09069128c3340 Gerrit-Change-Number: 55010 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 27 May 2021 17:42:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: vendorcode/intel/fsp: Update to include post PRQ UPDs for Tiger Lake
by Srinidhi N Kaushik (Code Review) 27 May '21

27 May '21

Attention is currently required from: Ravishankar Sarawadi, Tim Wawrzynczak, Nick Vaccaro, Raj Astekar, Patrick Rudolph. Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54811 ) Change subject: vendorcode/intel/fsp: Update to include post PRQ UPDs for Tiger Lake ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/54811/comment/adbb9e95_593fa713 PS1, Line 7: Update Tiger Lake FSP Headers for FSP v4133 > I believe this is just about opening up more UPDs because it is considered PRQ as you say below now? […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/54811 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I493391294391c1222a1aa5fdb86baad968abf7a6 Gerrit-Change-Number: 54811 Gerrit-PatchSet: 2 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 27 May 2021 17:42:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: acpi: Add support for reporting CrashLog in BERT table
by Francois Toguo Fotso (Code Review) 27 May '21

27 May '21

Francois Toguo Fotso has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49799 ) Change subject: acpi: Add support for reporting CrashLog in BERT table ...................................................................... Patch Set 10: (1 comment) Patchset: PS10: The generic code is currently there already, and working as indented in the common acpi to generate the BERT file/table from either the Intel or AMD. Again I don't see the need to change it. Could you please point to the common code dupplicated by https://review.coreboot.org/c/coreboot/+/49799/10/src/acpi/acpi.c#1585 ? The functions introduced are declared as "__weak". That concept gives it the option for to refined elsewhere. Which actually makes it generic for redefinition/re-use in your ADM flow if you wish. -- To view, visit https://review.coreboot.org/c/coreboot/+/49799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00e390d735d61beac2e89a726e39119d9b06b3df Gerrit-Change-Number: 49799 Gerrit-PatchSet: 10 Gerrit-Owner: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nikunj Dadhania <nikunj.dadhania(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Comment-Date: Thu, 27 May 2021 17:42:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: vendorcode/intel/fsp: Update to include post PRQ UPDs for Tiger Lake
by Srinidhi N Kaushik (Code Review) 27 May '21

27 May '21

Attention is currently required from: Ravishankar Sarawadi, Nick Vaccaro, Srinidhi N Kaushik, Raj Astekar, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Ravishankar Sarawadi, Tim Wawrzynczak, Nick Vaccaro, Raj Astekar, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54811 to look at the new patch set (#2). Change subject: vendorcode/intel/fsp: Update to include post PRQ UPDs for Tiger Lake ...................................................................... vendorcode/intel/fsp: Update to include post PRQ UPDs for Tiger Lake Update FSP headers for Tiger Lake platform generated based on FSP version 4133 to include post PRQ UPDs. BUG=b:188452018 BRANCH=none TEST=build voxel Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I493391294391c1222a1aa5fdb86baad968abf7a6 --- M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h 2 files changed, 2,138 insertions(+), 201 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/54811/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54811 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I493391294391c1222a1aa5fdb86baad968abf7a6 Gerrit-Change-Number: 54811 Gerrit-PatchSet: 2 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Documentation: Fix named link
by Patrick Georgi (Code Review) 27 May '21

27 May '21

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55019 ) Change subject: Documentation: Fix named link ...................................................................... Documentation: Fix named link The syntax requires two bracketed fields. Change-Id: I98ebe714e57f50017755eed7888f0dd2637a3066 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Documentation/mainboard/supermicro/flashing_on_vendorbmc.md 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/55019/1 diff --git a/Documentation/mainboard/supermicro/flashing_on_vendorbmc.md b/Documentation/mainboard/supermicro/flashing_on_vendorbmc.md index c831302..377d900 100644 --- a/Documentation/mainboard/supermicro/flashing_on_vendorbmc.md +++ b/Documentation/mainboard/supermicro/flashing_on_vendorbmc.md @@ -34,7 +34,7 @@ ## Flashing with disabled ME If ME is disabled via `me_cleaner` or the ME recovery jumper, it is still -possible to flash remotely with the [`Supermicro Update Manager`](SUM) (`SUM`). +possible to flash remotely with the [`Supermicro Update Manager`][SUM] (`SUM`). ```sh ./sum -i <remote BMC IP> -u <user> -p <password> -c UpdateBios --reboot \ -- To view, visit https://review.coreboot.org/c/coreboot/+/55019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98ebe714e57f50017755eed7888f0dd2637a3066 Gerrit-Change-Number: 55019 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: Fix up toctree
by Patrick Georgi (Code Review) 27 May '21

27 May '21

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55020 ) Change subject: Documentation: Fix up toctree ...................................................................... Documentation: Fix up toctree Some files weren't properly hooked up, making Sphinx complain. Change-Id: If959fa63d4ddbc3916c49c5ad6602e76b12a7e60 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Documentation/infrastructure/index.md M Documentation/mainboard/index.md M Documentation/technotes/index.md 3 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/55020/1 diff --git a/Documentation/infrastructure/index.md b/Documentation/infrastructure/index.md index 42bcbf6..a452013 100644 --- a/Documentation/infrastructure/index.md +++ b/Documentation/infrastructure/index.md @@ -3,4 +3,4 @@ This section contains documentation about coreboot infrastructure ## Jenkins builders and builds -[Setting up Jenkins build machines](builders.md) +* [Setting up Jenkins build machines](builders.md) diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 3307271..a08cc43 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -153,6 +153,7 @@ ## Purism +- [Librem 14](purism/librem_14.md) - [Librem Mini](purism/librem_mini.md) ## Protectli diff --git a/Documentation/technotes/index.md b/Documentation/technotes/index.md index a9320fb..fda8bd6 100644 --- a/Documentation/technotes/index.md +++ b/Documentation/technotes/index.md @@ -3,4 +3,5 @@ * [Dealing with Untrusted Input in SMM](2017-02-dealing-with-untrusted-input-in-smm.md) * [Rebuilding coreboot image generation](2015-11-rebuilding-coreboot-image-generation.md) * [Unit testing coreboot](2020-03-unit-testing-coreboot.md) +* [Unit Test Code Coverage](2021-05-code-coverage.md) * [Address Sanitizer](asan.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/55020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If959fa63d4ddbc3916c49c5ad6602e76b12a7e60 Gerrit-Change-Number: 55020 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation/community: Add Discord to forums
by Patrick Georgi (Code Review) 27 May '21

27 May '21

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55018 ) Change subject: Documentation/community: Add Discord to forums ...................................................................... Documentation/community: Add Discord to forums Change-Id: Ib1d866ecf041ddc4aaf508d290a3e31b9a108cf2 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Documentation/community/forums.md 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/55018/1 diff --git a/Documentation/community/forums.md b/Documentation/community/forums.md index 92eb6be..c6c913e 100644 --- a/Documentation/community/forums.md +++ b/Documentation/community/forums.md @@ -14,7 +14,8 @@ ## Real time chat We also have a real time chat room on [IRC](ircs://irc.libera.chat/#coreboot), -also bridged to [Matrix](https://matrix.to/#/#coreboot:libera.chat). +also bridged to [Matrix](https://matrix.to/#/#coreboot:libera.chat) and a +[Discord](https://discord.gg/JqT8NM5Zbg) presence. ## Fortnightly coreboot leadership meeting -- To view, visit https://review.coreboot.org/c/coreboot/+/55018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1d866ecf041ddc4aaf508d290a3e31b9a108cf2 Gerrit-Change-Number: 55018 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: Update real time chat options
by Patrick Georgi (Code Review) 27 May '21

27 May '21

Attention is currently required from: Stefan Reinauer, Felix Held. Hello Felix Singer, build bot (Jenkins), Stefan Reinauer, Paul Menzel, Angel Pons, Werner Zeh, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55010 to look at the new patch set (#2). Change subject: Documentation: Update real time chat options ...................................................................... Documentation: Update real time chat options Change-Id: I3035266c5e035b954c0d709bd2c09069128c3340 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Documentation/community/forums.md 1 file changed, 3 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/55010/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3035266c5e035b954c0d709bd2c09069128c3340 Gerrit-Change-Number: 55010 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common/block/rtd3: Add AMD specific RTD3 driver
by Raul Rangel (Code Review) 27 May '21

27 May '21

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Marshall Dawson, Tim Wawrzynczak, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54966 ) Change subject: soc/amd/common/block/rtd3: Add AMD specific RTD3 driver ...................................................................... Patch Set 1: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/54966/comment/9b4bea6d_375c1a53 PS1, Line 9: I decided : to copy and modify it because the Intel driver has a lot of Intel : specific code. > From a quick look, I see that the following things were omitted: […] So I tried refactoring the code into common, but I grew uncomfortable at the number of changes required to isolate the Intel specific parts. 1. Agree that adding this is fine. 2. So this is where I grew uncomfortable. I'm not sure of the sequence required to put a PCIe Root Port into D3. We also don't currently support hot plugging support while the root port is in D0. I'm not sure what it would take to support hot plugging while in D3, or if it's even supported by the hardware. The AMD CRB doesn't implement any of this. 3. So I think the Intel driver conflates the two power resources. * There should be a power resource on the PCIe device that toggles the power/reset GPIOs. This power resource needs _PR3, otherwise the kernel will only put the device into D3Hot. HotPlugSupportInD3 is not required for this PowerResource to be used. We do need StorageD3Enabled for NVMe when ASPM is enabled. This will tell the kernel to power off the device instead of rely on ASPM + NVMe Power States. https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi… * The second power resource is for the PCIe Root Port. This power resource handles the platform specific methods to enable/disable the root port. i.e., PMC communication, L23 entry/exit. It looks like the kernel doesn't even need HotPlugSupportInD3 to power down the port? https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi… Patchset: PS1: First off, sorry for the lack of detail in the commit message. I wanted to push it out before EOD for RFC but ran out of time to elaborate. File src/soc/amd/common/block/rtd3/rtd3.c: https://review.coreboot.org/c/coreboot/+/54966/comment/8c1260f1_0f74fadc PS1, Line 160: "_PR2", "_PR3"} > Duncan had added a comment about not adding _PR3 to this device: https://review.coreboot. […] See comment #11 for a response. https://review.coreboot.org/c/coreboot/+/54966/comment/4d2636fd_687e730f PS1, Line 206: PXSX So I shot a message to the LKML yesterday asking if we could remove this hardcoded constant: https://lore.kernel.org/linux-nvme/YK6gmAWqaRmvpJXb@google.com/T/#m90055222… And I think we can. This resulted in AMD pushing the following patch: https://lore.kernel.org/linux-nvme/20210527135941.7634-1-mario.limonciello@… This means that the StorageD3Enable _DSD should live on the PCI device's ACPI node and we can stop using this hardcoded string. https://review.coreboot.org/c/coreboot/+/54966/comment/a6a8a822_918796bf PS1, Line 210: pci_dev_read_resources > This assumes that the PCI device under the GPP bridge is of type PCI_HEADER_TYPE_NORMAL. […] Ah, are you envisioning a case where we have a bridge connected to the root port? I wasn't a fan of the fake device because it made it difficult to understand. It was confusing why it was writing `acpigen_write_ADR(0);` for the `PXSX`, but then I realized it was the PCI Address of the first device/function on the root port. Thinking more about this now I think I want two drivers: * drivers/pcie/rtd3/device: This is an SoC agnostic driver that deals with adding a power resource onto the PCI device and setting the `StorageD3Enable` property. Essentially what this CL is, just in a different location. This is all that would be needed for AMD right now. If we needed to support a bridge device we can either create a new driver since it's a pretty trivial driver, or we can refactor set_pci_ops so we can get the default pci ops from a device. I'm not sure if an external PCIe Bridge will need a special power resource though, so it might be best to tackle that when we need it. * soc/{amd,intel}/common/block/rtd3/gpp: This driver would contain all the SoC specific code to implement HotPlugSupportInD3, L23, and powering on/off the GPP. This wouldn't be required for AMD in the short term since it's unclear how to even accomplish this. Thoughts? -- To view, visit https://review.coreboot.org/c/coreboot/+/54966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2adfc925183ff7a19ab97e89212bc87c40d552d0 Gerrit-Change-Number: 54966 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 27 May 2021 17:29:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit May 2021