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Change subject: util/sconfig: Add support for discontiguous FW_CONFIG fields
......................................................................
Patch Set 5:
(3 comments)
File Documentation/lib/fw_config.md:
https://review.coreboot.org/c/coreboot/+/52747/comment/deeb53bf_ef32fbe3
PS4, Line 134: 2
> should this be end-bit1? (to be consistent with the first set of start-bit0/end-bit0
Oops
https://review.coreboot.org/c/coreboot/+/52747/comment/a145de34_d4a70e8a
PS4, Line 139:
> this is a tab when the others are spaces. […]
Done
https://review.coreboot.org/c/coreboot/+/52747/comment/bfe81eaf_5012f52c
PS4, Line 141:
> remove this tab to align?
Done
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Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Duncan Laurie,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#5).
Change subject: util/sconfig: Add support for discontiguous FW_CONFIG fields
......................................................................
util/sconfig: Add support for discontiguous FW_CONFIG fields
Sooner or later, some board was going to need extra FW_CONFIG bits for
a field that was already in production, so this patch adds support for
adding extra (unused) bits to a field.
The extra are appended via a syntax like:
`field FIELD_NAME START0 END0 | START1 END1 | START2 END2 ...`
and the suffixed bits are all treated as if they are contiguous when
defining option values.
BUG=b:185190978
TEST=Modified volteer fw_config to the following:
field AUDIO 8 10 | 29 29 | 31 31
option NONE 0
option MAX98357_ALC5682I_I2S 1
option MAX98373_ALC5682I_I2S 2
option MAX98373_ALC5682_SNDW 3
option MAX98373_ALC5682I_I2S_UP4 4
option MAX98360_ALC5682I_I2S 5
option RT1011_ALC5682I_I2S 6
option AUDIO_FOO 7
option AUDIO_BAR 8
option AUDIO_QUUX 9
option AUDIO_BLAH1 10
option AUDIO_BLAH2 15
option AUDIO_BLAH3 16
option AUDIO_BLAH4 31
end
which yielded (in static_fw_config.h):
FW_CONFIG_FIELD_AUDIO_MASK 0xa0000700
FW_CONFIG_FIELD_AUDIO_OPTION_NONE_VALUE 0x0
FW_CONFIG_FIELD_AUDIO_OPTION_MAX98357_ALC5682I_I2S_VALUE 0x100
FW_CONFIG_FIELD_AUDIO_OPTION_MAX98373_ALC5682I_I2S_VALUE 0x200
FW_CONFIG_FIELD_AUDIO_OPTION_MAX98373_ALC5682_SNDW_VALUE 0x300
FW_CONFIG_FIELD_AUDIO_OPTION_MAX98373_ALC5682I_I2S_UP4_VALUE 0x400
FW_CONFIG_FIELD_AUDIO_OPTION_MAX98360_ALC5682I_I2S_VALUE 0x500
FW_CONFIG_FIELD_AUDIO_OPTION_RT1011_ALC5682I_I2S_VALUE 0x600
FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_FOO_VALUE 0x700
FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BAR_VALUE 0x20000000
FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_QUUX_VALUE 0x20000100
FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH1_VALUE 0x20000200
FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH2_VALUE 0x20000700
FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH3_VALUE 0x80000000
FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH4_VALUE 0xa0000700
Change-Id: I5ed76706347ee9642198efc77139abdc3af1b8a6
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M Documentation/lib/fw_config.md
M util/sconfig/lex.yy.c_shipped
M util/sconfig/main.c
M util/sconfig/sconfig.h
M util/sconfig/sconfig.l
M util/sconfig/sconfig.tab.c_shipped
M util/sconfig/sconfig.tab.h_shipped
M util/sconfig/sconfig.y
8 files changed, 537 insertions(+), 361 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/52747/5
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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52801 )
Change subject: mb/google/guybrush: Fix S0i3/S3 GPIO configuration
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/guybrush/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/52801/comment/252a3019_d063bff4
PS1, Line 20: PAD_SCI
I think we might have to use GPIO-controller wake route for the pen eject if we need to apply debounce logic at the pad. Some background from my experiments on Zork: b/159832123#comment16
Quick summary: Debounce logic at the GPIO pad is applied only for the GPIO-controller route and not for the SCI route. For pen detect (I think it really is pen eject from garage), the hardware debouncing on the board has proved to be ineffective on most platforms. And so we have had to apply GPIO controller based debouncing. Thus, to ensure that wake happens only when pen is ejected, we have had to use the GPIO controller route. That should be okay as we do not expose GPE in this case but instead the GPIO IRQ route info: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi…
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Star Labs has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52804 )
Change subject: Added Star Labs labtop series
......................................................................
Added Star Labs labtop series
Change-Id: Ifa79eaffbb7ac83da0124819eec5559af49cc475
---
M src/mainboard/starlabs/labtop/acpi/mainboard.asl
1 file changed, 2 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/52804/1
diff --git a/src/mainboard/starlabs/labtop/acpi/mainboard.asl b/src/mainboard/starlabs/labtop/acpi/mainboard.asl
index bf73244..7b955c4 100644
--- a/src/mainboard/starlabs/labtop/acpi/mainboard.asl
+++ b/src/mainboard/starlabs/labtop/acpi/mainboard.asl
@@ -34,7 +34,7 @@
Name (_CID, Package (0x02)
{
- "PRP00001",
+ "PRP00001",
"PNP0A05"
})
@@ -45,7 +45,7 @@
}
}
-/*
+/*
* ITE IT8987E Embedded Controller
*
* We include this here as we need to support different levels within
@@ -55,5 +55,3 @@
#define EC_GPE_SCI 0x50 /* GPP_E16 */
#include <ec/starlabs/it8987/acpi/ec.asl>
-
-
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Change subject: Added CMOS option to disable ME
......................................................................
Added CMOS option to disable ME
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I374db3b7c0ded71cdc18f27970252fec7220cc20
---
M src/soc/intel/cannonlake/me.c
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/include/intelblocks/cse.h
M src/soc/intel/skylake/me.c
M src/soc/intel/tigerlake/me.c
5 files changed, 45 insertions(+), 1 deletion(-)
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Change subject: Revert "libpayload/keyboard: Reset to scancode set #2 on exit"
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> I just tried it and it made this error go away: […]
I need to test again on a volteer I guess. your EC log output seems to show set1+translate which I don't think is a valid state..
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Change subject: util/sconfig: Add support for discontiguous FW_CONFIG fields
......................................................................
Patch Set 4:
(3 comments)
File Documentation/lib/fw_config.md:
https://review.coreboot.org/c/coreboot/+/52747/comment/2b5d53fe_ef067d8d
PS4, Line 134: 2
should this be end-bit1? (to be consistent with the first set of start-bit0/end-bit0
https://review.coreboot.org/c/coreboot/+/52747/comment/7d3bcffc_f0640f94
PS4, Line 139:
this is a tab when the others are spaces. (it probably all works out in markdown format)
https://review.coreboot.org/c/coreboot/+/52747/comment/3dba0962_77e0a6dc
PS4, Line 141:
remove this tab to align?
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Change subject: Revert "libpayload/keyboard: Reset to scancode set #2 on exit"
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> I'd prefer this as well.
I just tried it and it made this error go away:
[ 3425.046782] atkbd serio0: Use 'setkeycodes e035 <keycode>' to make it known.
[ 3425.127573] atkbd serio0: Unknown key pressed (raw set 2, code 0xb5 on isa0060/serio0).
but I don't get any keys when I do evtest :(
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