coreboot-gerrit April 2021

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Change in coreboot[master]: mb/amd/majolica: add DXIO and DDI descriptors
by Felix Held (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Matt Papageorge. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51956 ) Change subject: mb/amd/majolica: add DXIO and DDI descriptors ...................................................................... Patch Set 10: (1 comment) File src/mainboard/amd/majolica/port_descriptors.c: https://review.coreboot.org/c/coreboot/+/51956/comment/6eb93fb1_c30dc71e PS3, Line 23: device_number = 1, > done, but untested Done -- To view, visit https://review.coreboot.org/c/coreboot/+/51956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65c7e0ebf1e43fd4608d46bae8a176cfc3d0236b Gerrit-Change-Number: 51956 Gerrit-PatchSet: 10 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 22:32:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush/port_descriptors: add dummy descriptors
by Felix Held (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Matt Papageorge, Felix Held. Hello build bot (Jenkins), Raul Rangel, Matt Papageorge, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52141 to look at the new patch set (#3). Change subject: mb/google/guybrush/port_descriptors: add dummy descriptors ...................................................................... mb/google/guybrush/port_descriptors: add dummy descriptors This is a temporary workaround for a bug that breaks graphics due to some power management issue. Signed-off-by: Matt Papageorge <matthewpapa07(a)gmail.com> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie4c8ff8e827901112fd8b2e993898006bc133241 --- M src/mainboard/google/guybrush/port_descriptors.c 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/52141/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/52141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4c8ff8e827901112fd8b2e993898006bc133241 Gerrit-Change-Number: 52141 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush: Add aux PCIe reset GPIOs to dxio descriptors
by Felix Held (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Martin Roth, Felix Held. Felix Held has uploaded a new patch set (#5) to the change originally created by Martin Roth. ( https://review.coreboot.org/c/coreboot/+/52114 ) Change subject: mb/google/guybrush: Add aux PCIe reset GPIOs to dxio descriptors ...................................................................... mb/google/guybrush: Add aux PCIe reset GPIOs to dxio descriptors pcie_rst isn't working correctly, so use the AUX resets to reset the PCIe devices before training. BUG=b:182202136 TEST=See PCIe devices train & enumerate Change-Id: I6db21c79dcbd40c7a8c3f01c60b02882a3851278 Signed-off-by: Martin Roth <martinroth(a)chromium.org> --- M src/mainboard/google/guybrush/port_descriptors.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/52114/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/52114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6db21c79dcbd40c7a8c3f01c60b02882a3851278 Gerrit-Change-Number: 52114 Gerrit-PatchSet: 5 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/amd/majolica: add DXIO and DDI descriptors
by Felix Held (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Matt Papageorge. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Matt Papageorge, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51956 to look at the new patch set (#10). Change subject: mb/amd/majolica: add DXIO and DDI descriptors ...................................................................... mb/amd/majolica: add DXIO and DDI descriptors TEST=Worked on Matt's Majolica board. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Signed-off-by: Matt Papageorge <matthewpapa07(a)gmail.com> Change-Id: I65c7e0ebf1e43fd4608d46bae8a176cfc3d0236b --- M src/mainboard/amd/majolica/port_descriptors.c 1 file changed, 110 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/51956/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/51956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65c7e0ebf1e43fd4608d46bae8a176cfc3d0236b Gerrit-Change-Number: 51956 Gerrit-PatchSet: 10 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/ocp/deltalake: enable SOL console via Kconfig
by Michael Niewöhner (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Marc Jones, Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Angel Pons, Tim Wawrzynczak, Morgan Jang. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52091 ) Change subject: mb/ocp/deltalake: enable SOL console via Kconfig ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Thanks for testing! Will have a look again just to be sure... did you do `make oldconfig` after picking this change and before building? -- To view, visit https://review.coreboot.org/c/coreboot/+/52091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida0632c6d5a3c8a951bf84600e06e394a2bdf022 Gerrit-Change-Number: 52091 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 22:21:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Johnny Lin <Johnny_Lin(a)wiwynn.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] mb/fujitsu/d3410-b1: Add new mainboard
by Angel Pons (Code Review) 07 Apr '21

07 Apr '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48383 ) Change subject: [WIP] mb/fujitsu/d3410-b1: Add new mainboard ...................................................................... [WIP] mb/fujitsu/d3410-b1: Add new mainboard Seems like something on the board isn't happy about coreboot. This code booted once, but the board usually fails to boot... Change-Id: I1fd843cd783b0324866933b95dd46eaccb634ba8 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/fujitsu/Kconfig A src/mainboard/fujitsu/Kconfig.name A src/mainboard/fujitsu/d3410-b1/Kconfig A src/mainboard/fujitsu/d3410-b1/Kconfig.name A src/mainboard/fujitsu/d3410-b1/Makefile.inc A src/mainboard/fujitsu/d3410-b1/acpi/ec.asl A src/mainboard/fujitsu/d3410-b1/acpi/superio.asl A src/mainboard/fujitsu/d3410-b1/board_info.txt A src/mainboard/fujitsu/d3410-b1/bootblock.c A src/mainboard/fujitsu/d3410-b1/devicetree.cb A src/mainboard/fujitsu/d3410-b1/dsdt.asl A src/mainboard/fujitsu/d3410-b1/gma-mainboard.ads A src/mainboard/fujitsu/d3410-b1/gpio.c A src/mainboard/fujitsu/d3410-b1/gpio.h A src/mainboard/fujitsu/d3410-b1/ramstage.c A src/mainboard/fujitsu/d3410-b1/romstage.c 16 files changed, 571 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/48383/1 diff --git a/src/mainboard/fujitsu/Kconfig b/src/mainboard/fujitsu/Kconfig new file mode 100644 index 0000000..fb6d31e --- /dev/null +++ b/src/mainboard/fujitsu/Kconfig @@ -0,0 +1,15 @@ +if VENDOR_FUJITSU + +choice + prompt "Mainboard model" + +source "src/mainboard/fujitsu/*/Kconfig.name" + +endchoice + +source "src/mainboard/fujitsu/*/Kconfig" + +config MAINBOARD_VENDOR + default "Fujitsu" + +endif # VENDOR_FUJITSU diff --git a/src/mainboard/fujitsu/Kconfig.name b/src/mainboard/fujitsu/Kconfig.name new file mode 100644 index 0000000..60d1dd9 --- /dev/null +++ b/src/mainboard/fujitsu/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_FUJITSU + bool "Fujitsu" diff --git a/src/mainboard/fujitsu/d3410-b1/Kconfig b/src/mainboard/fujitsu/d3410-b1/Kconfig new file mode 100644 index 0000000..029c24f --- /dev/null +++ b/src/mainboard/fujitsu/d3410-b1/Kconfig @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if BOARD_FUJITSU_D3410_B1 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select EXCLUDE_NATIVE_SD_INTERFACE + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_LIBGFXINIT + #select NO_FADT_8042 + select SOC_INTEL_KABYLAKE + select SUPERIO_NUVOTON_COMMON_COM_A + select SUPERIO_NUVOTON_NCT6791D + select SKYLAKE_SOC_PCH_H + +config MAINBOARD_DIR + string + default "fujitsu/d3410-b1" + +config MAINBOARD_PART_NUMBER + string + default "D3410-B1" + +config MAX_CPUS + int + default 8 + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +endif diff --git a/src/mainboard/fujitsu/d3410-b1/Kconfig.name b/src/mainboard/fujitsu/d3410-b1/Kconfig.name new file mode 100644 index 0000000..3de8ce8 --- /dev/null +++ b/src/mainboard/fujitsu/d3410-b1/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_FUJITSU_D3410_B1 + bool "D3410-B1" diff --git a/src/mainboard/fujitsu/d3410-b1/Makefile.inc b/src/mainboard/fujitsu/d3410-b1/Makefile.inc new file mode 100644 index 0000000..c75390d --- /dev/null +++ b/src/mainboard/fujitsu/d3410-b1/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c + +ramstage-y += gpio.c +ramstage-y += ramstage.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/fujitsu/d3410-b1/acpi/ec.asl b/src/mainboard/fujitsu/d3410-b1/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/fujitsu/d3410-b1/acpi/ec.asl diff --git a/src/mainboard/fujitsu/d3410-b1/acpi/superio.asl b/src/mainboard/fujitsu/d3410-b1/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/fujitsu/d3410-b1/acpi/superio.asl diff --git a/src/mainboard/fujitsu/d3410-b1/board_info.txt b/src/mainboard/fujitsu/d3410-b1/board_info.txt new file mode 100644 index 0000000..b1c4635 --- /dev/null +++ b/src/mainboard/fujitsu/d3410-b1/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Kontron +Board name: COMe-bSL6 +Category: misc +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/fujitsu/d3410-b1/bootblock.c b/src/mainboard/fujitsu/d3410-b1/bootblock.c new file mode 100644 index 0000000..3224688 --- /dev/null +++ b/src/mainboard/fujitsu/d3410-b1/bootblock.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pnp_ops.h> +#include <bootblock_common.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6791d/nct6791d.h> + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6791D_SP1) + +void bootblock_mainboard_early_init(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin mux states */ + pnp_write_config(GLOBAL_DEV, 0x1a, 0x31); + pnp_write_config(GLOBAL_DEV, 0x1b, 0x61); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x71); + pnp_write_config(GLOBAL_DEV, 0x24, 0x20); + pnp_write_config(GLOBAL_DEV, 0x27, 0x01); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x40); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2f, 0x00); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Enable UART */ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/fujitsu/d3410-b1/devicetree.cb b/src/mainboard/fujitsu/d3410-b1/devicetree.cb new file mode 100644 index 0000000..fbf40d2 --- /dev/null +++ b/src/mainboard/fujitsu/d3410-b1/devicetree.cb @@ -0,0 +1,128 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/skylake + + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" + register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" + register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" + register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S" + register "PmConfigPciClockRun" = "1" + register "PmConfigPwrCycDur" = "RESET_POWER_CYCLE_4S" + + # Vendor set Psys Pmax to 30W + register "power_limits_config" = "{ + .psys_pmax = 30, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 01.0 on end # PEG + device pci 02.0 on end # Integrated Graphics Device + device pci 08.0 on end # Gaussian Mixture Model + device pci 14.0 on # USB xHCI + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[11]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)" + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # MEI #1 + device pci 16.1 off end # MEI #2 + device pci 16.2 off end # ME IDE-R + device pci 16.3 off end # ME KT Redirection + device pci 16.4 off end # MEI #3 + device pci 17.0 on # SATA + register "SataMode" = "KBLFSP_SATA_MODE_AHCI" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + }" + # SataPortsDevSlp not supported + end + device pci 19.0 off end # UART #2 + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on # PCI Express Port 9 (COMe 0) + register "PcieRpEnable[8]" = "1" + end + device pci 1d.1 on # PCI Express Port 10 (COMe 1) + register "PcieRpEnable[9]" = "1" + end + device pci 1d.2 on # PCI Express Port 11 (COMe 2) + register "PcieRpEnable[10]" = "1" + end + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on # LPC Interface + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + #register "gen1_dec" = "0x000c0291" + + chip superio/common + device pnp 2e.0 on + chip superio/nuvoton/nct6791d + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + end + end + end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 on end # GbE + end +end diff --git a/src/mainboard/fujitsu/d3410-b1/dsdt.asl b/src/mainboard/fujitsu/d3410-b1/dsdt.asl new file mode 100644 index 0000000..b5e5a68 --- /dev/null +++ b/src/mainboard/fujitsu/d3410-b1/dsdt.asl @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <cpu/intel/common/acpi/cpu.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/skylake/acpi/globalnvs.asl> + + Device (\_SB.PCI0) { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/fujitsu/d3410-b1/gma-mainboard.ads b/src/mainboard/fujitsu/d3410-b1/gma-mainboard.ads new file mode 100644 index 0000000..0cf02cd --- /dev/null +++ b/src/mainboard/fujitsu/d3410-b1/gma-mainboard.ads @@ -0,0 +1,21 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/fujitsu/d3410-b1/gpio.c b/src/mainboard/fujitsu/d3410-b1/gpio.c new file mode 100644 index 0000000..8498fc5 --- /dev/null +++ b/src/mainboard/fujitsu/d3410-b1/gpio.c @@ -0,0 +1,245 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpe.h> +#include <soc/gpio.h> +#include "gpio.h" + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_A ------- */ + _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_A16, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_A17, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_A18, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_A19, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_A20, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_A21, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(TX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_A22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | (1 << 1) | 1, 0), + _PAD_CFG_STRUCT(GPP_A23, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + + /* ------- GPIO Group GPP_B ------- */ + _PAD_CFG_STRUCT(GPP_B0, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_B1, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + PAD_NC(GPP_B2, UP_20K), + _PAD_CFG_STRUCT(GPP_B3, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_B4, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_B5, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_B6, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_B7, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_B8, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_B9, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_B10, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_B11, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPP_B15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | (1 << 1) | 1, 0), + _PAD_CFG_STRUCT(GPP_B16, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_B17, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPP_B19, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_B20, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_B21, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_B22, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + _PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_C5, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + _PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_C9, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + //PAD_CFG_GPIO_BIDIRECT(GPP_C11, 0, NONE, PLTRST, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_C12, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_C13, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_C14, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_C15, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_C16, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_C17, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_C18, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_C19, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_C20, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_C21, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_C22, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_C23, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + + /* ------- GPIO Group GPP_D ------- */ + _PAD_CFG_STRUCT(GPP_D0, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_D1, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_D2, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_D3, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + //PAD_CFG_GPIO_BIDIRECT(GPP_D5, 0, NONE, PLTRST, LEVEL, ACPI), + _PAD_CFG_STRUCT(GPP_D6, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_D7, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + PAD_CFG_GPI_TRIG_OWN(GPP_D8, DN_20K, PWROK, LEVEL, ACPI), + _PAD_CFG_STRUCT(GPP_D9, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + PAD_CFG_GPI_TRIG_OWN(GPP_D10, DN_20K, PWROK, LEVEL, ACPI), + _PAD_CFG_STRUCT(GPP_D11, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_D12, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_D13, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_D14, PAD_FUNC(GPIO) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_D15, PAD_FUNC(GPIO) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_D16, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_D17, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_D18, PAD_FUNC(GPIO) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_D19, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_D20, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_D21, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_D22, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_D23, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + + /* ------- GPIO Group GPP_E ------- */ + _PAD_CFG_STRUCT(GPP_E0, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_E1, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_E2, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_E3, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_E4, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_E5, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_E6, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_E7, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* ------- GPIO Group GPP_F ------- */ + _PAD_CFG_STRUCT(GPP_F0, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_F1, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_F2, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_F3, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_F4, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_F6, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_F7, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_F8, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_F9, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_F10, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_F11, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_F12, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_F13, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + PAD_NC(GPP_F14, NONE), + _PAD_CFG_STRUCT(GPP_F15, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_F16, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_F17, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_F18, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | (1 << 1) | 1, 0), + _PAD_CFG_STRUCT(GPP_F19, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_F20, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_F21, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_F22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | (1 << 1) | 1, 0), + _PAD_CFG_STRUCT(GPP_F23, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + + /* ------- GPIO Group GPP_G ------- */ + _PAD_CFG_STRUCT(GPP_G0, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G1, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G2, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G3, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G4, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G5, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G6, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G7, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G8, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G9, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G10, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G11, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G12, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G13, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G14, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + PAD_CFG_GPI_TRIG_OWN(GPP_G15, DN_20K, PWROK, LEVEL, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G16, DN_20K, PWROK, LEVEL, ACPI), + _PAD_CFG_STRUCT(GPP_G17, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G18, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G19, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G20, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G21, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G22, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G23, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + + /* ------- GPIO Group GPP_H ------- */ + _PAD_CFG_STRUCT(GPP_H0, PAD_FUNC(GPIO) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(DN_20K)), + PAD_CFG_GPI_TRIG_OWN(GPP_H1, DN_20K, PWROK, LEVEL, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_H2, DN_20K, PWROK, LEVEL, ACPI), + _PAD_CFG_STRUCT(GPP_H3, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_H4, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_H5, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_H6, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_H7, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_H8, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_H9, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_H10, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + //PAD_CFG_GPIO_BIDIRECT(GPP_H11, 0, NONE, PWROK, LEVEL, ACPI), + _PAD_CFG_STRUCT(GPP_H12, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPP_H13, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_H14, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_H15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | (1 << 1) | 1, 0), + _PAD_CFG_STRUCT(GPP_H16, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_H17, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_H18, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_H19, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | (1 << 1) | 1, 0), + _PAD_CFG_STRUCT(GPP_H20, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_H21, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_H22, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_H23, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + + /* ------- GPIO Community 2 ------- */ + + /* -------- GPIO Group GPD -------- */ + PAD_NC(GPD0, NONE), + PAD_NC(GPD1, NONE), + _PAD_CFG_STRUCT(GPD2, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), + _PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPD4, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPD5, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPD6, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + PAD_NC(GPD7, NONE), + _PAD_CFG_STRUCT(GPD8, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPD9, PAD_FUNC(NF1) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + PAD_CFG_GPO(GPD10, 0, DEEP), + _PAD_CFG_STRUCT(GPD11, PAD_FUNC(NF1) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group GPP_I ------- */ + _PAD_CFG_STRUCT(GPP_I0, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_I1, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_I2, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_I3, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_I4, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_I5, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_I6, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_I7, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_I8, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_I9, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_I10, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), +}; +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/fujitsu/d3410-b1/gpio.h b/src/mainboard/fujitsu/d3410-b1/gpio.h new file mode 100644 index 0000000..c3ab23c --- /dev/null +++ b/src/mainboard/fujitsu/d3410-b1/gpio.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +void mainboard_configure_gpios(void); diff --git a/src/mainboard/fujitsu/d3410-b1/ramstage.c b/src/mainboard/fujitsu/d3410-b1/ramstage.c new file mode 100644 index 0000000..8751e53c --- /dev/null +++ b/src/mainboard/fujitsu/d3410-b1/ramstage.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include "gpio.h" + +static void init_mainboard(void *chip_info) +{ + mainboard_configure_gpios(); +} + +struct chip_operations mainboard_ops = { + .init = init_mainboard, +}; diff --git a/src/mainboard/fujitsu/d3410-b1/romstage.c b/src/mainboard/fujitsu/d3410-b1/romstage.c new file mode 100644 index 0000000..8998c17 --- /dev/null +++ b/src/mainboard/fujitsu/d3410-b1/romstage.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <string.h> +#include <assert.h> +#include <spd_bin.h> +#include <soc/romstage.h> +#include <fsp/soc_binding.h> + +/* Rcomp resistors are located on the CPU package */ +static const u16 rcomp_resistors[3] = { 121, 75, 100 }; + +/* Rcomp targets for DDR4 1DPC */ +static const u16 rcomp_targets[5] = { 50, 26, 20, 20, 26 }; + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *const memory_params = &mupd->FspmConfig; + struct spd_block blk = { + .addr_map = { 0x50, 0x52 }, + }; + + assert(sizeof(memory_params->RcompResistor) == sizeof(rcomp_resistors)); + assert(sizeof(memory_params->RcompTarget) == sizeof(rcomp_targets)); + + memory_params->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; + get_spd_smbus(&blk); + memory_params->MemorySpdPtr00 = (u32)blk.spd_array[0]; + memory_params->MemorySpdPtr10 = (u32)blk.spd_array[1]; + + memcpy(memory_params->RcompResistor, rcomp_resistors, + sizeof(memory_params->RcompResistor)); + memcpy(memory_params->RcompTarget, rcomp_targets, + sizeof(memory_params->RcompTarget)); + + memory_params->DqPinsInterleaved = true; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/48383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fd843cd783b0324866933b95dd46eaccb634ba8 Gerrit-Change-Number: 48383 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 31

Change in coreboot[master]: soc/intel/alderlake: Enable VT-d
by Tim Wawrzynczak (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Meera Ravindranath, Ronak Kanabar, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51849 ) Change subject: soc/intel/alderlake: Enable VT-d ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/51849/comment/78477e88_41b4a36f PS6, Line 198: m_cfg->VtdDisable = 0; : m_cfg->VtdIopEnable = 0x1; : : if (m_cfg->InternalGfx && GFXVT_BASE_ADDRESS == 0) { : m_cfg->VtdIgdEnable = 0; : printk(BIOS_ERR, "ERROR: Requested IGD VT-d, but GFXVT_BASE_ADDRESS is 0\n"); : } : else { : m_cfg->VtdIgdEnable = 0x1; : m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; : } : : if (m_cfg->SaIpuEnable && IPUVT_BASE_ADDRESS == 0) { : m_cfg->VtdIpuEnable = 0x0; : printk(BIOS_ERR, "ERROR: Requested IPU VT-d, but IPUVT_BASE_ADDRESS is 0\n"); : } : else { : m_cfg->VtdIpuEnable = 0x1; : m_cfg->VtdBaseAddress[1] = IPUVT_BASE_ADDRESS; : } Let's try to be consistent when specifying boolean values, e.g. `m_cfg->VtdIgdEnable = 1` is preferred vs. `m_cfg->VtdIgdEnable = 0x1`, but consistency is more important IMO 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/51849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96a9f3df185002a4e58faa910f867ace0b97ec2b Gerrit-Change-Number: 51849 Gerrit-PatchSet: 6 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 07 Apr 2021 21:47:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: src/intel/xeon_sp: add hardware error support
by Rocky Phagura (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Rocky Phagura. Rocky Phagura has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52090 ) Change subject: src/intel/xeon_sp: add hardware error support ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/52090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If76b2af153616182cc053ca878f30fe056e9c8bd Gerrit-Change-Number: 52090 Gerrit-PatchSet: 11 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Rocky Phagura <rphagura(a)fb.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 21:25:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/common: Refactor _PRT generation to support GSI-based tables
by Tim Wawrzynczak (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Angel Pons, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50857 ) Change subject: sb/intel/common: Refactor _PRT generation to support GSI-based tables ...................................................................... Patch Set 20: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/50857/comment/7ebedab9_1e63c807 PS19, Line 10: insteade > instead Done Patchset: PS20: sorry for the bad rebase, y'all! 🙏 File src/southbridge/intel/common/acpi_pirq_gen.h: https://review.coreboot.org/c/coreboot/+/50857/comment/30357c12_3cc86cc5 PS19, Line 33: The type of IRQ : * (GSI or PIRQ) comes from `pirq_map_type`. : * > This seems like it went back to an older patchset? bad rebase https://review.coreboot.org/c/coreboot/+/50857/comment/27653102_fd7e033f PS19, Line 39: pack > path? Done File src/southbridge/intel/common/acpi_pirq_gen.c: https://review.coreboot.org/c/coreboot/+/50857/comment/003cce90_6a0f16b2 PS15, Line 15: /* : * The reason for subtracting PCI_INT_A from the pin given is : * that PCI defines pins as 1-4, and _PRT uses 0-3. : */ > Was this intentionally dropped? Or just a bad rebase? ugh bad rebase File src/southbridge/intel/common/rcba_pirq.c: https://review.coreboot.org/c/coreboot/+/50857/comment/845d3580_7d3a31f4 PS19, Line 74: int_idx > nit: This is used in just one place i.e. printk. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/50857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica420a3d12fd1d64c8fe6e4b326fd779b3f10868 Gerrit-Change-Number: 50857 Gerrit-PatchSet: 20 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 07 Apr 2021 21:12:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: sb/intel/common: Refactor _PRT generation to support GSI-based tables
by Tim Wawrzynczak (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Angel Pons, Patrick Rudolph. Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Angel Pons, Nick Vaccaro, Arthur Heymans, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50857 to look at the new patch set (#20). Change subject: sb/intel/common: Refactor _PRT generation to support GSI-based tables ...................................................................... sb/intel/common: Refactor _PRT generation to support GSI-based tables Newer Intel SoCs also support _PRT tables, but they route PCI devices to more than just PIRQs, and statically specify IRQs instead of using link devices. Extend/refactor intel_acpi_gen_def_acpi_pirq to support this additional use case. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ica420a3d12fd1d64c8fe6e4b326fd779b3f10868 --- M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/common/acpi_pirq_gen.c M src/southbridge/intel/common/acpi_pirq_gen.h M src/southbridge/intel/common/rcba_pirq.c M src/southbridge/intel/common/rcba_pirq.h M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 10 files changed, 174 insertions(+), 78 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/50857/20 -- To view, visit https://review.coreboot.org/c/coreboot/+/50857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica420a3d12fd1d64c8fe6e4b326fd779b3f10868 Gerrit-Change-Number: 50857 Gerrit-PatchSet: 20 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit April 2021