coreboot-gerrit April 2021

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Change in coreboot[master]: timestamp: Add helper fucntions
by Julius Werner (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Furquan Shaikh, Angel Pons, Subrata Banik, Aaron Durbin. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51445 ) Change subject: timestamp: Add helper fucntions ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/51445/comment/6d5896cd_ef968479 PS3, Line 7: Add helper fucntions > > ... and for this you need some way to add relative ones. […] Yes, I think timestamp_add_relative() sounds a bit better. -- To view, visit https://review.coreboot.org/c/coreboot/+/51445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b7065ed26e231fc898ae44bcc15cba6fb42b308 Gerrit-Change-Number: 51445 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Wed, 07 Apr 2021 23:16:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: timestamp: Add helper fucntions
by Furquan Shaikh (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Julius Werner, Angel Pons, Subrata Banik, Aaron Durbin. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51445 ) Change subject: timestamp: Add helper fucntions ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/51445/comment/f58c7349_1ae27c62 PS3, Line 7: Add helper fucntions > ... and for this you need some way to add relative ones. Do you think `timestamp_add_relative()` is clearer than `timestamp_add_time_from_base()`? Shorter names are easier to read too, but I was afraid if it seemed too ambiguous. > BTW, am I seeing this right that in this particular case, your rewind_base() would cause ts->base_time to underflow and become a large positive uint64_t? Your observation is absolutely right. I had noticed this when reading the picasso/ code(it already underflows base_time), but like you said, it should still work out and we never really should see values wrapping around, so it isn't a problem. But I agree with you that it looks a little weird and changing to int64_t might be better. We can fix that as part of this effort. -- To view, visit https://review.coreboot.org/c/coreboot/+/51445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b7065ed26e231fc898ae44bcc15cba6fb42b308 Gerrit-Change-Number: 51445 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Wed, 07 Apr 2021 23:08:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: timestamp: Add helper fucntions
by Julius Werner (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Furquan Shaikh, Angel Pons, Subrata Banik, Aaron Durbin. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51445 ) Change subject: timestamp: Add helper fucntions ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/51445/comment/5feb4718_d84d75d9 PS3, Line 7: Add helper fucntions > > I think the time_from_base in your naming is confusing, because all timestamp_add()s are relative […] Sorry, yeah, I confused myself somehow there. You're right that we currently add absolute timestamps and for this you need some way to add relative ones. Switching to microseconds won't change that (although it would remove the need for extra frequency arguments everywhere). (BTW, am I seeing this right that in this particular case, your rewind_base() would cause ts->base_time to underflow and become a large positive uint64_t? I guess fundamentally that should still work out right in the end, but it looks a bit weird. Maybe we should consider changing it to int64_t if we do that?) -- To view, visit https://review.coreboot.org/c/coreboot/+/51445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b7065ed26e231fc898ae44bcc15cba6fb42b308 Gerrit-Change-Number: 51445 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Wed, 07 Apr 2021 22:58:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso/acpi: fix domain argument of acpigen_write_CSD_package
by Felix Held (Code Review) 07 Apr '21

07 Apr '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51932 ) Change subject: soc/amd/picasso/acpi: fix domain argument of acpigen_write_CSD_package ...................................................................... soc/amd/picasso/acpi: fix domain argument of acpigen_write_CSD_package Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I50e88ac946b9d8797571f9e3d4b325db760e423f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51932 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/picasso/acpi.c 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 4ec08e1..7315b92 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -354,7 +354,8 @@ acpigen_write_CST_package(cstate_info, ARRAY_SIZE(cstate_info)); - acpigen_write_CSD_package(cpu >> 1, threads_per_core, CSD_HW_ALL, 0); + acpigen_write_CSD_package(cpu / threads_per_core, threads_per_core, + CSD_HW_ALL, 0); acpigen_pop_len(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/51932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50e88ac946b9d8797571f9e3d4b325db760e423f Gerrit-Change-Number: 51932 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common: Handle power resume after power failure
by Felix Held (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Jason Glenesk, Martin Roth, Marshall Dawson, Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51924 ) Change subject: soc/amd/common: Handle power resume after power failure ...................................................................... Patch Set 6: (1 comment) File src/soc/amd/common/block/pm/Kconfig: https://review.coreboot.org/c/coreboot/+/51924/comment/2da90b30_d2659c74 PS6, Line 10: config POWER_STATE_DEFAULT_ON_AFTER_FAILURE isn't this already defined in the mainboard directory\s kconfig? not sure if this needs to be written here again; i'd assume that just selecting it in the block above should be sufficient -- To view, visit https://review.coreboot.org/c/coreboot/+/51924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea4ea57d747425fe6714d40ba6e60f2447febf28 Gerrit-Change-Number: 51924 Gerrit-PatchSet: 6 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 22:55:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush/port_descriptors: add dummy descriptors
by Felix Held (Code Review) 07 Apr '21

07 Apr '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52141 ) Change subject: mb/google/guybrush/port_descriptors: add dummy descriptors ...................................................................... mb/google/guybrush/port_descriptors: add dummy descriptors This is a temporary workaround for a bug that breaks graphics due to some power management issue. Signed-off-by: Matt Papageorge <matthewpapa07(a)gmail.com> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie4c8ff8e827901112fd8b2e993898006bc133241 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52141 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/guybrush/port_descriptors.c 1 file changed, 22 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c index 3227812..cc1fa1a 100644 --- a/src/mainboard/google/guybrush/port_descriptors.c +++ b/src/mainboard/google/guybrush/port_descriptors.c @@ -53,6 +53,28 @@ .clk_req = CLK_REQ3, .gpio_group_id = GPIO_40, .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + }, + { /* TODO: remove this temporay workaround */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 8, + .end_logical_lane = 11, + .device_number = 2, + .function_number = 5, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ5, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + }, + { /* TODO: remove this temporay workaround */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 16, + .end_logical_lane = 23, + .device_number = 1, + .function_number = 1, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ6, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} } }; -- To view, visit https://review.coreboot.org/c/coreboot/+/52141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4c8ff8e827901112fd8b2e993898006bc133241 Gerrit-Change-Number: 52141 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush: Add aux PCIe reset GPIOs to dxio descriptors
by Felix Held (Code Review) 07 Apr '21

07 Apr '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52114 ) Change subject: mb/google/guybrush: Add aux PCIe reset GPIOs to dxio descriptors ...................................................................... mb/google/guybrush: Add aux PCIe reset GPIOs to dxio descriptors pcie_rst isn't working correctly, so use the AUX resets to reset the PCIe devices before training. BUG=b:182202136 TEST=See PCIe devices train & enumerate Change-Id: I6db21c79dcbd40c7a8c3f01c60b02882a3851278 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52114 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/google/guybrush/port_descriptors.c 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c index b0f4fa9..3227812 100644 --- a/src/mainboard/google/guybrush/port_descriptors.c +++ b/src/mainboard/google/guybrush/port_descriptors.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/platform_descriptors.h> +#include <soc/gpio.h> #include <types.h> /* TODO: test if this really works */ @@ -14,6 +15,7 @@ .function_number = 1, .turn_off_unused_lanes = true, .clk_req = CLK_REQ0, + .gpio_group_id = GPIO_29, .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} }, { /* SD */ @@ -25,6 +27,7 @@ .function_number = 2, .turn_off_unused_lanes = true, .clk_req = CLK_REQ1, + .gpio_group_id = GPIO_70, .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} }, { /* WWAN */ @@ -36,6 +39,7 @@ .function_number = 3, .turn_off_unused_lanes = true, .clk_req = CLK_REQ2, + .gpio_group_id = GPIO_18, .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} }, { /* NVME */ @@ -47,6 +51,7 @@ .function_number = 4, .turn_off_unused_lanes = true, .clk_req = CLK_REQ3, + .gpio_group_id = GPIO_40, .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} } }; -- To view, visit https://review.coreboot.org/c/coreboot/+/52114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6db21c79dcbd40c7a8c3f01c60b02882a3851278 Gerrit-Change-Number: 52114 Gerrit-PatchSet: 6 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/amd/majolica: add DXIO and DDI descriptors
by Felix Held (Code Review) 07 Apr '21

07 Apr '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51956 ) Change subject: mb/amd/majolica: add DXIO and DDI descriptors ...................................................................... mb/amd/majolica: add DXIO and DDI descriptors TEST=Worked on Matt's Majolica board. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Signed-off-by: Matt Papageorge <matthewpapa07(a)gmail.com> Change-Id: I65c7e0ebf1e43fd4608d46bae8a176cfc3d0236b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51956 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/amd/majolica/port_descriptors.c 1 file changed, 110 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/amd/majolica/port_descriptors.c b/src/mainboard/amd/majolica/port_descriptors.c index 913e48b..6aa55b4 100644 --- a/src/mainboard/amd/majolica/port_descriptors.c +++ b/src/mainboard/amd/majolica/port_descriptors.c @@ -4,9 +4,119 @@ #include <types.h> static const fsp_dxio_descriptor majolica_czn_dxio_descriptors[] = { + { /* MXM */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 16, + .end_logical_lane = 23, + .device_number = 1, + .function_number = 1, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ0, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + }, + { /* SSD */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 0, + .end_logical_lane = 1, + .device_number = 2, + .function_number = 1, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ5, + .gpio_group_id = 26, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + }, + { /* DT */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 4, + .end_logical_lane = 4, + .device_number = 2, + .function_number = 2, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ4_GFX, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + }, + { /* WWAN */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 5, + .end_logical_lane = 5, + .device_number = 2, + .function_number = 3, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ2, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + }, + { /* LAN */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 6, + .end_logical_lane = 6, + .device_number = 2, + .function_number = 4, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ1, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + }, + { /* WLAN */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 7, + .end_logical_lane = 7, + .device_number = 2, + .function_number = 5, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ6, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + }, + { /* TB */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 8, + .end_logical_lane = 11, + .device_number = 2, + .function_number = 6, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ3, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + }, + { /* SATA */ + .engine_type = SATA_ENGINE, + .port_present = true, + .start_logical_lane = 2, + .end_logical_lane = 3, + .channel_type = SATA_CHANNEL_LONG, + } }; static const fsp_ddi_descriptor majolica_czn_ddi_descriptors[] = { + { /* DDI0 - DP */ + .connector_type = DDI_DP, + .aux_index = DDI_AUX1, + .hdp_index = DDI_HDP1 + }, + { /* DDI1 - HDMI */ + .connector_type = DDI_HDMI, + .aux_index = DDI_AUX2, + .hdp_index = DDI_HDP2 + }, + { /* DDI2 */ + .connector_type = DDI_UNUSED_TYPE, + .aux_index = DDI_AUX3, + .hdp_index = DDI_HDP3, + }, + { /* DDI3 - DP (type C) */ + .connector_type = DDI_DP, + .aux_index = DDI_AUX3, + .hdp_index = DDI_HDP3, + }, + { /* DDI4 - DP (type C) */ + .connector_type = DDI_DP, + .aux_index = DDI_AUX4, + .hdp_index = DDI_HDP4, + } }; void mainboard_get_dxio_ddi_descriptors( -- To view, visit https://review.coreboot.org/c/coreboot/+/51956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65c7e0ebf1e43fd4608d46bae8a176cfc3d0236b Gerrit-Change-Number: 51956 Gerrit-PatchSet: 11 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/amd/majolica: add PCIe devices to devicetree
by Felix Held (Code Review) 07 Apr '21

07 Apr '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52045 ) Change subject: mb/amd/majolica: add PCIe devices to devicetree ...................................................................... mb/amd/majolica: add PCIe devices to devicetree Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I838aeda2e6c403eaa3388a6b934e7ab6b4e918e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52045 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/mainboard/amd/majolica/devicetree.cb 1 file changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/amd/majolica/devicetree.cb b/src/mainboard/amd/majolica/devicetree.cb index 5efe709..088b259 100644 --- a/src/mainboard/amd/majolica/devicetree.cb +++ b/src/mainboard/amd/majolica/devicetree.cb @@ -15,6 +15,13 @@ }" device domain 0 on + device ref gpp_gfx_bridge_0 on end # MXM + device ref gpp_bridge_0 on end # NVMe + device ref gpp_bridge_1 on end + device ref gpp_bridge_2 on end # WWAN + device ref gpp_bridge_3 on end # LAN + device ref gpp_bridge_4 on end # WLAN + device ref gpp_bridge_5 on end device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) device ref xhci_0 on # USB 3.1 (USB0) -- To view, visit https://review.coreboot.org/c/coreboot/+/52045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I838aeda2e6c403eaa3388a6b934e7ab6b4e918e3 Gerrit-Change-Number: 52045 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush: add DXIO and DDI descriptors
by Felix Held (Code Review) 07 Apr '21

07 Apr '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51957 ) Change subject: mb/google/guybrush: add DXIO and DDI descriptors ...................................................................... mb/google/guybrush: add DXIO and DDI descriptors Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Signed-off-by: Matt Papageorge <matthewpapa07(a)gmail.com> Change-Id: Ic8a4349315f8759c79dc6b087b2a933c307cd573 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51957 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/google/guybrush/port_descriptors.c 1 file changed, 71 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c index d407fe9..b0f4fa9 100644 --- a/src/mainboard/google/guybrush/port_descriptors.c +++ b/src/mainboard/google/guybrush/port_descriptors.c @@ -3,10 +3,81 @@ #include <soc/platform_descriptors.h> #include <types.h> +/* TODO: test if this really works */ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = { + { /* WLAN */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 0, + .end_logical_lane = 0, + .device_number = 2, + .function_number = 1, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ0, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + }, + { /* SD */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 1, + .end_logical_lane = 1, + .device_number = 2, + .function_number = 2, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ1, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + }, + { /* WWAN */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 2, + .end_logical_lane = 2, + .device_number = 2, + .function_number = 3, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ2, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + }, + { /* NVME */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 4, + .end_logical_lane = 7, + .device_number = 2, + .function_number = 4, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ3, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + } }; +/* TODO: verify the DDI table, since this is mostly an educated guess right now */ static const fsp_ddi_descriptor guybrush_czn_ddi_descriptors[] = { + { /* DDI0 - eDP */ + .connector_type = DDI_EDP, + .aux_index = DDI_AUX1, + .hdp_index = DDI_HDP1 + }, + { /* DDI1 - HDMI */ + .connector_type = DDI_HDMI, + .aux_index = DDI_AUX2, + .hdp_index = DDI_HDP2 + }, + { /* DDI2 */ + .connector_type = DDI_UNUSED_TYPE, + .aux_index = DDI_AUX3, + .hdp_index = DDI_HDP3, + }, + { /* DDI3 - DP (type C) */ + .connector_type = DDI_DP, + .aux_index = DDI_AUX3, + .hdp_index = DDI_HDP3, + }, + { /* DDI4 - DP (type C) */ + .connector_type = DDI_DP, + .aux_index = DDI_AUX4, + .hdp_index = DDI_HDP4, + } }; void mainboard_get_dxio_ddi_descriptors( -- To view, visit https://review.coreboot.org/c/coreboot/+/51957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8a4349315f8759c79dc6b087b2a933c307cd573 Gerrit-Change-Number: 51957 Gerrit-PatchSet: 9 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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coreboot-gerrit April 2021