coreboot-gerrit April 2021

coreboot-gerrit@coreboot.org

1 participants
6269 discussions

Change in coreboot[master]: soc/amd/cezanne: Pass DXIO and DDI Descriptors to FSP
by Felix Held (Code Review) 07 Apr '21

07 Apr '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51948 ) Change subject: soc/amd/cezanne: Pass DXIO and DDI Descriptors to FSP ...................................................................... soc/amd/cezanne: Pass DXIO and DDI Descriptors to FSP This patch adds the functionality to write the DXIO and DDI descriptors to the UPD data structure to the SoC code and adds the mainboard_get_dxio_ddi_descriptors function to each mainboard using the Cezanne SoC that gets called to get the descriptors from the board code. Change-Id: I1cb36addcf0202cd56ce99e610a13d6d230bc981 Signed-off-by: Matt Papageorge <matthewpapa07(a)gmail.com> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51948 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/amd/majolica/Makefile.inc A src/mainboard/amd/majolica/port_descriptors.c M src/mainboard/google/guybrush/Makefile.inc A src/mainboard/google/guybrush/port_descriptors.c M src/mainboard/google/mancomb/Makefile.inc A src/mainboard/google/mancomb/port_descriptors.c M src/soc/amd/cezanne/fsp_m_params.c A src/soc/amd/cezanne/include/soc/platform_descriptors.h 8 files changed, 126 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/amd/majolica/Makefile.inc b/src/mainboard/amd/majolica/Makefile.inc index 7c146cf..23e9dd1 100644 --- a/src/mainboard/amd/majolica/Makefile.inc +++ b/src/mainboard/amd/majolica/Makefile.inc @@ -3,6 +3,8 @@ bootblock-y += bootblock.c bootblock-y += early_gpio.c +romstage-y += port_descriptors.c + ramstage-y += chromeos.c APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4.bin diff --git a/src/mainboard/amd/majolica/port_descriptors.c b/src/mainboard/amd/majolica/port_descriptors.c new file mode 100644 index 0000000..913e48b --- /dev/null +++ b/src/mainboard/amd/majolica/port_descriptors.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/platform_descriptors.h> +#include <types.h> + +static const fsp_dxio_descriptor majolica_czn_dxio_descriptors[] = { +}; + +static const fsp_ddi_descriptor majolica_czn_ddi_descriptors[] = { +}; + +void mainboard_get_dxio_ddi_descriptors( + const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, + const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) +{ + *dxio_descs = majolica_czn_dxio_descriptors; + *dxio_num = ARRAY_SIZE(majolica_czn_dxio_descriptors); + *ddi_descs = majolica_czn_ddi_descriptors; + *ddi_num = ARRAY_SIZE(majolica_czn_ddi_descriptors); +} diff --git a/src/mainboard/google/guybrush/Makefile.inc b/src/mainboard/google/guybrush/Makefile.inc index 263483f..d4eeaf5 100644 --- a/src/mainboard/google/guybrush/Makefile.inc +++ b/src/mainboard/google/guybrush/Makefile.inc @@ -10,6 +10,8 @@ $(info APCB sources not found. Skipping APCB.) endif +romstage-y += port_descriptors.c + ramstage-y += mainboard.c ramstage-y += ec.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c new file mode 100644 index 0000000..d407fe9 --- /dev/null +++ b/src/mainboard/google/guybrush/port_descriptors.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/platform_descriptors.h> +#include <types.h> + +static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = { +}; + +static const fsp_ddi_descriptor guybrush_czn_ddi_descriptors[] = { +}; + +void mainboard_get_dxio_ddi_descriptors( + const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, + const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) +{ + *dxio_descs = guybrush_czn_dxio_descriptors; + *dxio_num = ARRAY_SIZE(guybrush_czn_dxio_descriptors); + *ddi_descs = guybrush_czn_ddi_descriptors; + *ddi_num = ARRAY_SIZE(guybrush_czn_ddi_descriptors); +} diff --git a/src/mainboard/google/mancomb/Makefile.inc b/src/mainboard/google/mancomb/Makefile.inc index ccf9055..21e71d7 100644 --- a/src/mainboard/google/mancomb/Makefile.inc +++ b/src/mainboard/google/mancomb/Makefile.inc @@ -4,6 +4,8 @@ verstage-y += verstage.c +romstage-y += port_descriptors.c + ramstage-y += ec.c ramstage-y += mainboard.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/mancomb/port_descriptors.c b/src/mainboard/google/mancomb/port_descriptors.c new file mode 100644 index 0000000..8a761fe --- /dev/null +++ b/src/mainboard/google/mancomb/port_descriptors.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/platform_descriptors.h> +#include <types.h> + +static const fsp_dxio_descriptor mancomb_czn_dxio_descriptors[] = { +}; + +static const fsp_ddi_descriptor mancomb_czn_ddi_descriptors[] = { +}; + +void mainboard_get_dxio_ddi_descriptors( + const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, + const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) +{ + *dxio_descs = mancomb_czn_dxio_descriptors; + *dxio_num = ARRAY_SIZE(mancomb_czn_dxio_descriptors); + *ddi_descs = mancomb_czn_ddi_descriptors; + *ddi_num = ARRAY_SIZE(mancomb_czn_ddi_descriptors); +} diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index 083a82d..f24b601 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -2,8 +2,51 @@ #include <amdblocks/apob_cache.h> #include <amdblocks/memmap.h> +#include <assert.h> #include <console/uart.h> #include <fsp/api.h> +#include <soc/platform_descriptors.h> +#include <string.h> +#include <types.h> + +static void fill_dxio_descriptors(FSP_M_CONFIG *mcfg, + const fsp_dxio_descriptor *descs, size_t num) +{ + size_t i; + + ASSERT_MSG(num <= FSPM_UPD_DXIO_DESCRIPTOR_COUNT, + "Too many DXIO descriptors provided."); + + for (i = 0; i < num; i++) { + memcpy(mcfg->dxio_descriptor[i], &descs[i], sizeof(mcfg->dxio_descriptor[0])); + } +} + +static void fill_ddi_descriptors(FSP_M_CONFIG *mcfg, + const fsp_ddi_descriptor *descs, size_t num) +{ + size_t i; + + ASSERT_MSG(num <= FSPM_UPD_DDI_DESCRIPTOR_COUNT, + "Too many DDI descriptors provided."); + + for (i = 0; i < num; i++) { + memcpy(&mcfg->ddi_descriptor[i], &descs[i], sizeof(mcfg->ddi_descriptor[0])); + } +} + +static void fsp_fill_pcie_ddi_descriptors(FSP_M_CONFIG *mcfg) +{ + const fsp_dxio_descriptor *fsp_dxio; + const fsp_ddi_descriptor *fsp_ddi; + size_t num_dxio; + size_t num_ddi; + + mainboard_get_dxio_ddi_descriptors(&fsp_dxio, &num_dxio, + &fsp_ddi, &num_ddi); + fill_dxio_descriptors(mcfg, fsp_dxio, num_dxio); + fill_ddi_descriptors(mcfg, fsp_ddi, num_ddi); +} void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { @@ -18,4 +61,6 @@ mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM); mcfg->serial_port_baudrate = get_uart_baudrate(); mcfg->serial_port_refclk = uart_platform_refclk(); + + fsp_fill_pcie_ddi_descriptors(mcfg); } diff --git a/src/soc/amd/cezanne/include/soc/platform_descriptors.h b/src/soc/amd/cezanne/include/soc/platform_descriptors.h new file mode 100644 index 0000000..d68cd7f --- /dev/null +++ b/src/soc/amd/cezanne/include/soc/platform_descriptors.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_PICASSO_PLATFORM_DESCRIPTORS_H +#define AMD_PICASSO_PLATFORM_DESCRIPTORS_H + +#include <types.h> +#include <platform_descriptors.h> +#include <FspmUpd.h> + +/* Mainboard callback to obtain DXI/PCIe and DDI descriptors. */ +void mainboard_get_dxio_ddi_descriptors( + const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, + const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num); + +#endif /* AMD_PICASSO_PLATFORM_DESCRIPTORS_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/51948 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cb36addcf0202cd56ce99e610a13d6d230bc981 Gerrit-Change-Number: 51948 Gerrit-PatchSet: 9 Gerrit-Owner: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: vc/amd/fsp/cezanne/FspmUpd: use arrays for DXIO/DDI descriptors
by Felix Held (Code Review) 07 Apr '21

07 Apr '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51955 ) Change subject: vc/amd/fsp/cezanne/FspmUpd: use arrays for DXIO/DDI descriptors ...................................................................... vc/amd/fsp/cezanne/FspmUpd: use arrays for DXIO/DDI descriptors This allows coreboot to easily iterate over the descriptors. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I2ecb3b543f90b8c6a957794f0c55b0ba5c72d59d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51955 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/vendorcode/amd/fsp/cezanne/FspmUpd.h 1 file changed, 5 insertions(+), 19 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h index 0ba9f89..e51cbef 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h +++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h @@ -9,6 +9,9 @@ #include <FspUpd.h> +#define FSPM_UPD_DXIO_DESCRIPTOR_COUNT 14 +#define FSPM_UPD_DDI_DESCRIPTOR_COUNT 5 + /** Fsp M Configuration **/ typedef struct __packed { @@ -21,26 +24,9 @@ /** Offset 0x0074**/ uint32_t serial_port_baudrate; /** Offset 0x0078**/ uint32_t serial_port_refclk; /** Offset 0x007C**/ uint32_t serial_reserved; - /** Offset 0x0080**/ uint8_t dxio_descriptor0[52]; - /** Offset 0x00B4**/ uint8_t dxio_descriptor1[52]; - /** Offset 0x00E8**/ uint8_t dxio_descriptor2[52]; - /** Offset 0x011C**/ uint8_t dxio_descriptor3[52]; - /** Offset 0x0150**/ uint8_t dxio_descriptor4[52]; - /** Offset 0x0184**/ uint8_t dxio_descriptor5[52]; - /** Offset 0x01B8**/ uint8_t dxio_descriptor6[52]; - /** Offset 0x01EC**/ uint8_t dxio_descriptor7[52]; - /** Offset 0x0220**/ uint8_t dxio_descriptor8[52]; - /** Offset 0x0254**/ uint8_t dxio_descriptor9[52]; - /** Offset 0x0288**/ uint8_t dxio_descriptor10[52]; - /** Offset 0x02BC**/ uint8_t dxio_descriptor11[52]; - /** Offset 0x02F0**/ uint8_t dxio_descriptor12[52]; - /** Offset 0x0324**/ uint8_t dxio_descriptor13[52]; + /** Offset 0x0080**/ uint8_t dxio_descriptor[FSPM_UPD_DXIO_DESCRIPTOR_COUNT][52]; /** Offset 0x0358**/ uint8_t pcie_reserved[52]; - /** Offset 0x038C**/ uint32_t ddi_descriptor0; - /** Offset 0x0390**/ uint32_t ddi_descriptor1; - /** Offset 0x0394**/ uint32_t ddi_descriptor2; - /** Offset 0x0398**/ uint32_t ddi_descriptor3; - /** Offset 0x039C**/ uint32_t ddi_descriptor4; + /** Offset 0x038C**/ uint32_t ddi_descriptor[FSPM_UPD_DDI_DESCRIPTOR_COUNT]; /** Offset 0x03A0**/ uint8_t ddi_reserved[6]; /** Offset 0x03A6**/ uint8_t ccx_down_core_mode; /** Offset 0x03A7**/ uint8_t ccx_disable_smt; -- To view, visit https://review.coreboot.org/c/coreboot/+/51955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ecb3b543f90b8c6a957794f0c55b0ba5c72d59d Gerrit-Change-Number: 51955 Gerrit-PatchSet: 8 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: vc/amd/fsp/cezanne: update UPD headers
by Felix Held (Code Review) 07 Apr '21

07 Apr '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51806 ) Change subject: vc/amd/fsp/cezanne: update UPD headers ...................................................................... vc/amd/fsp/cezanne: update UPD headers The UPD header files get generated as part of the FSP build process. For the initial Cezanne development we took the Picasso UPD data structures as a starting point. This patch replaces it with the first version of the Cezanne-specific UPD data structures that is present in version 12 of the internal work-in-progress FSP binary drops. The serial_port_stride UPD-M field is removed, since the information is already given by serial_port_use_mmio. The stride is 4 bytes for the MMIO UART case and 1 byte for the legacy I/O case. BUG=b:182524631 TEST=NVMe works on google/guybrush when the rest of the patch train is applied as well. Change-Id: Idca235029bf2e68d403230d55308820cab61a6c0 Signed-off-by: Matt Papageorge <matthewpapa07(a)gmail.com> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51806 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/cezanne/fsp_m_params.c M src/soc/amd/cezanne/fsp_s_params.c M src/vendorcode/amd/fsp/cezanne/FspmUpd.h M src/vendorcode/amd/fsp/cezanne/FspsUpd.h 4 files changed, 109 insertions(+), 101 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index cb60c89..083a82d 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -16,7 +16,6 @@ mcfg->bert_size = CONFIG_ACPI_BERT_SIZE; mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE); mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM); - mcfg->serial_port_stride = CONFIG(DRIVERS_UART_8250MEM_32) ? 4 : 1; mcfg->serial_port_baudrate = get_uart_baudrate(); mcfg->serial_port_refclk = uart_platform_refclk(); } diff --git a/src/soc/amd/cezanne/fsp_s_params.c b/src/soc/amd/cezanne/fsp_s_params.c index b117afb..ae51f92 100644 --- a/src/soc/amd/cezanne/fsp_s_params.c +++ b/src/soc/amd/cezanne/fsp_s_params.c @@ -5,7 +5,7 @@ static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg) { - scfg->vbios_buffer_addr = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0; + scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0; } void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h index 960d0b4..0ba9f89 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h +++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h @@ -12,61 +12,110 @@ /** Fsp M Configuration **/ typedef struct __packed { - /** Offset 0x0040**/ uint32_t pci_express_base_addr; - /** Offset 0x0044**/ uint32_t serial_port_base; - /** Offset 0x0048**/ uint32_t serial_port_use_mmio; - /** Offset 0x004C**/ uint32_t serial_port_stride; - /** Offset 0x0050**/ uint32_t serial_port_baudrate; - /** Offset 0x0054**/ uint32_t serial_port_refclk; - /** Offset 0x0058**/ uint32_t telemetry_vddcr_vdd_slope_mA; - /** Offset 0x005C**/ uint32_t telemetry_vddcr_vdd_slope2_mA; - /** Offset 0x0060**/ uint32_t telemetry_vddcr_vdd_slope3_mA; - /** Offset 0x0064**/ uint32_t telemetry_vddcr_vdd_slope4_mA; - /** Offset 0x0068**/ uint32_t telemetry_vddcr_vdd_slope5_mA; - /** Offset 0x006C**/ uint32_t telemetry_vddcr_vdd_offset; - /** Offset 0x0070**/ uint32_t telemetry_vddcr_soc_slope_mA; - /** Offset 0x0074**/ uint32_t telemetry_vddcr_soc_offset; - /** Offset 0x0078**/ uint8_t aa_mode_en; - /** Offset 0x0079**/ uint8_t unused2; - /** Offset 0x007A**/ uint8_t unused3; - /** Offset 0x007B**/ uint8_t unused4; - /** Offset 0x007C**/ uint32_t fast_ppt_limit_mW; - /** Offset 0x0080**/ uint32_t slow_ppt_limit_mW; - /** Offset 0x0084**/ uint32_t slow_ppt_time_constant_s; - /** Offset 0x0088**/ uint32_t psi0_current_limit_mA; - /** Offset 0x008C**/ uint32_t psi0_soc_current_limit_mA; - /** Offset 0x0090**/ uint32_t thermctl_limit_degreeC; - /** Offset 0x0094**/ uint32_t vrm_maximum_current_limit_mA; - /** Offset 0x0098**/ uint32_t vrm_soc_maximum_current_limit_mA; - /** Offset 0x009C**/ uint32_t sustained_power_limit_mW; - /** Offset 0x00A0**/ uint32_t stapm_time_constant_s; - /** Offset 0x00A4**/ uint32_t prochot_l_deassertion_ramp_time_ms; - /** Offset 0x00A8**/ uint32_t vrm_current_limit_mA; - /** Offset 0x00AC**/ uint32_t vrm_soc_current_limit_mA; - /** Offset 0x00B0**/ uint32_t vddcr_soc_voltage_margin_mV; - /** Offset 0x00B4**/ uint32_t vddcr_vdd_voltage_margin_mV; - /** Offset 0x00B8**/ uint32_t smu_feature_control_defines; - /** Offset 0x00BC**/ uint32_t smu_feature_control_defines_ext; - /** Offset 0x00C0**/ uint8_t sb_tsi_alert_comparator_mode_en; - /** Offset 0x00C1**/ uint8_t system_config; - /** Offset 0x00C2**/ uint8_t core_dldo_bypass; - /** Offset 0x00C3**/ uint8_t min_soc_vid_offset; - /** Offset 0x00C4**/ uint8_t aclk_dpm0_freq_400MHz; - /** Offset 0x00C5**/ uint8_t unused5; - /** Offset 0x00C6**/ uint8_t unused6; - /** Offset 0x00C7**/ uint8_t sata_enable; - /** Offset 0x00C8**/ uint32_t tseg_size; - /** Offset 0x00CC**/ uint8_t pspp_policy; - /** Offset 0x00CD**/ uint8_t audio_soundwire; - /** Offset 0x00CE**/ uint8_t hd_audio_enable; - /** Offset 0x00CF**/ uint8_t unused9; - /** Offset 0x00D0**/ uint32_t bert_size; - /** Offset 0x00D4**/ uint8_t UnusedUpdSpace0; - /** Offset 0x00D5**/ uint8_t ccx_down_core_mode; - /** Offset 0x00D6**/ uint8_t ccx_disable_smt; - /** Offset 0x00D7**/ uint8_t UnusedUpdSpace1[41]; - /** Offset 0x0100**/ uint16_t Reserved100; - /** Offset 0x0102**/ uint16_t UpdTerminator; + /** Offset 0x0040**/ uint32_t bert_size; + /** Offset 0x0044**/ uint32_t tseg_size; + /** Offset 0x0048**/ uint32_t pci_express_base_addr; + /** Offset 0x004C**/ uint8_t misc_reserved[32]; + /** Offset 0x006C**/ uint32_t serial_port_base; + /** Offset 0x0070**/ uint32_t serial_port_use_mmio; + /** Offset 0x0074**/ uint32_t serial_port_baudrate; + /** Offset 0x0078**/ uint32_t serial_port_refclk; + /** Offset 0x007C**/ uint32_t serial_reserved; + /** Offset 0x0080**/ uint8_t dxio_descriptor0[52]; + /** Offset 0x00B4**/ uint8_t dxio_descriptor1[52]; + /** Offset 0x00E8**/ uint8_t dxio_descriptor2[52]; + /** Offset 0x011C**/ uint8_t dxio_descriptor3[52]; + /** Offset 0x0150**/ uint8_t dxio_descriptor4[52]; + /** Offset 0x0184**/ uint8_t dxio_descriptor5[52]; + /** Offset 0x01B8**/ uint8_t dxio_descriptor6[52]; + /** Offset 0x01EC**/ uint8_t dxio_descriptor7[52]; + /** Offset 0x0220**/ uint8_t dxio_descriptor8[52]; + /** Offset 0x0254**/ uint8_t dxio_descriptor9[52]; + /** Offset 0x0288**/ uint8_t dxio_descriptor10[52]; + /** Offset 0x02BC**/ uint8_t dxio_descriptor11[52]; + /** Offset 0x02F0**/ uint8_t dxio_descriptor12[52]; + /** Offset 0x0324**/ uint8_t dxio_descriptor13[52]; + /** Offset 0x0358**/ uint8_t pcie_reserved[52]; + /** Offset 0x038C**/ uint32_t ddi_descriptor0; + /** Offset 0x0390**/ uint32_t ddi_descriptor1; + /** Offset 0x0394**/ uint32_t ddi_descriptor2; + /** Offset 0x0398**/ uint32_t ddi_descriptor3; + /** Offset 0x039C**/ uint32_t ddi_descriptor4; + /** Offset 0x03A0**/ uint8_t ddi_reserved[6]; + /** Offset 0x03A6**/ uint8_t ccx_down_core_mode; + /** Offset 0x03A7**/ uint8_t ccx_disable_smt; + /** Offset 0x03A8**/ uint8_t ccx_reserved[32]; + /** Offset 0x03C8**/ uint8_t stt_control; + /** Offset 0x03C9**/ uint8_t stt_pcb_sensor_count; + /** Offset 0x03CA**/ uint16_t stt_min_limit; + /** Offset 0x03CC**/ uint16_t stt_m1; + /** Offset 0x03CE**/ uint16_t stt_m2; + /** Offset 0x03D0**/ uint16_t stt_m3; + /** Offset 0x03D2**/ uint16_t stt_m4; + /** Offset 0x03D4**/ uint16_t stt_m5; + /** Offset 0x03D6**/ uint16_t stt_m6; + /** Offset 0x03D8**/ uint16_t stt_c_apu; + /** Offset 0x03DA**/ uint16_t stt_c_gpu; + /** Offset 0x03DC**/ uint16_t stt_c_hs2; + /** Offset 0x03DE**/ uint16_t stt_alpha_apu; + /** Offset 0x03E0**/ uint16_t stt_alpha_gpu; + /** Offset 0x03E2**/ uint16_t stt_alpha_hs2; + /** Offset 0x03E4**/ uint16_t stt_skin_temp_apu; + /** Offset 0x03E6**/ uint16_t stt_skin_temp_gpu; + /** Offset 0x03E8**/ uint16_t stt_skin_temp_hs2; + /** Offset 0x03EA**/ uint16_t stt_error_coeff; + /** Offset 0x03EC**/ uint16_t stt_error_rate_coefficient; + /** Offset 0x03EE**/ uint8_t stapm_control; + /** Offset 0x03EF**/ uint8_t stapm_boost; + /** Offset 0x03F0**/ uint8_t smartshift_enable; + /** Offset 0x03F1**/ uint32_t apu_only_sppt_limit; + /** Offset 0x03F5**/ uint32_t sustained_power_limit; + /** Offset 0x03F9**/ uint32_t fast_ppt_limit; + /** Offset 0x03FD**/ uint32_t slow_ppt_limit; + /** Offset 0x0401**/ uint8_t system_configuration; + /** Offset 0x0402**/ uint8_t cppc_ctrl; + /** Offset 0x0403**/ uint8_t cppc_perf_limit_max_range; + /** Offset 0x0404**/ uint8_t cppc_perf_limit_min_range; + /** Offset 0x0405**/ uint8_t cppc_epp_max_range; + /** Offset 0x0406**/ uint8_t cppc_epp_min_range; + /** Offset 0x0407**/ uint8_t cppc_preferred_cores; + /** Offset 0x0408**/ uint8_t smu_soc_tuning_reserved[20]; + /** Offset 0x041C**/ uint8_t iommu_support; + /** Offset 0x041D**/ uint8_t pspp_policy; + /** Offset 0x041E**/ uint8_t enable_nb_azalia; + /** Offset 0x041F**/ uint8_t audio_io_ctl; + /** Offset 0x0420**/ uint8_t pdm_mic_selection; + /** Offset 0x0421**/ uint8_t nbio_reserved[32]; + /** Offset 0x0441**/ uint32_t emmc0_mode; + /** Offset 0x0445**/ uint16_t emmc0_init_khz_preset; + /** Offset 0x0447**/ uint8_t emmc0_sdr104_hs400_driver_strength; + /** Offset 0x0448**/ uint8_t emmc0_ddr50_driver_strength; + /** Offset 0x0449**/ uint8_t emmc0_sdr50_driver_strength; + /** Offset 0x044A**/ uint8_t fch_usb_version_major; + /** Offset 0x044B**/ uint8_t fch_usb_version_minor; + /** Offset 0x044C**/ uint8_t fch_usb_2_port0_phy_tune[9]; + /** Offset 0x0455**/ uint8_t fch_usb_2_port1_phy_tune[9]; + /** Offset 0x045E**/ uint8_t fch_usb_2_port2_phy_tune[9]; + /** Offset 0x0467**/ uint8_t fch_usb_2_port3_phy_tune[9]; + /** Offset 0x0470**/ uint8_t fch_usb_2_port4_phy_tune[9]; + /** Offset 0x0479**/ uint8_t fch_usb_2_port5_phy_tune[9]; + /** Offset 0x0482**/ uint8_t fch_usb_2_port6_phy_tune[9]; + /** Offset 0x048B**/ uint8_t fch_usb_2_port7_phy_tune[9]; + /** Offset 0x0494**/ uint8_t fch_usb_device_removable; + /** Offset 0x0495**/ uint8_t fch_usb_3_port_force_gen1; + /** Offset 0x0496**/ uint8_t fch_usb_u3_rx_det_wa_enable; + /** Offset 0x0497**/ uint8_t fch_usb_u3_rx_det_wa_portmap; + /** Offset 0x0498**/ uint8_t fch_usb_early_debug_select_enable; + /** Offset 0x0499**/ uint32_t xhci_oc_pin_select; + /** Offset 0x049D**/ uint8_t xhci0_force_gen1; + /** Offset 0x049E**/ uint8_t xhci_sparse_mode_enable; + /** Offset 0x049F**/ uint32_t gnb_ioapic_base; + /** Offset 0x04A3**/ uint8_t gnb_ioapic_id; + /** Offset 0x04A4**/ uint8_t fch_ioapic_id; + /** Offset 0x04A5**/ uint8_t sata_enable; + /** Offset 0x04A6**/ uint8_t fch_reserved[32]; + /** Offset 0x04C6**/ uint8_t UnusedUpdSpace0[58]; + /** Offset 0x0500**/ uint16_t UpdTerminator; } FSP_M_CONFIG; /** Fsp M UPD Configuration diff --git a/src/vendorcode/amd/fsp/cezanne/FspsUpd.h b/src/vendorcode/amd/fsp/cezanne/FspsUpd.h index 7025485..3ac52c0 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspsUpd.h +++ b/src/vendorcode/amd/fsp/cezanne/FspsUpd.h @@ -10,50 +10,10 @@ #include <FspUpd.h> typedef struct __packed { - /** Offset 0x0020**/ uint32_t emmc0_mode; - /** Offset 0x0024**/ uint16_t emmc0_init_khz_preset; - /** Offset 0x0026**/ uint8_t emmc0_sdr104_hs400_driver_strength; - /** Offset 0x0027**/ uint8_t emmc0_ddr50_driver_strength; - /** Offset 0x0028**/ uint8_t emmc0_sdr50_driver_strength; - /** Offset 0x0029**/ uint8_t unused0[7]; - /** Offset 0x0030**/ uint8_t dxio_descriptor0[16]; - /** Offset 0x0040**/ uint8_t dxio_descriptor1[16]; - /** Offset 0x0050**/ uint8_t dxio_descriptor2[16]; - /** Offset 0x0060**/ uint8_t dxio_descriptor3[16]; - /** Offset 0x0070**/ uint8_t dxio_descriptor4[16]; - /** Offset 0x0080**/ uint8_t dxio_descriptor5[16]; - /** Offset 0x0090**/ uint8_t dxio_descriptor6[16]; - /** Offset 0x00A0**/ uint8_t dxio_descriptor7[16]; - /** Offset 0x00B0**/ uint8_t unused1[16]; - /** Offset 0x00C0**/ uint32_t ddi_descriptor0; - /** Offset 0x00C4**/ uint32_t ddi_descriptor1; - /** Offset 0x00C8**/ uint32_t ddi_descriptor2; - /** Offset 0x00CC**/ uint32_t ddi_descriptor3; - /** Offset 0x00D0**/ uint8_t unused2[16]; - /** Offset 0x00E0**/ uint8_t fch_usb_version_major; - /** Offset 0x00E1**/ uint8_t fch_usb_version_minor; - /** Offset 0x00E2**/ uint8_t fch_usb_2_port0_phy_tune[9]; - /** Offset 0x00EB**/ uint8_t fch_usb_2_port1_phy_tune[9]; - /** Offset 0x00F4**/ uint8_t fch_usb_2_port2_phy_tune[9]; - /** Offset 0x00FD**/ uint8_t fch_usb_2_port3_phy_tune[9]; - /** Offset 0x0106**/ uint8_t fch_usb_2_port4_phy_tune[9]; - /** Offset 0x010F**/ uint8_t fch_usb_2_port5_phy_tune[9]; - /** Offset 0x0118**/ uint8_t fch_usb_device_removable; - /** Offset 0x0119**/ uint8_t fch_usb_3_port_force_gen1; - /** Offset 0x011A**/ uint8_t fch_usb_u3_rx_det_wa_enable; - /** Offset 0x011B**/ uint8_t fch_usb_u3_rx_det_wa_portmap; - /** Offset 0x011C**/ uint8_t fch_usb_early_debug_select_enable; - /** Offset 0x011D**/ uint8_t unused3; - /** Offset 0x011E**/ uint32_t xhci_oc_pin_select; - /** Offset 0x0122**/ uint8_t xhci0_force_gen1; - /** Offset 0x0123**/ uint8_t xhci_sparse_mode_enable; - /** Offset 0x0124**/ uint32_t gnb_ioapic_base; - /** Offset 0x0128**/ uint8_t gnb_ioapic_id; - /** Offset 0x0129**/ uint8_t fch_ioapic_id; - /** Offset 0x012A**/ uint8_t UnusedUpdSpace0[6]; - /** Offset 0x0130**/ uint32_t vbios_buffer_addr; - /** Offset 0x0134**/ uint8_t UnusedUpdSpace1[28]; - /** Offset 0x0150**/ uint16_t UpdTerminator; + /** Offset 0x0020**/ uint32_t vbios_buffer; + /** Offset 0x0024**/ uint64_t gop_reserved; + /** Offset 0x002C**/ uint32_t reserved1; + /** Offset 0x0030**/ uint16_t UpdTerminator; } FSP_S_CONFIG; /** Fsp S UPD Configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/51806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idca235029bf2e68d403230d55308820cab61a6c0 Gerrit-Change-Number: 51806 Gerrit-PatchSet: 12 Gerrit-Owner: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: sb/intel/common: Refactor _PRT generation to support GSI-based tables
by Tim Wawrzynczak (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Angel Pons, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50857 ) Change subject: sb/intel/common: Refactor _PRT generation to support GSI-based tables ...................................................................... Patch Set 20: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/50857/comment/76d1f687_2fb06779 PS20, Line 13: > Adding just as a placeholder to ensure this patch is tested before it can be submitted. Good idea, thanks! Angel, Nico, Arthur, Patrick, etc. would be grateful if someone had a chance to test this on one of the existing `SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ` platforms 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/50857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica420a3d12fd1d64c8fe6e4b326fd779b3f10868 Gerrit-Change-Number: 50857 Gerrit-PatchSet: 20 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 07 Apr 2021 22:41:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: sb/intel/common: Refactor _PRT generation to support GSI-based tables
by Furquan Shaikh (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Angel Pons, Patrick Rudolph. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50857 ) Change subject: sb/intel/common: Refactor _PRT generation to support GSI-based tables ...................................................................... Patch Set 20: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/50857/comment/f19d9353_509e6d55 PS20, Line 13: Adding just as a placeholder to ensure this patch is tested before it can be submitted. -- To view, visit https://review.coreboot.org/c/coreboot/+/50857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica420a3d12fd1d64c8fe6e4b326fd779b3f10868 Gerrit-Change-Number: 50857 Gerrit-PatchSet: 20 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 07 Apr 2021 22:38:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: vc/amd/fsp/cezanne: add platform_descriptors.h
by Felix Held (Code Review) 07 Apr '21

07 Apr '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51197 ) Change subject: vc/amd/fsp/cezanne: add platform_descriptors.h ...................................................................... vc/amd/fsp/cezanne: add platform_descriptors.h Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ib16f133b270c99c6e060e5bd0c156cbb03293474 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51197 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- A src/vendorcode/amd/fsp/cezanne/platform_descriptors.h 1 file changed, 218 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/vendorcode/amd/fsp/cezanne/platform_descriptors.h b/src/vendorcode/amd/fsp/cezanne/platform_descriptors.h new file mode 100644 index 0000000..ada9bbd --- /dev/null +++ b/src/vendorcode/amd/fsp/cezanne/platform_descriptors.h @@ -0,0 +1,218 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * These definitions are used to describe PCIe bifurcation and display physical + * connector types connected to the SOC. + */ + +#ifndef PI_CEZANNE_PLATFORM_DESCRIPTORS_H +#define PI_CEZANNE_PLATFORM_DESCRIPTORS_H + +#define NUM_DXIO_PHY_PARAMS 6 +#define NUM_DXIO_PORT_PARAMS 6 + +/* Engine descriptor type */ +enum dxio_engine_type { + UNUSED_ENGINE = 0x00, // Unused descriptor + PCIE_ENGINE = 0x01, // PCIe port + USB_ENGINE = 0x02, // USB port + SATA_ENGINE = 0x03, // SATA + DP_ENGINE = 0x08, // Digital Display + ETHERNET_ENGINE = 0x10, // Ethernet (GBe, XGBe) + MAX_ENGINE // Max engine type for boundary check. +}; + +/* PCIe link capability/speed */ +enum dxio_link_speed_cap { + GEN_MAX = 0, // Maximum supported + GEN1, + GEN2, + GEN3, + GEN_INVALID // Max Gen for boundary check +}; + +/* Upstream Auto Speed Change Allowed */ +enum dxio_upstream_auto_speed_change { + SPDC_DEFAULT = 0, // Enabled for Gen2 and Gen3 + SPDC_DISABLED, + SPDC_ENABLED, + SPDC_INVALID +}; + +/* SATA ChannelType initialization */ +enum dxio_sata_channel_type { + SATA_CHANNEL_OTHER = 0, // Default Channel Type + SATA_CHANNEL_SHORT, // Short Trace Channel Type + SATA_CHANNEL_LONG // Long Trace Channel Type +}; + +/* CLKREQ for PCIe type descriptors */ +enum cpm_clk_req { + CLK_DISABLE = 0x00, + CLK_REQ0, + CLK_REQ1, + CLK_REQ2, + CLK_REQ3, + CLK_REQ4_GFX, + CLK_REQ5, + CLK_REQ6, + CLK_ENABLE = 0xff, +}; + +/* PCIe link ASPM initialization */ +enum dxio_aspm_type { + ASPM_DISABLED = 0, // Disabled + ASPM_L0s, // PCIe L0s link state + ASPM_L1, // PCIe L1 link state + ASPM_L0sL1, // PCIe L0s & L1 link state + ASPM_MAX // Not valid value, used to verify input +}; + +enum dxio_port_param_type { + PP_DEVICE = 1, + PP_FUNCTION, + PP_PORT_PRESENT, + PP_LINK_SPEED_CAP, + PP_LINK_ASPM, + PP_HOTPLUG_TYPE, + PP_CLKREQ, + PP_ASPM_L1_1, + PP_ASPM_L1_2, + PP_COMPLIANCE, + PP_SAFE_MODE, + PP_CHIPSET_LINK, + PP_CLOCK_PM, + PP_CHANNELTYPE, + PP_TURN_OFF_UNUSED_LANES, + PP_APIC_GROUPMAP, + PP_APIC_SWIZZLE, + PP_APIC_BRIDGEINT, + PP_MASTER_PLL, + PP_SLOT_NUM, + PP_PHY_PARAM, + PP_ESM, + PP_CCIX, + PP_GEN3_DS_TX_PRESET, + PP_GEN3_DS_RX_PRESET_HINT, + PP_GEN3_US_TX_PRESET, + PP_GEN3_US_RX_PRESET_HINT, + PP_GEN4_DS_TX_PRESET, + PP_GEN4_US_TX_PRESET, + PP_GEN3_FIXED_PRESET, + PP_GEN4_FIXED_PRESET, + PP_PSPP_DC, + PP_PSPP_AC, + PP_GEN2_DEEMPHASIS, + PP_INVERT_POLARITY, + PP_TARGET_LINK_SPEED, + PP_GEN4_DLF_CAP_DISABLE, + PP_GEN4_DLF_EXCHG_DISABLE +}; + +/* DDI Aux channel */ +enum ddi_aux_type { + DDI_AUX1 = 0, + DDI_AUX2, + DDI_AUX3, + DDI_AUX4, + DDI_AUX5, + DDI_AUX6, + DDI_AUX_MAX // Not valid value, used to verify input +}; + +/* DDI Hdp Index */ +enum ddi_hdp_type { + DDI_HDP1 = 0, + DDI_HDP2, + DDI_HDP3, + DDI_HDP4, + DDI_HDP5, + DDI_HDP6, + DDI_HDP_MAX // Not valid value, used to verify input +}; + +/* DDI display connector type */ +enum ddi_connector_type { + DDI_DP = 0, // DP + DDI_EDP, // eDP + DDI_SINGLE_LINK_DVI, // Single Link DVI-D + DDI_DUAL_LINK_DVI, // Dual Link DVI-D + DDI_HDMI, // HDMI + DDI_DP_TO_VGA, // DP-to-VGA + DDI_DP_TO_LVDS, // DP-to-LVDS + DDI_NUTMEG_DP_TO_VGA, // Hudson-2 NutMeg DP-to-VGA + DDI_SINGLE_LINK_DVI_I, // Single Link DVI-I + DDI_CRT, // CRT (VGA) + DDI_LVDS, // LVDS + DDI_EDP_TO_LVDS, // eDP-to-LVDS translator chip without AMD SW init + DDI_EDP_TO_LVDS_SW, // eDP-to-LVDS translator which requires AMD SW init + DDI_AUTO_DETECT, // VBIOS auto detect connector type + DDI_UNUSED_TYPE, // UnusedType + DDI_MAX_CONNECTOR_TYPE // Not valid value, used to verify input +}; + +/* Cezanne DDI Descriptor: used for configuring display outputs */ +typedef struct __packed { + uint8_t connector_type; // see ddi_connector_type + uint8_t aux_index; // see ddi_aux_type + uint8_t hdp_index; // see ddi_hdp_type + uint8_t reserved; +} fsp_ddi_descriptor; + +/* + * Cezanne DXIO Descriptor: Used for assigning lanes to PCIe/SATA/XGBE engines, + * configure bifurcation and other settings. Beware that the lane numbers in + * here are the logical and not the physical lane numbers! + * + * Cezanne DXIO logical lane to physical PCIe lane mapping: + * + * logical | FT6 | AM4 + * --------|------------|---------------------- + * [00:03] | GPP[00:03] | GPP[00:03] + * [04:07] | GPP[04:07] | GPP[04:07]/HUB[00:03] + * [08:11] | GPP[08:11] | GFX[15:12] + * [12:15] | n/a | GFX[11:08] + * [16:23] | GFX[00:07] | GFX[07:0] + * + * Different ports mustn't overlap or be assigned to the same lane(s). Within + * ports with the same width the one with a higher start logical lane number + * needs to be assigned to a higher PCIe root port number; ports of the same + * size don't have to be assigned to consecutive PCIe root ports though. + * + * Lanes 2 and 3 can be mapped to the SATA controller on all packages; the FT6 + * platform additionally supports mapping lanes 8 and 9 to a SATA controller. + * On embedded SKUs lanes 0 and 1 can be mapped to the Gigabit Ethernet + * controllers. + */ +typedef struct __packed { + uint8_t engine_type; // See dxio_engine_type + uint8_t start_logical_lane; // Start lane of the pci device + uint8_t end_logical_lane; // End lane of the pci device + uint8_t gpio_group_id; // GPIO number used as reset + uint32_t port_present :1; // Should be TRUE if train link + uint32_t reserved_3 :7; + uint32_t device_number :5; // Desired root port device number + uint32_t function_number :3; // Desired root port function number + uint32_t link_speed_capability :2; // See dxio_link_speed_cap + uint32_t auto_spd_change :2; // See dxio_upstream_auto_speed_change + uint32_t eq_preset :4; // Gen3 equalization preset + uint32_t link_aspm :2; // See dxio_aspm_type + uint32_t link_aspm_L1_1 :1; // En/Dis root port capabilities for L1.1 + uint32_t link_aspm_L1_2 :1; // En/Dis root port capabilities for L1.2 + uint32_t clk_req :4; // See cpm_clk_req + uint8_t link_hotplug; // Currently unused by FSP + uint8_t slot_power_limit; // Currently unused by FSP + uint32_t slot_power_limit_scale :2; // Currently unused by FSP + uint32_t reserved_4 :6; + uint32_t link_compliance_mode :1; // Currently unused by FSP + uint32_t link_safe_mode :1; // Currently unused by FSP + uint32_t sb_link :1; // Currently unused by FSP + uint32_t clk_pm_support :1; // Currently unused by FSP + uint32_t channel_type :3; // See dxio_sata_channel_type + uint32_t turn_off_unused_lanes :1; // Power down lanes if device not present + uint8_t reserved[4]; + uint8_t phy_params[NUM_DXIO_PHY_PARAMS*2]; + uint16_t port_params[NUM_DXIO_PORT_PARAMS*2]; // key-value parameters. see dxio_port_param_type +} fsp_dxio_descriptor; + +#endif /* PI_CEZANNE_PLATFORM_DESCRIPTORS_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/51197 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib16f133b270c99c6e060e5bd0c156cbb03293474 Gerrit-Change-Number: 51197 Gerrit-PatchSet: 15 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Justin Frodsham <justin.frodsham(a)protonmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Justin Frodsham <justin.frodsham(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: sb/intel/common: Refactor _PRT generation to support GSI-based tables
by Furquan Shaikh (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Angel Pons, Patrick Rudolph. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50857 ) Change subject: sb/intel/common: Refactor _PRT generation to support GSI-based tables ...................................................................... Patch Set 20: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica420a3d12fd1d64c8fe6e4b326fd779b3f10868 Gerrit-Change-Number: 50857 Gerrit-PatchSet: 20 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 07 Apr 2021 22:38:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/amd/majolica: add DXIO and DDI descriptors
by Raul Rangel (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Matt Papageorge, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51956 ) Change subject: mb/amd/majolica: add DXIO and DDI descriptors ...................................................................... Patch Set 10: Code-Review+2 (1 comment) Patchset: PS10: Majolica still boots. -- To view, visit https://review.coreboot.org/c/coreboot/+/51956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65c7e0ebf1e43fd4608d46bae8a176cfc3d0236b Gerrit-Change-Number: 51956 Gerrit-PatchSet: 10 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 07 Apr 2021 22:35:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/guybrush/port_descriptors: add dummy descriptors
by Raul Rangel (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Marshall Dawson, Matt Papageorge, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52141 ) Change subject: mb/google/guybrush/port_descriptors: add dummy descriptors ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4c8ff8e827901112fd8b2e993898006bc133241 Gerrit-Change-Number: 52141 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 07 Apr 2021 22:34:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/guybrush/port_descriptors: add dummy descriptors
by Felix Held (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Marshall Dawson, Matt Papageorge. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52141 ) Change subject: mb/google/guybrush/port_descriptors: add dummy descriptors ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > Are these UNUSED_ENGINE instead and did we default the FSP's UPD to unused? Sorry, I may be confusi […] the upd defaults are UNUSED_ENGINE (first byte 0x00) -- To view, visit https://review.coreboot.org/c/coreboot/+/52141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4c8ff8e827901112fd8b2e993898006bc133241 Gerrit-Change-Number: 52141 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 22:33:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2021