coreboot-gerrit March 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/guybrush: Add generated LPDDR4x SPDs
by Martin Roth (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Mathew King. Hello build bot (Jenkins), Furquan Shaikh, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51020 to look at the new patch set (#4). Change subject: mb/google/guybrush: Add generated LPDDR4x SPDs ...................................................................... mb/google/guybrush: Add generated LPDDR4x SPDs These SPDs were generated by the lpddr4 version of gen_spd.go from the global_lp4x_mem_parts.json.txt file. BUG=b:178715165 TEST=None Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I7b9bd04534d6e45dbfe10a0028052978ef3d7c17 --- A src/mainboard/google/guybrush/spd/lp4x-spd-1.hex A src/mainboard/google/guybrush/spd/lp4x-spd-2.hex A src/mainboard/google/guybrush/spd/lp4x-spd-3.hex A src/mainboard/google/guybrush/spd/lp4x-spd-4.hex A src/mainboard/google/guybrush/spd/lp4x-spd-5.hex A src/mainboard/google/guybrush/spd/lp4x-spd-6.hex A src/mainboard/google/guybrush/spd/lp4x-spd-7.hex A src/mainboard/google/guybrush/spd/lp4x-spd-8.hex A src/mainboard/google/guybrush/spd/lp4x-spd-9.hex A src/mainboard/google/guybrush/spd/lp4x_spd_manifest.generated.txt 10 files changed, 309 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/51020/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/51020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b9bd04534d6e45dbfe10a0028052978ef3d7c17 Gerrit-Change-Number: 51020 Gerrit-PatchSet: 4 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Mathew King <mathewk(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Mathew King <mathewk(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/spd_tools/lp4x: Add 2 new parts to global memory definition
by Martin Roth (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Furquan Shaikh. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51057 to look at the new patch set (#3). Change subject: util/spd_tools/lp4x: Add 2 new parts to global memory definition ...................................................................... util/spd_tools/lp4x: Add 2 new parts to global memory definition This adds the definitions for MT53E1G32D4NQ-046 WT:E used on Majolica, and the NT6AP256T32AV-J1 part used on Guybrush. BUG=b:178715165 TEST=Generate SPDs Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I7cd729fc72d8f44a449429e97683b2ca1f560f2c --- M util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt 1 file changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/51057/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/51057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cd729fc72d8f44a449429e97683b2ca1f560f2c Gerrit-Change-Number: 51057 Gerrit-PatchSet: 3 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush: Add generated LPDDR4x SPDs
by Martin Roth (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Mathew King. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51020 ) Change subject: mb/google/guybrush: Add generated LPDDR4x SPDs ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/guybrush/spd/guybrush_lp4x_mem_parts.json.txt: PS1: > Great. Thanks very much for the explanation. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/51020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b9bd04534d6e45dbfe10a0028052978ef3d7c17 Gerrit-Change-Number: 51020 Gerrit-PatchSet: 3 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Mathew King <mathewk(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Mathew King <mathewk(a)chromium.org> Gerrit-Comment-Date: Mon, 01 Mar 2021 19:31:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: util/spd_tools/lp4x: Add 2 new parts to global memory definition
by Martin Roth (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Furquan Shaikh. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51057 ) Change subject: util/spd_tools/lp4x: Add 2 new parts to global memory definition ...................................................................... Patch Set 2: (4 comments) File util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt: https://review.coreboot.org/c/coreboot/+/51057/comment/5581af42_7bbc135b PS1, Line 239: 2 > I think this is 1. […] Done https://review.coreboot.org/c/coreboot/+/51057/comment/0bee8bd1_db3e8e3a PS1, Line 242: "speedMbps": 4267 > "casLatencies": "14 20 24 28 32 36" […] Done https://review.coreboot.org/c/coreboot/+/51057/comment/c6ca6b59_af204197 PS1, Line 248: 16 > Isn't this 8? Done https://review.coreboot.org/c/coreboot/+/51057/comment/c372533f_2106e82f PS1, Line 250: 4 > 2? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/51057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cd729fc72d8f44a449429e97683b2ca1f560f2c Gerrit-Change-Number: 51057 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Mon, 01 Mar 2021 19:30:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Add SPDs to build for Guybrush variant
by Martin Roth (Code Review) 01 Mar '21

01 Mar '21

Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51021 to look at the new patch set (#3). Change subject: mb/google/guybrush: Add SPDs to build for Guybrush variant ...................................................................... mb/google/guybrush: Add SPDs to build for Guybrush variant These files were automatically generated by the lpddr4 version of gen_part_id.go. BUG=b:178715165 TEST=Build Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I3797ba6d52248961418000614a4f7885182521a3 --- D src/mainboard/google/guybrush/spd/lp4x-spd-10.hex M src/mainboard/google/guybrush/spd/lp4x-spd-9.hex M src/mainboard/google/guybrush/spd/lp4x_spd_manifest.generated.txt A src/mainboard/google/guybrush/variants/guybrush/Makefile.inc A src/mainboard/google/guybrush/variants/guybrush/memory/Makefile.inc A src/mainboard/google/guybrush/variants/guybrush/memory/dram_id.generated.txt A src/mainboard/google/guybrush/variants/guybrush/memory/mem_list_variant.txt 7 files changed, 20 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/51021/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/51021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3797ba6d52248961418000614a4f7885182521a3 Gerrit-Change-Number: 51021 Gerrit-PatchSet: 3 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Mathew King <mathewk(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/spd_tools/lp4x: Add 2 new parts to global memory definition
by Martin Roth (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Martin Roth. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51057 to look at the new patch set (#2). Change subject: util/spd_tools/lp4x: Add 2 new parts to global memory definition ...................................................................... util/spd_tools/lp4x: Add 2 new parts to global memory definition This adds the definitions for MT53E1G32D4NQ-046 WT:E used on Majolica, and the NT6AP256T32AV-J1 part used on Guybrush. BUG=b:178715165 TEST=Generate SPDs Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I7cd729fc72d8f44a449429e97683b2ca1f560f2c --- M util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt 1 file changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/51057/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cd729fc72d8f44a449429e97683b2ca1f560f2c Gerrit-Change-Number: 51057 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/basecode: Add bootblock common code
by Angel Pons (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Nico Huber, Martin Roth, Furquan Shaikh, Tim Wawrzynczak, Meera Ravindranath, Michael Niewöhner, Usha P, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50955 ) Change subject: soc/intel/common/basecode: Add bootblock common code ...................................................................... Patch Set 3: (4 comments) File src/soc/intel/common/basecode/Kconfig: https://review.coreboot.org/c/coreboot/+/50955/comment/7ae0d048_b6675925 PS2, Line 6: if SOC_INTEL_COMMON_BASECODE > Why? Is there an actual dependency on something only […] Not sure why. I've removed the guard and made SOC_INTEL_COMMON_BASECODE_BOOTBLOCK select SOC_INTEL_COMMON_BASECODE File src/soc/intel/common/basecode/bootblock/bootblock.c: https://review.coreboot.org/c/coreboot/+/50955/comment/2b35022f_6f425f88 PS2, Line 27: void bootblock_soc_init(void) > Moving the entry point to common code makes it harder to pass chip- […] I agree with the reasoning. However, I would need to reorder some code, which could break stuff I can't easily test... File src/soc/intel/common/basecode/bootblock/bootblock.c: https://review.coreboot.org/c/coreboot/+/50955/comment/3e7ff881_fa1ecff3 PS3, Line 16: /* FIXME: Drop function pointer usage */ This is cursed, I know File src/soc/intel/skylake/bootblock/report_platform.c: https://review.coreboot.org/c/coreboot/+/50955/comment/dd628b35_0168cd5a PS2, Line 5: #include <intelblocks/mp_init.h> > odd CPUID macros are in this header. -- To view, visit https://review.coreboot.org/c/coreboot/+/50955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d547347ba595edcc3b6253448c8f5060b4fdfff Gerrit-Change-Number: 50955 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 01 Mar 2021 19:11:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Use common bootblock basecode
by Angel Pons (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50956 ) Change subject: soc/intel/cannonlake: Use common bootblock basecode ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/cannonlake/bootblock/bootblock.c: https://review.coreboot.org/c/coreboot/+/50956/comment/12bfdfe3_4674a81e PS2, Line 64: /* : * Clear the GPI interrupt status and enable registers. These : * registers do not get reset to default state when booting from S5. : */ : gpi_clear_int_cfg(); > How about bootblock_pch_init() for now, and I'll try to follow up later to move it to common code . CB:51148 -- To view, visit https://review.coreboot.org/c/coreboot/+/50956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3dd647b1c4803de4b36fed51d4f03ef86ff4386 Gerrit-Change-Number: 50956 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 01 Mar 2021 19:10:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/basecode: Add bootblock common code
by build bot (Jenkins) (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Martin Roth, Furquan Shaikh, Tim Wawrzynczak, Meera Ravindranath, Michael Niewöhner, Usha P, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50955 ) Change subject: soc/intel/common/basecode: Add bootblock common code ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/common/basecode/bootblock/report_platform.c: https://review.coreboot.org/c/coreboot/+/50955/comment/ce5099f6_4feed0f4 PS3, Line 72: for (size_t i = 0; i < length; i++) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/50955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d547347ba595edcc3b6253448c8f5060b4fdfff Gerrit-Change-Number: 50955 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 01 Mar 2021 19:09:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/basecode: Add bootblock common code
by Angel Pons (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Martin Roth, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Meera Ravindranath, Michael Niewöhner, Usha P, Patrick Rudolph. Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Furquan Shaikh, Tim Wawrzynczak, Meera Ravindranath, Subrata Banik, Usha P, Michael Niewöhner, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50955 to look at the new patch set (#3). Change subject: soc/intel/common/basecode: Add bootblock common code ...................................................................... soc/intel/common/basecode: Add bootblock common code Use Skylake as a starting point. Other platforms will be adapted later. PCH code could be deduplicated more, but it would be necessary to reorder function calls... Change-Id: I0d547347ba595edcc3b6253448c8f5060b4fdfff Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/common/basecode/Kconfig A src/soc/intel/common/basecode/bootblock/Kconfig A src/soc/intel/common/basecode/bootblock/Makefile.inc A src/soc/intel/common/basecode/bootblock/bootblock.c A src/soc/intel/common/basecode/bootblock/report_platform.c A src/soc/intel/common/basecode/include/intelbasecode/bootblock.h M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/Makefile.inc M src/soc/intel/skylake/bootblock/bootblock.c M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/skylake/bootblock/report_platform.c M src/soc/intel/skylake/include/soc/bootblock.h M src/soc/intel/skylake/uart.c 13 files changed, 189 insertions(+), 158 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/50955/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/50955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d547347ba595edcc3b6253448c8f5060b4fdfff Gerrit-Change-Number: 50955 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2021