coreboot-gerrit March 2021

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Change in coreboot[master]: soc/intel/icelake: Rename `pch_init()` function
by Angel Pons (Code Review) 01 Mar '21

01 Mar '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50944 ) Change subject: soc/intel/icelake: Rename `pch_init()` function ...................................................................... soc/intel/icelake: Rename `pch_init()` function There's two instances of the same function, one for the bootblock and another for romstage. Prefix them with the stage they are executed in. Change-Id: I35e87cd47f3cef8952481d25b54558a546aebb60 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50944 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/icelake/bootblock/bootblock.c M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/icelake/include/soc/bootblock.h M src/soc/intel/icelake/include/soc/romstage.h M src/soc/intel/icelake/romstage/pch.c M src/soc/intel/icelake/romstage/romstage.c 6 files changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/icelake/bootblock/bootblock.c b/src/soc/intel/icelake/bootblock/bootblock.c index 54ad85a..9f360da 100644 --- a/src/soc/intel/icelake/bootblock/bootblock.c +++ b/src/soc/intel/icelake/bootblock/bootblock.c @@ -24,5 +24,5 @@ void bootblock_soc_init(void) { report_platform_info(); - pch_init(); + bootblock_pch_init(); } diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index a4166fc..7694a10 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -109,7 +109,7 @@ pch_enable_lpc(); } -void pch_init(void) +void bootblock_pch_init(void) { /* * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, diff --git a/src/soc/intel/icelake/include/soc/bootblock.h b/src/soc/intel/icelake/include/soc/bootblock.h index 0132cfc..f22b266 100644 --- a/src/soc/intel/icelake/include/soc/bootblock.h +++ b/src/soc/intel/icelake/include/soc/bootblock.h @@ -8,7 +8,7 @@ void bootblock_pch_early_init(void); /* Bootblock post console init programming */ -void pch_init(void); +void bootblock_pch_init(void); void pch_early_iorange_init(void); void report_platform_info(void); diff --git a/src/soc/intel/icelake/include/soc/romstage.h b/src/soc/intel/icelake/include/soc/romstage.h index 90a19f2..3772db4 100644 --- a/src/soc/intel/icelake/include/soc/romstage.h +++ b/src/soc/intel/icelake/include/soc/romstage.h @@ -7,7 +7,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); -void pch_init(void); +void romstage_pch_init(void); /* Board type */ enum board_type { diff --git a/src/soc/intel/icelake/romstage/pch.c b/src/soc/intel/icelake/romstage/pch.c index e800ce5..6b134c0 100644 --- a/src/soc/intel/icelake/romstage/pch.c +++ b/src/soc/intel/icelake/romstage/pch.c @@ -4,7 +4,7 @@ #include <intelblocks/tco.h> #include <soc/romstage.h> -void pch_init(void) +void romstage_pch_init(void) { /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ tco_configure(); diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 6af2961..1517974 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -111,7 +111,7 @@ /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); /* Program PCH init */ - pch_init(); + romstage_pch_init(); /* initialize Heci interface */ heci_init(HECI1_BASE_ADDRESS); -- To view, visit https://review.coreboot.org/c/coreboot/+/50944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35e87cd47f3cef8952481d25b54558a546aebb60 Gerrit-Change-Number: 50944 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/skylake: Drop unused function prototypes
by Angel Pons (Code Review) 01 Mar '21

01 Mar '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50943 ) Change subject: soc/intel/skylake: Drop unused function prototypes ...................................................................... soc/intel/skylake: Drop unused function prototypes Change-Id: I1b08b31876d6c10ac155fd67d4a505e8c272a15c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50943 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/skylake/include/soc/bootblock.h M src/soc/intel/skylake/include/soc/romstage.h 2 files changed, 1 insertion(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h index bde941c..6b6af36 100644 --- a/src/soc/intel/skylake/include/soc/bootblock.h +++ b/src/soc/intel/skylake/include/soc/bootblock.h @@ -10,7 +10,6 @@ void bootblock_pch_early_init(void); /* Bootblock post console init programming */ -void i2c_early_init(void); void bootblock_pch_init(void); void pch_early_iorange_init(void); void report_platform_info(void); diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h index fe8bc21..3772db4 100644 --- a/src/soc/intel/skylake/include/soc/romstage.h +++ b/src/soc/intel/skylake/include/soc/romstage.h @@ -8,7 +8,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); void romstage_pch_init(void); -int smbus_read_byte(unsigned int device, unsigned int address); + /* Board type */ enum board_type { BOARD_TYPE_MOBILE = 0, -- To view, visit https://review.coreboot.org/c/coreboot/+/50943 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b08b31876d6c10ac155fd67d4a505e8c272a15c Gerrit-Change-Number: 50943 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel: Factor out common smbus.h
by Angel Pons (Code Review) 01 Mar '21

01 Mar '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50942 ) Change subject: soc/intel: Factor out common smbus.h ...................................................................... soc/intel: Factor out common smbus.h Change-Id: I31bb406bd2cf371ee935aa31777307043b2ee61a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50942 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/include/soc/smbus.h M src/soc/intel/cannonlake/include/soc/smbus.h A src/soc/intel/common/pch/include/intelpch/smbus.h M src/soc/intel/elkhartlake/include/soc/smbus.h M src/soc/intel/icelake/include/soc/smbus.h M src/soc/intel/jasperlake/include/soc/smbus.h M src/soc/intel/skylake/include/soc/smbus.h M src/soc/intel/tigerlake/include/soc/smbus.h 8 files changed, 46 insertions(+), 172 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/alderlake/include/soc/smbus.h b/src/soc/intel/alderlake/include/soc/smbus.h index ab4994a..c865fbe 100644 --- a/src/soc/intel/alderlake/include/soc/smbus.h +++ b/src/soc/intel/alderlake/include/soc/smbus.h @@ -1,35 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* - * This file is created based on Intel Alder Lake Processor PCH Datasheet - * Document number: 621483 - * Chapter number: 6 - */ +#ifndef _SOC_SMBUS_H_ +#define _SOC_SMBUS_H_ -#ifndef _SOC_ALDERLAKE_SMBUS_H_ -#define _SOC_ALDERLAKE_SMBUS_H_ - -/* IO and MMIO registers under primary BAR */ - -/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ -#define TCO1_STS 0x04 -#define TCO_TIMEOUT (1 << 3) -#define TCO2_STS 0x06 -#define TCO_STS_SECOND_TO (1 << 1) -#define TCO_INTRD_DET (1 << 0) -#define TCO1_CNT 0x08 -#define TCO_LOCK (1 << 12) -#define TCO_TMR_HLT (1 << 11) -#define TCO2_CNT 0x0A -#define TCO_INTRD_SEL_MASK (3 << 1) -#define TCO_INTRD_SEL_SMI (1 << 2) -#define TCO_INTRD_SEL_INT (1 << 1) - -/* - * Default slave address value for PCH. This value is set to match default - * value set by hardware. It is useful since PCH is able to respond even - * before CPU is up. This is reset by RSMRST# but not by PLTRST#. - */ -#define SMBUS_SLAVE_ADDR 0x44 +#include <intelpch/smbus.h> #endif diff --git a/src/soc/intel/cannonlake/include/soc/smbus.h b/src/soc/intel/cannonlake/include/soc/smbus.h index c6d20a5..c865fbe 100644 --- a/src/soc/intel/cannonlake/include/soc/smbus.h +++ b/src/soc/intel/cannonlake/include/soc/smbus.h @@ -1,27 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef _SOC_CANNONLAKE_SMBUS_H_ -#define _SOC_CANNONLAKE_SMBUS_H_ +#ifndef _SOC_SMBUS_H_ +#define _SOC_SMBUS_H_ -/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ -#define TCO1_STS 0x04 -#define TCO_TIMEOUT (1 << 3) -#define TCO2_STS 0x06 -#define TCO_STS_SECOND_TO (1 << 1) -#define TCO_INTRD_DET (1 << 0) -#define TCO1_CNT 0x08 -#define TCO_LOCK (1 << 12) -#define TCO_TMR_HLT (1 << 11) -#define TCO2_CNT 0x0A -#define TCO_INTRD_SEL_MASK (3 << 1) -#define TCO_INTRD_SEL_SMI (1 << 2) -#define TCO_INTRD_SEL_INT (1 << 1) - -/* - * Default slave address value for PCH. This value is set to match default - * value set by hardware. It is useful since PCH is able to respond even - * before CPU is up. This is reset by RSMRST# but not by PLTRST#. - */ -#define SMBUS_SLAVE_ADDR 0x44 +#include <intelpch/smbus.h> #endif diff --git a/src/soc/intel/common/pch/include/intelpch/smbus.h b/src/soc/intel/common/pch/include/intelpch/smbus.h new file mode 100644 index 0000000..238da2b --- /dev/null +++ b/src/soc/intel/common/pch/include/intelpch/smbus.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _INTELPCH_SMBUS_H_ +#define _INTELPCH_SMBUS_H_ + +/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ +#define TCO1_STS 0x04 +#define TCO_TIMEOUT (1 << 3) +#define TCO2_STS 0x06 +#define TCO_STS_SECOND_TO (1 << 1) +#define TCO_INTRD_DET (1 << 0) +#define TCO1_CNT 0x08 +#define TCO_LOCK (1 << 12) +#define TCO_TMR_HLT (1 << 11) +#define TCO2_CNT 0x0A +#define TCO_INTRD_SEL_MASK (3 << 1) +#define TCO_INTRD_SEL_SMI (1 << 2) +#define TCO_INTRD_SEL_INT (1 << 1) + +/* + * Default slave address value for PCH. This value is set to match default + * value set by hardware. It is useful since PCH is able to respond even + * before CPU is up. This is reset by RSMRST# but not by PLTRST#. + */ +#define SMBUS_SLAVE_ADDR 0x44 + +#endif diff --git a/src/soc/intel/elkhartlake/include/soc/smbus.h b/src/soc/intel/elkhartlake/include/soc/smbus.h index 0ea469c..c865fbe 100644 --- a/src/soc/intel/elkhartlake/include/soc/smbus.h +++ b/src/soc/intel/elkhartlake/include/soc/smbus.h @@ -1,29 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef _SOC_ELKHARTLAKE_SMBUS_H_ -#define _SOC_ELKHARTLAKE_SMBUS_H_ +#ifndef _SOC_SMBUS_H_ +#define _SOC_SMBUS_H_ -/* IO and MMIO registers under primary BAR */ - -/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ -#define TCO1_STS 0x04 -#define TCO_TIMEOUT (1 << 3) -#define TCO2_STS 0x06 -#define TCO_STS_SECOND_TO (1 << 1) -#define TCO_INTRD_DET (1 << 0) -#define TCO1_CNT 0x08 -#define TCO_LOCK (1 << 12) -#define TCO_TMR_HLT (1 << 11) -#define TCO2_CNT 0x0A -#define TCO_INTRD_SEL_MASK (3 << 1) -#define TCO_INTRD_SEL_SMI (1 << 2) -#define TCO_INTRD_SEL_INT (1 << 1) - -/* - * Default slave address value for PCH. This value is set to match default - * value set by hardware. It is useful since PCH is able to respond even - * before CPU is up. This is reset by RSMRST# but not by PLTRST#. - */ -#define SMBUS_SLAVE_ADDR 0x44 +#include <intelpch/smbus.h> #endif diff --git a/src/soc/intel/icelake/include/soc/smbus.h b/src/soc/intel/icelake/include/soc/smbus.h index c8503d5..c865fbe 100644 --- a/src/soc/intel/icelake/include/soc/smbus.h +++ b/src/soc/intel/icelake/include/soc/smbus.h @@ -1,27 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef _SOC_ICELAKE_SMBUS_H_ -#define _SOC_ICELAKE_SMBUS_H_ +#ifndef _SOC_SMBUS_H_ +#define _SOC_SMBUS_H_ -/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ -#define TCO1_STS 0x04 -#define TCO_TIMEOUT (1 << 3) -#define TCO2_STS 0x06 -#define TCO_STS_SECOND_TO (1 << 1) -#define TCO_INTRD_DET (1 << 0) -#define TCO1_CNT 0x08 -#define TCO_LOCK (1 << 12) -#define TCO_TMR_HLT (1 << 11) -#define TCO2_CNT 0x0A -#define TCO_INTRD_SEL_MASK (3 << 1) -#define TCO_INTRD_SEL_SMI (1 << 2) -#define TCO_INTRD_SEL_INT (1 << 1) - -/* - * Default slave address value for PCH. This value is set to match default - * value set by hardware. It is useful since PCH is able to respond even - * before CPU is up. This is reset by RSMRST# but not by PLTRST#. - */ -#define SMBUS_SLAVE_ADDR 0x44 +#include <intelpch/smbus.h> #endif diff --git a/src/soc/intel/jasperlake/include/soc/smbus.h b/src/soc/intel/jasperlake/include/soc/smbus.h index 7a3a890..c865fbe 100644 --- a/src/soc/intel/jasperlake/include/soc/smbus.h +++ b/src/soc/intel/jasperlake/include/soc/smbus.h @@ -1,29 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef _SOC_JASPERLAKE_SMBUS_H_ -#define _SOC_JASPERLAKE_SMBUS_H_ +#ifndef _SOC_SMBUS_H_ +#define _SOC_SMBUS_H_ -/* IO and MMIO registers under primary BAR */ - -/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ -#define TCO1_STS 0x04 -#define TCO_TIMEOUT (1 << 3) -#define TCO2_STS 0x06 -#define TCO_STS_SECOND_TO (1 << 1) -#define TCO_INTRD_DET (1 << 0) -#define TCO1_CNT 0x08 -#define TCO_LOCK (1 << 12) -#define TCO_TMR_HLT (1 << 11) -#define TCO2_CNT 0x0A -#define TCO_INTRD_SEL_MASK (3 << 1) -#define TCO_INTRD_SEL_SMI (1 << 2) -#define TCO_INTRD_SEL_INT (1 << 1) - -/* - * Default slave address value for PCH. This value is set to match default - * value set by hardware. It is useful since PCH is able to respond even - * before CPU is up. This is reset by RSMRST# but not by PLTRST#. - */ -#define SMBUS_SLAVE_ADDR 0x44 +#include <intelpch/smbus.h> #endif diff --git a/src/soc/intel/skylake/include/soc/smbus.h b/src/soc/intel/skylake/include/soc/smbus.h index bd86aca..c865fbe 100644 --- a/src/soc/intel/skylake/include/soc/smbus.h +++ b/src/soc/intel/skylake/include/soc/smbus.h @@ -3,25 +3,6 @@ #ifndef _SOC_SMBUS_H_ #define _SOC_SMBUS_H_ -/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ -#define TCO1_STS 0x04 -#define TCO_TIMEOUT (1 << 3) -#define TCO2_STS 0x06 -#define TCO_STS_SECOND_TO (1 << 1) -#define TCO_INTRD_DET (1 << 0) -#define TCO1_CNT 0x08 -#define TCO_LOCK (1 << 12) -#define TCO_TMR_HLT (1 << 11) -#define TCO2_CNT 0x0A -#define TCO_INTRD_SEL_MASK (3 << 1) -#define TCO_INTRD_SEL_SMI (1 << 2) -#define TCO_INTRD_SEL_INT (1 << 1) - -/* - * Default slave address value for PCH. This value is set to match default - * value set by hardware. It is useful since PCH is able to respond even - * before CPU is up. This is reset by RSMRST# but not by PLTRST#. - */ -#define SMBUS_SLAVE_ADDR 0x44 +#include <intelpch/smbus.h> #endif diff --git a/src/soc/intel/tigerlake/include/soc/smbus.h b/src/soc/intel/tigerlake/include/soc/smbus.h index 71c4d6a..c865fbe 100644 --- a/src/soc/intel/tigerlake/include/soc/smbus.h +++ b/src/soc/intel/tigerlake/include/soc/smbus.h @@ -1,35 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* - * This file is created based on Intel Tiger Lake Processor PCH Datasheet - * Document number: 575857 - * Chapter number: 6 - */ +#ifndef _SOC_SMBUS_H_ +#define _SOC_SMBUS_H_ -#ifndef _SOC_TIGERLAKE_SMBUS_H_ -#define _SOC_TIGERLAKE_SMBUS_H_ - -/* IO and MMIO registers under primary BAR */ - -/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ -#define TCO1_STS 0x04 -#define TCO_TIMEOUT (1 << 3) -#define TCO2_STS 0x06 -#define TCO_STS_SECOND_TO (1 << 1) -#define TCO_INTRD_DET (1 << 0) -#define TCO1_CNT 0x08 -#define TCO_LOCK (1 << 12) -#define TCO_TMR_HLT (1 << 11) -#define TCO2_CNT 0x0A -#define TCO_INTRD_SEL_MASK (3 << 1) -#define TCO_INTRD_SEL_SMI (1 << 2) -#define TCO_INTRD_SEL_INT (1 << 1) - -/* - * Default slave address value for PCH. This value is set to match default - * value set by hardware. It is useful since PCH is able to respond even - * before CPU is up. This is reset by RSMRST# but not by PLTRST#. - */ -#define SMBUS_SLAVE_ADDR 0x44 +#include <intelpch/smbus.h> #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/50942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31bb406bd2cf371ee935aa31777307043b2ee61a Gerrit-Change-Number: 50942 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/skylake: Correct SMBUS_SLAVE_ADDR definition
by Angel Pons (Code Review) 01 Mar '21

01 Mar '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50941 ) Change subject: soc/intel/skylake: Correct SMBUS_SLAVE_ADDR definition ...................................................................... soc/intel/skylake: Correct SMBUS_SLAVE_ADDR definition According to document 332691-003EN (SPT-H datasheet volume 2), the hardware defaults to 0x44, which matches what newer platforms use. Change-Id: I494587b0074ab3675c3e88676375f667e757cdf0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50941 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/skylake/include/soc/smbus.h 1 file changed, 6 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/skylake/include/soc/smbus.h b/src/soc/intel/skylake/include/soc/smbus.h index 00aae2c..bd86aca 100644 --- a/src/soc/intel/skylake/include/soc/smbus.h +++ b/src/soc/intel/skylake/include/soc/smbus.h @@ -17,7 +17,11 @@ #define TCO_INTRD_SEL_SMI (1 << 2) #define TCO_INTRD_SEL_INT (1 << 1) -/* SMBus I/O bits. */ -#define SMBUS_SLAVE_ADDR 0x24 +/* + * Default slave address value for PCH. This value is set to match default + * value set by hardware. It is useful since PCH is able to respond even + * before CPU is up. This is reset by RSMRST# but not by PLTRST#. + */ +#define SMBUS_SLAVE_ADDR 0x44 #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/50941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I494587b0074ab3675c3e88676375f667e757cdf0 Gerrit-Change-Number: 50941 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel: Factor out common gpe.h
by Angel Pons (Code Review) 01 Mar '21

01 Mar '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50940 ) Change subject: soc/intel: Factor out common gpe.h ...................................................................... soc/intel: Factor out common gpe.h The definitions are identical across seven platforms. Unify them. Change-Id: I32bbd0777f8ca9d0362d210b43e0ba8dd0c8d79b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50940 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/include/soc/gpe.h M src/soc/intel/cannonlake/include/soc/gpe.h A src/soc/intel/common/pch/include/intelpch/gpe.h M src/soc/intel/elkhartlake/include/soc/gpe.h M src/soc/intel/icelake/include/soc/gpe.h M src/soc/intel/jasperlake/include/soc/gpe.h M src/soc/intel/skylake/include/soc/gpe.h M src/soc/intel/tigerlake/include/soc/gpe.h 8 files changed, 129 insertions(+), 799 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/alderlake/include/soc/gpe.h b/src/soc/intel/alderlake/include/soc/gpe.h index 34dfcea..6c08d35 100644 --- a/src/soc/intel/alderlake/include/soc/gpe.h +++ b/src/soc/intel/alderlake/include/soc/gpe.h @@ -3,119 +3,6 @@ #ifndef _SOC_GPE_H_ #define _SOC_GPE_H_ -/* GPE_31_0 */ -#define GPE0_DW0_00 0 -#define GPE0_DW0_01 1 -#define GPE0_DW0_02 2 -#define GPE0_DW0_03 3 -#define GPE0_DW0_04 4 -#define GPE0_DW0_05 5 -#define GPE0_DW0_06 6 -#define GPE0_DW0_07 7 -#define GPE0_DW0_08 8 -#define GPE0_DW0_09 9 -#define GPE0_DW0_10 10 -#define GPE0_DW0_11 11 -#define GPE0_DW0_12 12 -#define GPE0_DW0_13 13 -#define GPE0_DW0_14 14 -#define GPE0_DW0_15 15 -#define GPE0_DW0_16 16 -#define GPE0_DW0_17 17 -#define GPE0_DW0_18 18 -#define GPE0_DW0_19 19 -#define GPE0_DW0_20 20 -#define GPE0_DW0_21 21 -#define GPE0_DW0_22 22 -#define GPE0_DW0_23 23 -#define GPE0_DW0_24 24 -#define GPE0_DW0_25 25 -#define GPE0_DW0_26 26 -#define GPE0_DW0_27 27 -#define GPE0_DW0_28 28 -#define GPE0_DW0_29 29 -#define GPE0_DW0_30 30 -#define GPE0_DW0_31 31 -/* GPE_63_32 */ -#define GPE0_DW1_00 32 -#define GPE0_DW1_01 33 -#define GPE0_DW1_02 34 -#define GPE0_DW1_03 36 -#define GPE0_DW1_04 36 -#define GPE0_DW1_05 37 -#define GPE0_DW1_06 38 -#define GPE0_DW1_07 39 -#define GPE0_DW1_08 40 -#define GPE0_DW1_09 41 -#define GPE0_DW1_10 42 -#define GPE0_DW1_11 43 -#define GPE0_DW1_12 44 -#define GPE0_DW1_13 45 -#define GPE0_DW1_14 46 -#define GPE0_DW1_15 47 -#define GPE0_DW1_16 48 -#define GPE0_DW1_17 49 -#define GPE0_DW1_18 50 -#define GPE0_DW1_19 51 -#define GPE0_DW1_20 52 -#define GPE0_DW1_21 53 -#define GPE0_DW1_22 54 -#define GPE0_DW1_23 55 -#define GPE0_DW1_24 56 -#define GPE0_DW1_25 57 -#define GPE0_DW1_26 58 -#define GPE0_DW1_27 59 -#define GPE0_DW1_28 60 -#define GPE0_DW1_29 61 -#define GPE0_DW1_30 62 -#define GPE0_DW1_31 63 -/* GPE_95_64 */ -#define GPE0_DW2_00 64 -#define GPE0_DW2_01 65 -#define GPE0_DW2_02 66 -#define GPE0_DW2_03 67 -#define GPE0_DW2_04 68 -#define GPE0_DW2_05 69 -#define GPE0_DW2_06 70 -#define GPE0_DW2_07 71 -#define GPE0_DW2_08 72 -#define GPE0_DW2_09 73 -#define GPE0_DW2_10 74 -#define GPE0_DW2_11 75 -#define GPE0_DW2_12 76 -#define GPE0_DW2_13 77 -#define GPE0_DW2_14 78 -#define GPE0_DW2_15 79 -#define GPE0_DW2_16 80 -#define GPE0_DW2_17 81 -#define GPE0_DW2_18 82 -#define GPE0_DW2_19 83 -#define GPE0_DW2_20 84 -#define GPE0_DW2_21 85 -#define GPE0_DW2_22 86 -#define GPE0_DW2_23 87 -#define GPE0_DW2_24 88 -#define GPE0_DW2_25 89 -#define GPE0_DW2_26 90 -#define GPE0_DW2_27 91 -#define GPE0_DW2_28 92 -#define GPE0_DW2_29 93 -#define GPE0_DW2_30 94 -#define GPE0_DW2_31 95 -/* GPE_STD */ -#define GPE0_HOT_PLUG 97 -#define GPE0_SWGPE 98 -#define GPE0_TCOSCI 102 -#define GPE0_SMB_WAK 103 -#define GPE0_PCI_EXP 105 -#define GPE0_BATLOW 106 -#define GPE0_PME 107 -#define GPE0_ME_SCI 108 -#define GPE0_PME_B0 109 -#define GPE0_ESPI 110 -#define GPE0_GPIO_T2 111 -#define GPE0_LAN_WAK 112 -#define GPE0_WADT 114 +#include <intelpch/gpe.h> -#define GPE_MAX GPE0_WADT #endif /* _SOC_GPE_H_ */ diff --git a/src/soc/intel/cannonlake/include/soc/gpe.h b/src/soc/intel/cannonlake/include/soc/gpe.h index 34dfcea..6c08d35 100644 --- a/src/soc/intel/cannonlake/include/soc/gpe.h +++ b/src/soc/intel/cannonlake/include/soc/gpe.h @@ -3,119 +3,6 @@ #ifndef _SOC_GPE_H_ #define _SOC_GPE_H_ -/* GPE_31_0 */ -#define GPE0_DW0_00 0 -#define GPE0_DW0_01 1 -#define GPE0_DW0_02 2 -#define GPE0_DW0_03 3 -#define GPE0_DW0_04 4 -#define GPE0_DW0_05 5 -#define GPE0_DW0_06 6 -#define GPE0_DW0_07 7 -#define GPE0_DW0_08 8 -#define GPE0_DW0_09 9 -#define GPE0_DW0_10 10 -#define GPE0_DW0_11 11 -#define GPE0_DW0_12 12 -#define GPE0_DW0_13 13 -#define GPE0_DW0_14 14 -#define GPE0_DW0_15 15 -#define GPE0_DW0_16 16 -#define GPE0_DW0_17 17 -#define GPE0_DW0_18 18 -#define GPE0_DW0_19 19 -#define GPE0_DW0_20 20 -#define GPE0_DW0_21 21 -#define GPE0_DW0_22 22 -#define GPE0_DW0_23 23 -#define GPE0_DW0_24 24 -#define GPE0_DW0_25 25 -#define GPE0_DW0_26 26 -#define GPE0_DW0_27 27 -#define GPE0_DW0_28 28 -#define GPE0_DW0_29 29 -#define GPE0_DW0_30 30 -#define GPE0_DW0_31 31 -/* GPE_63_32 */ -#define GPE0_DW1_00 32 -#define GPE0_DW1_01 33 -#define GPE0_DW1_02 34 -#define GPE0_DW1_03 36 -#define GPE0_DW1_04 36 -#define GPE0_DW1_05 37 -#define GPE0_DW1_06 38 -#define GPE0_DW1_07 39 -#define GPE0_DW1_08 40 -#define GPE0_DW1_09 41 -#define GPE0_DW1_10 42 -#define GPE0_DW1_11 43 -#define GPE0_DW1_12 44 -#define GPE0_DW1_13 45 -#define GPE0_DW1_14 46 -#define GPE0_DW1_15 47 -#define GPE0_DW1_16 48 -#define GPE0_DW1_17 49 -#define GPE0_DW1_18 50 -#define GPE0_DW1_19 51 -#define GPE0_DW1_20 52 -#define GPE0_DW1_21 53 -#define GPE0_DW1_22 54 -#define GPE0_DW1_23 55 -#define GPE0_DW1_24 56 -#define GPE0_DW1_25 57 -#define GPE0_DW1_26 58 -#define GPE0_DW1_27 59 -#define GPE0_DW1_28 60 -#define GPE0_DW1_29 61 -#define GPE0_DW1_30 62 -#define GPE0_DW1_31 63 -/* GPE_95_64 */ -#define GPE0_DW2_00 64 -#define GPE0_DW2_01 65 -#define GPE0_DW2_02 66 -#define GPE0_DW2_03 67 -#define GPE0_DW2_04 68 -#define GPE0_DW2_05 69 -#define GPE0_DW2_06 70 -#define GPE0_DW2_07 71 -#define GPE0_DW2_08 72 -#define GPE0_DW2_09 73 -#define GPE0_DW2_10 74 -#define GPE0_DW2_11 75 -#define GPE0_DW2_12 76 -#define GPE0_DW2_13 77 -#define GPE0_DW2_14 78 -#define GPE0_DW2_15 79 -#define GPE0_DW2_16 80 -#define GPE0_DW2_17 81 -#define GPE0_DW2_18 82 -#define GPE0_DW2_19 83 -#define GPE0_DW2_20 84 -#define GPE0_DW2_21 85 -#define GPE0_DW2_22 86 -#define GPE0_DW2_23 87 -#define GPE0_DW2_24 88 -#define GPE0_DW2_25 89 -#define GPE0_DW2_26 90 -#define GPE0_DW2_27 91 -#define GPE0_DW2_28 92 -#define GPE0_DW2_29 93 -#define GPE0_DW2_30 94 -#define GPE0_DW2_31 95 -/* GPE_STD */ -#define GPE0_HOT_PLUG 97 -#define GPE0_SWGPE 98 -#define GPE0_TCOSCI 102 -#define GPE0_SMB_WAK 103 -#define GPE0_PCI_EXP 105 -#define GPE0_BATLOW 106 -#define GPE0_PME 107 -#define GPE0_ME_SCI 108 -#define GPE0_PME_B0 109 -#define GPE0_ESPI 110 -#define GPE0_GPIO_T2 111 -#define GPE0_LAN_WAK 112 -#define GPE0_WADT 114 +#include <intelpch/gpe.h> -#define GPE_MAX GPE0_WADT #endif /* _SOC_GPE_H_ */ diff --git a/src/soc/intel/common/pch/include/intelpch/gpe.h b/src/soc/intel/common/pch/include/intelpch/gpe.h new file mode 100644 index 0000000..2e3f44a --- /dev/null +++ b/src/soc/intel/common/pch/include/intelpch/gpe.h @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _INTELPCH_GPE_H_ +#define _INTELPCH_GPE_H_ + +/* GPE_31_0 */ +#define GPE0_DW0_00 0 +#define GPE0_DW0_01 1 +#define GPE0_DW0_02 2 +#define GPE0_DW0_03 3 +#define GPE0_DW0_04 4 +#define GPE0_DW0_05 5 +#define GPE0_DW0_06 6 +#define GPE0_DW0_07 7 +#define GPE0_DW0_08 8 +#define GPE0_DW0_09 9 +#define GPE0_DW0_10 10 +#define GPE0_DW0_11 11 +#define GPE0_DW0_12 12 +#define GPE0_DW0_13 13 +#define GPE0_DW0_14 14 +#define GPE0_DW0_15 15 +#define GPE0_DW0_16 16 +#define GPE0_DW0_17 17 +#define GPE0_DW0_18 18 +#define GPE0_DW0_19 19 +#define GPE0_DW0_20 20 +#define GPE0_DW0_21 21 +#define GPE0_DW0_22 22 +#define GPE0_DW0_23 23 +#define GPE0_DW0_24 24 +#define GPE0_DW0_25 25 +#define GPE0_DW0_26 26 +#define GPE0_DW0_27 27 +#define GPE0_DW0_28 28 +#define GPE0_DW0_29 29 +#define GPE0_DW0_30 30 +#define GPE0_DW0_31 31 +/* GPE_63_32 */ +#define GPE0_DW1_00 32 +#define GPE0_DW1_01 33 +#define GPE0_DW1_02 34 +#define GPE0_DW1_03 36 +#define GPE0_DW1_04 36 +#define GPE0_DW1_05 37 +#define GPE0_DW1_06 38 +#define GPE0_DW1_07 39 +#define GPE0_DW1_08 40 +#define GPE0_DW1_09 41 +#define GPE0_DW1_10 42 +#define GPE0_DW1_11 43 +#define GPE0_DW1_12 44 +#define GPE0_DW1_13 45 +#define GPE0_DW1_14 46 +#define GPE0_DW1_15 47 +#define GPE0_DW1_16 48 +#define GPE0_DW1_17 49 +#define GPE0_DW1_18 50 +#define GPE0_DW1_19 51 +#define GPE0_DW1_20 52 +#define GPE0_DW1_21 53 +#define GPE0_DW1_22 54 +#define GPE0_DW1_23 55 +#define GPE0_DW1_24 56 +#define GPE0_DW1_25 57 +#define GPE0_DW1_26 58 +#define GPE0_DW1_27 59 +#define GPE0_DW1_28 60 +#define GPE0_DW1_29 61 +#define GPE0_DW1_30 62 +#define GPE0_DW1_31 63 +/* GPE_95_64 */ +#define GPE0_DW2_00 64 +#define GPE0_DW2_01 65 +#define GPE0_DW2_02 66 +#define GPE0_DW2_03 67 +#define GPE0_DW2_04 68 +#define GPE0_DW2_05 69 +#define GPE0_DW2_06 70 +#define GPE0_DW2_07 71 +#define GPE0_DW2_08 72 +#define GPE0_DW2_09 73 +#define GPE0_DW2_10 74 +#define GPE0_DW2_11 75 +#define GPE0_DW2_12 76 +#define GPE0_DW2_13 77 +#define GPE0_DW2_14 78 +#define GPE0_DW2_15 79 +#define GPE0_DW2_16 80 +#define GPE0_DW2_17 81 +#define GPE0_DW2_18 82 +#define GPE0_DW2_19 83 +#define GPE0_DW2_20 84 +#define GPE0_DW2_21 85 +#define GPE0_DW2_22 86 +#define GPE0_DW2_23 87 +#define GPE0_DW2_24 88 +#define GPE0_DW2_25 89 +#define GPE0_DW2_26 90 +#define GPE0_DW2_27 91 +#define GPE0_DW2_28 92 +#define GPE0_DW2_29 93 +#define GPE0_DW2_30 94 +#define GPE0_DW2_31 95 +/* GPE_STD */ +#define GPE0_HOT_PLUG 97 +#define GPE0_SWGPE 98 +#define GPE0_TCOSCI 102 +#define GPE0_SMB_WAK 103 +#define GPE0_PCI_EXP 105 +#define GPE0_BATLOW 106 +#define GPE0_PME 107 +#define GPE0_ME_SCI 108 +#define GPE0_PME_B0 109 +#define GPE0_ESPI 110 +#define GPE0_GPIO_T2 111 +#define GPE0_LAN_WAK 112 +#define GPE0_WADT 114 + +#define GPE_MAX GPE0_WADT + +#endif /* _INTELPCH_GPE_H_ */ diff --git a/src/soc/intel/elkhartlake/include/soc/gpe.h b/src/soc/intel/elkhartlake/include/soc/gpe.h index 34dfcea..6c08d35 100644 --- a/src/soc/intel/elkhartlake/include/soc/gpe.h +++ b/src/soc/intel/elkhartlake/include/soc/gpe.h @@ -3,119 +3,6 @@ #ifndef _SOC_GPE_H_ #define _SOC_GPE_H_ -/* GPE_31_0 */ -#define GPE0_DW0_00 0 -#define GPE0_DW0_01 1 -#define GPE0_DW0_02 2 -#define GPE0_DW0_03 3 -#define GPE0_DW0_04 4 -#define GPE0_DW0_05 5 -#define GPE0_DW0_06 6 -#define GPE0_DW0_07 7 -#define GPE0_DW0_08 8 -#define GPE0_DW0_09 9 -#define GPE0_DW0_10 10 -#define GPE0_DW0_11 11 -#define GPE0_DW0_12 12 -#define GPE0_DW0_13 13 -#define GPE0_DW0_14 14 -#define GPE0_DW0_15 15 -#define GPE0_DW0_16 16 -#define GPE0_DW0_17 17 -#define GPE0_DW0_18 18 -#define GPE0_DW0_19 19 -#define GPE0_DW0_20 20 -#define GPE0_DW0_21 21 -#define GPE0_DW0_22 22 -#define GPE0_DW0_23 23 -#define GPE0_DW0_24 24 -#define GPE0_DW0_25 25 -#define GPE0_DW0_26 26 -#define GPE0_DW0_27 27 -#define GPE0_DW0_28 28 -#define GPE0_DW0_29 29 -#define GPE0_DW0_30 30 -#define GPE0_DW0_31 31 -/* GPE_63_32 */ -#define GPE0_DW1_00 32 -#define GPE0_DW1_01 33 -#define GPE0_DW1_02 34 -#define GPE0_DW1_03 36 -#define GPE0_DW1_04 36 -#define GPE0_DW1_05 37 -#define GPE0_DW1_06 38 -#define GPE0_DW1_07 39 -#define GPE0_DW1_08 40 -#define GPE0_DW1_09 41 -#define GPE0_DW1_10 42 -#define GPE0_DW1_11 43 -#define GPE0_DW1_12 44 -#define GPE0_DW1_13 45 -#define GPE0_DW1_14 46 -#define GPE0_DW1_15 47 -#define GPE0_DW1_16 48 -#define GPE0_DW1_17 49 -#define GPE0_DW1_18 50 -#define GPE0_DW1_19 51 -#define GPE0_DW1_20 52 -#define GPE0_DW1_21 53 -#define GPE0_DW1_22 54 -#define GPE0_DW1_23 55 -#define GPE0_DW1_24 56 -#define GPE0_DW1_25 57 -#define GPE0_DW1_26 58 -#define GPE0_DW1_27 59 -#define GPE0_DW1_28 60 -#define GPE0_DW1_29 61 -#define GPE0_DW1_30 62 -#define GPE0_DW1_31 63 -/* GPE_95_64 */ -#define GPE0_DW2_00 64 -#define GPE0_DW2_01 65 -#define GPE0_DW2_02 66 -#define GPE0_DW2_03 67 -#define GPE0_DW2_04 68 -#define GPE0_DW2_05 69 -#define GPE0_DW2_06 70 -#define GPE0_DW2_07 71 -#define GPE0_DW2_08 72 -#define GPE0_DW2_09 73 -#define GPE0_DW2_10 74 -#define GPE0_DW2_11 75 -#define GPE0_DW2_12 76 -#define GPE0_DW2_13 77 -#define GPE0_DW2_14 78 -#define GPE0_DW2_15 79 -#define GPE0_DW2_16 80 -#define GPE0_DW2_17 81 -#define GPE0_DW2_18 82 -#define GPE0_DW2_19 83 -#define GPE0_DW2_20 84 -#define GPE0_DW2_21 85 -#define GPE0_DW2_22 86 -#define GPE0_DW2_23 87 -#define GPE0_DW2_24 88 -#define GPE0_DW2_25 89 -#define GPE0_DW2_26 90 -#define GPE0_DW2_27 91 -#define GPE0_DW2_28 92 -#define GPE0_DW2_29 93 -#define GPE0_DW2_30 94 -#define GPE0_DW2_31 95 -/* GPE_STD */ -#define GPE0_HOT_PLUG 97 -#define GPE0_SWGPE 98 -#define GPE0_TCOSCI 102 -#define GPE0_SMB_WAK 103 -#define GPE0_PCI_EXP 105 -#define GPE0_BATLOW 106 -#define GPE0_PME 107 -#define GPE0_ME_SCI 108 -#define GPE0_PME_B0 109 -#define GPE0_ESPI 110 -#define GPE0_GPIO_T2 111 -#define GPE0_LAN_WAK 112 -#define GPE0_WADT 114 +#include <intelpch/gpe.h> -#define GPE_MAX GPE0_WADT #endif /* _SOC_GPE_H_ */ diff --git a/src/soc/intel/icelake/include/soc/gpe.h b/src/soc/intel/icelake/include/soc/gpe.h index 34dfcea..6c08d35 100644 --- a/src/soc/intel/icelake/include/soc/gpe.h +++ b/src/soc/intel/icelake/include/soc/gpe.h @@ -3,119 +3,6 @@ #ifndef _SOC_GPE_H_ #define _SOC_GPE_H_ -/* GPE_31_0 */ -#define GPE0_DW0_00 0 -#define GPE0_DW0_01 1 -#define GPE0_DW0_02 2 -#define GPE0_DW0_03 3 -#define GPE0_DW0_04 4 -#define GPE0_DW0_05 5 -#define GPE0_DW0_06 6 -#define GPE0_DW0_07 7 -#define GPE0_DW0_08 8 -#define GPE0_DW0_09 9 -#define GPE0_DW0_10 10 -#define GPE0_DW0_11 11 -#define GPE0_DW0_12 12 -#define GPE0_DW0_13 13 -#define GPE0_DW0_14 14 -#define GPE0_DW0_15 15 -#define GPE0_DW0_16 16 -#define GPE0_DW0_17 17 -#define GPE0_DW0_18 18 -#define GPE0_DW0_19 19 -#define GPE0_DW0_20 20 -#define GPE0_DW0_21 21 -#define GPE0_DW0_22 22 -#define GPE0_DW0_23 23 -#define GPE0_DW0_24 24 -#define GPE0_DW0_25 25 -#define GPE0_DW0_26 26 -#define GPE0_DW0_27 27 -#define GPE0_DW0_28 28 -#define GPE0_DW0_29 29 -#define GPE0_DW0_30 30 -#define GPE0_DW0_31 31 -/* GPE_63_32 */ -#define GPE0_DW1_00 32 -#define GPE0_DW1_01 33 -#define GPE0_DW1_02 34 -#define GPE0_DW1_03 36 -#define GPE0_DW1_04 36 -#define GPE0_DW1_05 37 -#define GPE0_DW1_06 38 -#define GPE0_DW1_07 39 -#define GPE0_DW1_08 40 -#define GPE0_DW1_09 41 -#define GPE0_DW1_10 42 -#define GPE0_DW1_11 43 -#define GPE0_DW1_12 44 -#define GPE0_DW1_13 45 -#define GPE0_DW1_14 46 -#define GPE0_DW1_15 47 -#define GPE0_DW1_16 48 -#define GPE0_DW1_17 49 -#define GPE0_DW1_18 50 -#define GPE0_DW1_19 51 -#define GPE0_DW1_20 52 -#define GPE0_DW1_21 53 -#define GPE0_DW1_22 54 -#define GPE0_DW1_23 55 -#define GPE0_DW1_24 56 -#define GPE0_DW1_25 57 -#define GPE0_DW1_26 58 -#define GPE0_DW1_27 59 -#define GPE0_DW1_28 60 -#define GPE0_DW1_29 61 -#define GPE0_DW1_30 62 -#define GPE0_DW1_31 63 -/* GPE_95_64 */ -#define GPE0_DW2_00 64 -#define GPE0_DW2_01 65 -#define GPE0_DW2_02 66 -#define GPE0_DW2_03 67 -#define GPE0_DW2_04 68 -#define GPE0_DW2_05 69 -#define GPE0_DW2_06 70 -#define GPE0_DW2_07 71 -#define GPE0_DW2_08 72 -#define GPE0_DW2_09 73 -#define GPE0_DW2_10 74 -#define GPE0_DW2_11 75 -#define GPE0_DW2_12 76 -#define GPE0_DW2_13 77 -#define GPE0_DW2_14 78 -#define GPE0_DW2_15 79 -#define GPE0_DW2_16 80 -#define GPE0_DW2_17 81 -#define GPE0_DW2_18 82 -#define GPE0_DW2_19 83 -#define GPE0_DW2_20 84 -#define GPE0_DW2_21 85 -#define GPE0_DW2_22 86 -#define GPE0_DW2_23 87 -#define GPE0_DW2_24 88 -#define GPE0_DW2_25 89 -#define GPE0_DW2_26 90 -#define GPE0_DW2_27 91 -#define GPE0_DW2_28 92 -#define GPE0_DW2_29 93 -#define GPE0_DW2_30 94 -#define GPE0_DW2_31 95 -/* GPE_STD */ -#define GPE0_HOT_PLUG 97 -#define GPE0_SWGPE 98 -#define GPE0_TCOSCI 102 -#define GPE0_SMB_WAK 103 -#define GPE0_PCI_EXP 105 -#define GPE0_BATLOW 106 -#define GPE0_PME 107 -#define GPE0_ME_SCI 108 -#define GPE0_PME_B0 109 -#define GPE0_ESPI 110 -#define GPE0_GPIO_T2 111 -#define GPE0_LAN_WAK 112 -#define GPE0_WADT 114 +#include <intelpch/gpe.h> -#define GPE_MAX GPE0_WADT #endif /* _SOC_GPE_H_ */ diff --git a/src/soc/intel/jasperlake/include/soc/gpe.h b/src/soc/intel/jasperlake/include/soc/gpe.h index 34dfcea..6c08d35 100644 --- a/src/soc/intel/jasperlake/include/soc/gpe.h +++ b/src/soc/intel/jasperlake/include/soc/gpe.h @@ -3,119 +3,6 @@ #ifndef _SOC_GPE_H_ #define _SOC_GPE_H_ -/* GPE_31_0 */ -#define GPE0_DW0_00 0 -#define GPE0_DW0_01 1 -#define GPE0_DW0_02 2 -#define GPE0_DW0_03 3 -#define GPE0_DW0_04 4 -#define GPE0_DW0_05 5 -#define GPE0_DW0_06 6 -#define GPE0_DW0_07 7 -#define GPE0_DW0_08 8 -#define GPE0_DW0_09 9 -#define GPE0_DW0_10 10 -#define GPE0_DW0_11 11 -#define GPE0_DW0_12 12 -#define GPE0_DW0_13 13 -#define GPE0_DW0_14 14 -#define GPE0_DW0_15 15 -#define GPE0_DW0_16 16 -#define GPE0_DW0_17 17 -#define GPE0_DW0_18 18 -#define GPE0_DW0_19 19 -#define GPE0_DW0_20 20 -#define GPE0_DW0_21 21 -#define GPE0_DW0_22 22 -#define GPE0_DW0_23 23 -#define GPE0_DW0_24 24 -#define GPE0_DW0_25 25 -#define GPE0_DW0_26 26 -#define GPE0_DW0_27 27 -#define GPE0_DW0_28 28 -#define GPE0_DW0_29 29 -#define GPE0_DW0_30 30 -#define GPE0_DW0_31 31 -/* GPE_63_32 */ -#define GPE0_DW1_00 32 -#define GPE0_DW1_01 33 -#define GPE0_DW1_02 34 -#define GPE0_DW1_03 36 -#define GPE0_DW1_04 36 -#define GPE0_DW1_05 37 -#define GPE0_DW1_06 38 -#define GPE0_DW1_07 39 -#define GPE0_DW1_08 40 -#define GPE0_DW1_09 41 -#define GPE0_DW1_10 42 -#define GPE0_DW1_11 43 -#define GPE0_DW1_12 44 -#define GPE0_DW1_13 45 -#define GPE0_DW1_14 46 -#define GPE0_DW1_15 47 -#define GPE0_DW1_16 48 -#define GPE0_DW1_17 49 -#define GPE0_DW1_18 50 -#define GPE0_DW1_19 51 -#define GPE0_DW1_20 52 -#define GPE0_DW1_21 53 -#define GPE0_DW1_22 54 -#define GPE0_DW1_23 55 -#define GPE0_DW1_24 56 -#define GPE0_DW1_25 57 -#define GPE0_DW1_26 58 -#define GPE0_DW1_27 59 -#define GPE0_DW1_28 60 -#define GPE0_DW1_29 61 -#define GPE0_DW1_30 62 -#define GPE0_DW1_31 63 -/* GPE_95_64 */ -#define GPE0_DW2_00 64 -#define GPE0_DW2_01 65 -#define GPE0_DW2_02 66 -#define GPE0_DW2_03 67 -#define GPE0_DW2_04 68 -#define GPE0_DW2_05 69 -#define GPE0_DW2_06 70 -#define GPE0_DW2_07 71 -#define GPE0_DW2_08 72 -#define GPE0_DW2_09 73 -#define GPE0_DW2_10 74 -#define GPE0_DW2_11 75 -#define GPE0_DW2_12 76 -#define GPE0_DW2_13 77 -#define GPE0_DW2_14 78 -#define GPE0_DW2_15 79 -#define GPE0_DW2_16 80 -#define GPE0_DW2_17 81 -#define GPE0_DW2_18 82 -#define GPE0_DW2_19 83 -#define GPE0_DW2_20 84 -#define GPE0_DW2_21 85 -#define GPE0_DW2_22 86 -#define GPE0_DW2_23 87 -#define GPE0_DW2_24 88 -#define GPE0_DW2_25 89 -#define GPE0_DW2_26 90 -#define GPE0_DW2_27 91 -#define GPE0_DW2_28 92 -#define GPE0_DW2_29 93 -#define GPE0_DW2_30 94 -#define GPE0_DW2_31 95 -/* GPE_STD */ -#define GPE0_HOT_PLUG 97 -#define GPE0_SWGPE 98 -#define GPE0_TCOSCI 102 -#define GPE0_SMB_WAK 103 -#define GPE0_PCI_EXP 105 -#define GPE0_BATLOW 106 -#define GPE0_PME 107 -#define GPE0_ME_SCI 108 -#define GPE0_PME_B0 109 -#define GPE0_ESPI 110 -#define GPE0_GPIO_T2 111 -#define GPE0_LAN_WAK 112 -#define GPE0_WADT 114 +#include <intelpch/gpe.h> -#define GPE_MAX GPE0_WADT #endif /* _SOC_GPE_H_ */ diff --git a/src/soc/intel/skylake/include/soc/gpe.h b/src/soc/intel/skylake/include/soc/gpe.h index 09513ee..6c08d35 100644 --- a/src/soc/intel/skylake/include/soc/gpe.h +++ b/src/soc/intel/skylake/include/soc/gpe.h @@ -3,120 +3,6 @@ #ifndef _SOC_GPE_H_ #define _SOC_GPE_H_ -/* GPE_31_0 */ -#define GPE0_DW0_00 0 -#define GPE0_DW0_01 1 -#define GPE0_DW0_02 2 -#define GPE0_DW0_03 3 -#define GPE0_DW0_04 4 -#define GPE0_DW0_05 5 -#define GPE0_DW0_06 6 -#define GPE0_DW0_07 7 -#define GPE0_DW0_08 8 -#define GPE0_DW0_09 9 -#define GPE0_DW0_10 10 -#define GPE0_DW0_11 11 -#define GPE0_DW0_12 12 -#define GPE0_DW0_13 13 -#define GPE0_DW0_14 14 -#define GPE0_DW0_15 15 -#define GPE0_DW0_16 16 -#define GPE0_DW0_17 17 -#define GPE0_DW0_18 18 -#define GPE0_DW0_19 19 -#define GPE0_DW0_20 20 -#define GPE0_DW0_21 21 -#define GPE0_DW0_22 22 -#define GPE0_DW0_23 23 -#define GPE0_DW0_24 24 -#define GPE0_DW0_25 25 -#define GPE0_DW0_26 26 -#define GPE0_DW0_27 27 -#define GPE0_DW0_28 28 -#define GPE0_DW0_29 29 -#define GPE0_DW0_30 30 -#define GPE0_DW0_31 31 -/* GPE_63_32 */ -#define GPE0_DW1_00 32 -#define GPE0_DW1_01 33 -#define GPE0_DW1_02 34 -#define GPE0_DW1_03 36 -#define GPE0_DW1_04 36 -#define GPE0_DW1_05 37 -#define GPE0_DW1_06 38 -#define GPE0_DW1_07 39 -#define GPE0_DW1_08 40 -#define GPE0_DW1_09 41 -#define GPE0_DW1_10 42 -#define GPE0_DW1_11 43 -#define GPE0_DW1_12 44 -#define GPE0_DW1_13 45 -#define GPE0_DW1_14 46 -#define GPE0_DW1_15 47 -#define GPE0_DW1_16 48 -#define GPE0_DW1_17 49 -#define GPE0_DW1_18 50 -#define GPE0_DW1_19 51 -#define GPE0_DW1_20 52 -#define GPE0_DW1_21 53 -#define GPE0_DW1_22 54 -#define GPE0_DW1_23 55 -#define GPE0_DW1_24 56 -#define GPE0_DW1_25 57 -#define GPE0_DW1_26 58 -#define GPE0_DW1_27 59 -#define GPE0_DW1_28 60 -#define GPE0_DW1_29 61 -#define GPE0_DW1_30 62 -#define GPE0_DW1_31 63 -/* GPE_95_64 */ -#define GPE0_DW2_00 64 -#define GPE0_DW2_01 65 -#define GPE0_DW2_02 66 -#define GPE0_DW2_03 67 -#define GPE0_DW2_04 68 -#define GPE0_DW2_05 69 -#define GPE0_DW2_06 70 -#define GPE0_DW2_07 71 -#define GPE0_DW2_08 72 -#define GPE0_DW2_09 73 -#define GPE0_DW2_10 74 -#define GPE0_DW2_11 75 -#define GPE0_DW2_12 76 -#define GPE0_DW2_13 77 -#define GPE0_DW2_14 78 -#define GPE0_DW2_15 79 -#define GPE0_DW2_16 80 -#define GPE0_DW2_17 81 -#define GPE0_DW2_18 82 -#define GPE0_DW2_19 83 -#define GPE0_DW2_20 84 -#define GPE0_DW2_21 85 -#define GPE0_DW2_22 86 -#define GPE0_DW2_23 87 -#define GPE0_DW2_24 88 -#define GPE0_DW2_25 89 -#define GPE0_DW2_26 90 -#define GPE0_DW2_27 91 -#define GPE0_DW2_28 92 -#define GPE0_DW2_29 93 -#define GPE0_DW2_30 94 -#define GPE0_DW2_31 95 -/* GPE_STD */ -#define GPE0_HOT_PLUG 97 -#define GPE0_SWGPE 98 -#define GPE0_TCOSCI 102 -#define GPE0_SMB_WAK 103 -#define GPE0_PCI_EXP 105 -#define GPE0_BATLOW 106 -#define GPE0_PME 107 -#define GPE0_ME_SCI 108 -#define GPE0_PME_B0 109 -#define GPE0_ESPI 110 -#define GPE0_GPIO_T2 111 -#define GPE0_LAN_WAK 112 -#define GPE0_WADT 114 - -#define GPE_MAX GPE0_WADT +#include <intelpch/gpe.h> #endif /* _SOC_GPE_H_ */ diff --git a/src/soc/intel/tigerlake/include/soc/gpe.h b/src/soc/intel/tigerlake/include/soc/gpe.h index 34dfcea..6c08d35 100644 --- a/src/soc/intel/tigerlake/include/soc/gpe.h +++ b/src/soc/intel/tigerlake/include/soc/gpe.h @@ -3,119 +3,6 @@ #ifndef _SOC_GPE_H_ #define _SOC_GPE_H_ -/* GPE_31_0 */ -#define GPE0_DW0_00 0 -#define GPE0_DW0_01 1 -#define GPE0_DW0_02 2 -#define GPE0_DW0_03 3 -#define GPE0_DW0_04 4 -#define GPE0_DW0_05 5 -#define GPE0_DW0_06 6 -#define GPE0_DW0_07 7 -#define GPE0_DW0_08 8 -#define GPE0_DW0_09 9 -#define GPE0_DW0_10 10 -#define GPE0_DW0_11 11 -#define GPE0_DW0_12 12 -#define GPE0_DW0_13 13 -#define GPE0_DW0_14 14 -#define GPE0_DW0_15 15 -#define GPE0_DW0_16 16 -#define GPE0_DW0_17 17 -#define GPE0_DW0_18 18 -#define GPE0_DW0_19 19 -#define GPE0_DW0_20 20 -#define GPE0_DW0_21 21 -#define GPE0_DW0_22 22 -#define GPE0_DW0_23 23 -#define GPE0_DW0_24 24 -#define GPE0_DW0_25 25 -#define GPE0_DW0_26 26 -#define GPE0_DW0_27 27 -#define GPE0_DW0_28 28 -#define GPE0_DW0_29 29 -#define GPE0_DW0_30 30 -#define GPE0_DW0_31 31 -/* GPE_63_32 */ -#define GPE0_DW1_00 32 -#define GPE0_DW1_01 33 -#define GPE0_DW1_02 34 -#define GPE0_DW1_03 36 -#define GPE0_DW1_04 36 -#define GPE0_DW1_05 37 -#define GPE0_DW1_06 38 -#define GPE0_DW1_07 39 -#define GPE0_DW1_08 40 -#define GPE0_DW1_09 41 -#define GPE0_DW1_10 42 -#define GPE0_DW1_11 43 -#define GPE0_DW1_12 44 -#define GPE0_DW1_13 45 -#define GPE0_DW1_14 46 -#define GPE0_DW1_15 47 -#define GPE0_DW1_16 48 -#define GPE0_DW1_17 49 -#define GPE0_DW1_18 50 -#define GPE0_DW1_19 51 -#define GPE0_DW1_20 52 -#define GPE0_DW1_21 53 -#define GPE0_DW1_22 54 -#define GPE0_DW1_23 55 -#define GPE0_DW1_24 56 -#define GPE0_DW1_25 57 -#define GPE0_DW1_26 58 -#define GPE0_DW1_27 59 -#define GPE0_DW1_28 60 -#define GPE0_DW1_29 61 -#define GPE0_DW1_30 62 -#define GPE0_DW1_31 63 -/* GPE_95_64 */ -#define GPE0_DW2_00 64 -#define GPE0_DW2_01 65 -#define GPE0_DW2_02 66 -#define GPE0_DW2_03 67 -#define GPE0_DW2_04 68 -#define GPE0_DW2_05 69 -#define GPE0_DW2_06 70 -#define GPE0_DW2_07 71 -#define GPE0_DW2_08 72 -#define GPE0_DW2_09 73 -#define GPE0_DW2_10 74 -#define GPE0_DW2_11 75 -#define GPE0_DW2_12 76 -#define GPE0_DW2_13 77 -#define GPE0_DW2_14 78 -#define GPE0_DW2_15 79 -#define GPE0_DW2_16 80 -#define GPE0_DW2_17 81 -#define GPE0_DW2_18 82 -#define GPE0_DW2_19 83 -#define GPE0_DW2_20 84 -#define GPE0_DW2_21 85 -#define GPE0_DW2_22 86 -#define GPE0_DW2_23 87 -#define GPE0_DW2_24 88 -#define GPE0_DW2_25 89 -#define GPE0_DW2_26 90 -#define GPE0_DW2_27 91 -#define GPE0_DW2_28 92 -#define GPE0_DW2_29 93 -#define GPE0_DW2_30 94 -#define GPE0_DW2_31 95 -/* GPE_STD */ -#define GPE0_HOT_PLUG 97 -#define GPE0_SWGPE 98 -#define GPE0_TCOSCI 102 -#define GPE0_SMB_WAK 103 -#define GPE0_PCI_EXP 105 -#define GPE0_BATLOW 106 -#define GPE0_PME 107 -#define GPE0_ME_SCI 108 -#define GPE0_PME_B0 109 -#define GPE0_ESPI 110 -#define GPE0_GPIO_T2 111 -#define GPE0_LAN_WAK 112 -#define GPE0_WADT 114 +#include <intelpch/gpe.h> -#define GPE_MAX GPE0_WADT #endif /* _SOC_GPE_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32bbd0777f8ca9d0362d210b43e0ba8dd0c8d79b Gerrit-Change-Number: 50940 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/skylake: Move soc_acpi_name()
by Angel Pons (Code Review) 01 Mar '21

01 Mar '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50939 ) Change subject: soc/intel/skylake: Move soc_acpi_name() ...................................................................... soc/intel/skylake: Move soc_acpi_name() Done for consistency with newer platforms. Change-Id: I1250c4514e1512e748bfc65c3f9f9da4ff1ef78e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50939 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/chip.c 2 files changed, 111 insertions(+), 109 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index c2eb9a8..0d89f29 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -548,112 +548,3 @@ return GPE0_REG_MAX; } - -const char *soc_acpi_name(const struct device *dev) -{ - if (dev->path.type == DEVICE_PATH_DOMAIN) - return "PCI0"; - - if (dev->path.type == DEVICE_PATH_USB) { - switch (dev->path.usb.port_type) { - case 0: - /* Root Hub */ - return "RHUB"; - case 2: - /* USB2 ports */ - switch (dev->path.usb.port_id) { - case 0: return "HS01"; - case 1: return "HS02"; - case 2: return "HS03"; - case 3: return "HS04"; - case 4: return "HS05"; - case 5: return "HS06"; - case 6: return "HS07"; - case 7: return "HS08"; - case 8: return "HS09"; - case 9: return "HS10"; - } - break; - case 3: - /* USB3 ports */ - switch (dev->path.usb.port_id) { - case 0: return "SS01"; - case 1: return "SS02"; - case 2: return "SS03"; - case 3: return "SS04"; - case 4: return "SS05"; - case 5: return "SS06"; - } - break; - } - return NULL; - } - - if (dev->path.type != DEVICE_PATH_PCI) - return NULL; - - /* Match functions 0 and 1 for possible GPUs on a secondary bus */ - if (dev->bus && dev->bus->secondary > 0) { - switch (PCI_FUNC(dev->path.pci.devfn)) { - case 0: return "DEV0"; - case 1: return "DEV1"; - } - return NULL; - } - - switch (dev->path.pci.devfn) { - case SA_DEVFN_ROOT: return "MCHC"; - case SA_DEVFN_PEG0: return "PEGP"; - case SA_DEVFN_IGD: return "GFX0"; - case PCH_DEVFN_ISH: return "ISHB"; - case PCH_DEVFN_XHCI: return "XHCI"; - case PCH_DEVFN_USBOTG: return "XDCI"; - case PCH_DEVFN_THERMAL: return "THRM"; - case PCH_DEVFN_CIO: return "ICIO"; - case PCH_DEVFN_I2C0: return "I2C0"; - case PCH_DEVFN_I2C1: return "I2C1"; - case PCH_DEVFN_I2C2: return "I2C2"; - case PCH_DEVFN_I2C3: return "I2C3"; - case PCH_DEVFN_CSE: return "CSE1"; - case PCH_DEVFN_CSE_2: return "CSE2"; - case PCH_DEVFN_CSE_IDER: return "CSED"; - case PCH_DEVFN_CSE_KT: return "CSKT"; - case PCH_DEVFN_CSE_3: return "CSE3"; - case PCH_DEVFN_SATA: return "SATA"; - case PCH_DEVFN_UART2: return "UAR2"; - case PCH_DEVFN_I2C4: return "I2C4"; - case PCH_DEVFN_I2C5: return "I2C5"; - case PCH_DEVFN_PCIE1: return "RP01"; - case PCH_DEVFN_PCIE2: return "RP02"; - case PCH_DEVFN_PCIE3: return "RP03"; - case PCH_DEVFN_PCIE4: return "RP04"; - case PCH_DEVFN_PCIE5: return "RP05"; - case PCH_DEVFN_PCIE6: return "RP06"; - case PCH_DEVFN_PCIE7: return "RP07"; - case PCH_DEVFN_PCIE8: return "RP08"; - case PCH_DEVFN_PCIE9: return "RP09"; - case PCH_DEVFN_PCIE10: return "RP10"; - case PCH_DEVFN_PCIE11: return "RP11"; - case PCH_DEVFN_PCIE12: return "RP12"; - case PCH_DEVFN_PCIE13: return "RP13"; - case PCH_DEVFN_PCIE14: return "RP14"; - case PCH_DEVFN_PCIE15: return "RP15"; - case PCH_DEVFN_PCIE16: return "RP16"; - case PCH_DEVFN_UART0: return "UAR0"; - case PCH_DEVFN_UART1: return "UAR1"; - case PCH_DEVFN_GSPI0: return "SPI0"; - case PCH_DEVFN_GSPI1: return "SPI1"; - case PCH_DEVFN_EMMC: return "EMMC"; - case PCH_DEVFN_SDIO: return "SDIO"; - case PCH_DEVFN_SDCARD: return "SDXC"; - case PCH_DEVFN_P2SB: return "P2SB"; - case PCH_DEVFN_PMC: return "PMC_"; - case PCH_DEVFN_HDA: return "HDAS"; - case PCH_DEVFN_SMBUS: return "SBUS"; - case PCH_DEVFN_SPI: return "FSPI"; - case PCH_DEVFN_GBE: return "IGBE"; - case PCH_DEVFN_TRACEHUB:return "THUB"; - } - - return NULL; -} diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 728b023..0ae98a9 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -48,6 +48,117 @@ { 0 } }; +#if CONFIG(HAVE_ACPI_TABLES) +const char *soc_acpi_name(const struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + + if (dev->path.type == DEVICE_PATH_USB) { + switch (dev->path.usb.port_type) { + case 0: + /* Root Hub */ + return "RHUB"; + case 2: + /* USB2 ports */ + switch (dev->path.usb.port_id) { + case 0: return "HS01"; + case 1: return "HS02"; + case 2: return "HS03"; + case 3: return "HS04"; + case 4: return "HS05"; + case 5: return "HS06"; + case 6: return "HS07"; + case 7: return "HS08"; + case 8: return "HS09"; + case 9: return "HS10"; + } + break; + case 3: + /* USB3 ports */ + switch (dev->path.usb.port_id) { + case 0: return "SS01"; + case 1: return "SS02"; + case 2: return "SS03"; + case 3: return "SS04"; + case 4: return "SS05"; + case 5: return "SS06"; + } + break; + } + return NULL; + } + + if (dev->path.type != DEVICE_PATH_PCI) + return NULL; + + /* Match functions 0 and 1 for possible GPUs on a secondary bus */ + if (dev->bus && dev->bus->secondary > 0) { + switch (PCI_FUNC(dev->path.pci.devfn)) { + case 0: return "DEV0"; + case 1: return "DEV1"; + } + return NULL; + } + + switch (dev->path.pci.devfn) { + case SA_DEVFN_ROOT: return "MCHC"; + case SA_DEVFN_PEG0: return "PEGP"; + case SA_DEVFN_IGD: return "GFX0"; + case PCH_DEVFN_ISH: return "ISHB"; + case PCH_DEVFN_XHCI: return "XHCI"; + case PCH_DEVFN_USBOTG: return "XDCI"; + case PCH_DEVFN_THERMAL: return "THRM"; + case PCH_DEVFN_CIO: return "ICIO"; + case PCH_DEVFN_I2C0: return "I2C0"; + case PCH_DEVFN_I2C1: return "I2C1"; + case PCH_DEVFN_I2C2: return "I2C2"; + case PCH_DEVFN_I2C3: return "I2C3"; + case PCH_DEVFN_CSE: return "CSE1"; + case PCH_DEVFN_CSE_2: return "CSE2"; + case PCH_DEVFN_CSE_IDER: return "CSED"; + case PCH_DEVFN_CSE_KT: return "CSKT"; + case PCH_DEVFN_CSE_3: return "CSE3"; + case PCH_DEVFN_SATA: return "SATA"; + case PCH_DEVFN_UART2: return "UAR2"; + case PCH_DEVFN_I2C4: return "I2C4"; + case PCH_DEVFN_I2C5: return "I2C5"; + case PCH_DEVFN_PCIE1: return "RP01"; + case PCH_DEVFN_PCIE2: return "RP02"; + case PCH_DEVFN_PCIE3: return "RP03"; + case PCH_DEVFN_PCIE4: return "RP04"; + case PCH_DEVFN_PCIE5: return "RP05"; + case PCH_DEVFN_PCIE6: return "RP06"; + case PCH_DEVFN_PCIE7: return "RP07"; + case PCH_DEVFN_PCIE8: return "RP08"; + case PCH_DEVFN_PCIE9: return "RP09"; + case PCH_DEVFN_PCIE10: return "RP10"; + case PCH_DEVFN_PCIE11: return "RP11"; + case PCH_DEVFN_PCIE12: return "RP12"; + case PCH_DEVFN_PCIE13: return "RP13"; + case PCH_DEVFN_PCIE14: return "RP14"; + case PCH_DEVFN_PCIE15: return "RP15"; + case PCH_DEVFN_PCIE16: return "RP16"; + case PCH_DEVFN_UART0: return "UAR0"; + case PCH_DEVFN_UART1: return "UAR1"; + case PCH_DEVFN_GSPI0: return "SPI0"; + case PCH_DEVFN_GSPI1: return "SPI1"; + case PCH_DEVFN_EMMC: return "EMMC"; + case PCH_DEVFN_SDIO: return "SDIO"; + case PCH_DEVFN_SDCARD: return "SDXC"; + case PCH_DEVFN_P2SB: return "P2SB"; + case PCH_DEVFN_PMC: return "PMC_"; + case PCH_DEVFN_HDA: return "HDAS"; + case PCH_DEVFN_SMBUS: return "SBUS"; + case PCH_DEVFN_SPI: return "FSPI"; + case PCH_DEVFN_GBE: return "IGBE"; + case PCH_DEVFN_TRACEHUB:return "THUB"; + } + + return NULL; +} +#endif + void soc_init_pre_device(void *chip_info) { /* Snapshot the current GPIO IRQ polarities. FSP is setting a -- To view, visit https://review.coreboot.org/c/coreboot/+/50939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1250c4514e1512e748bfc65c3f9f9da4ff1ef78e Gerrit-Change-Number: 50939 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel: Factor out identical acpigen GPIO helpers
by Angel Pons (Code Review) 01 Mar '21

01 Mar '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50938 ) Change subject: soc/intel: Factor out identical acpigen GPIO helpers ...................................................................... soc/intel: Factor out identical acpigen GPIO helpers Change-Id: I27f198d403f6ba05ba72ae0652da224d4cbf323a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50938 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/acpi.c M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/acpi.c M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/Makefile.inc A src/soc/intel/common/block/acpi/gpio.c M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/acpi.c M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/acpi.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/acpi.c 15 files changed, 50 insertions(+), 222 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 916e5f3..3bcdb22 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -47,6 +47,7 @@ select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index 2eb6101..db005e8 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -301,40 +301,3 @@ { return MP_IRQ_POLARITY_HIGH; } - -static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num) -{ - /* op (gpio_num) */ - acpigen_emit_namestring(op); - acpigen_write_integer(gpio_num); - return 0; -} - -static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num) -{ - /* Store (op (gpio_num), Local0) */ - acpigen_write_store(); - acpigen_soc_gpio_op(op, gpio_num); - acpigen_emit_byte(LOCAL0_OP); - return 0; -} - -int acpigen_soc_read_rx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_get_gpio_state("\\_SB.PCI0.GRXS", gpio_num); -} - -int acpigen_soc_get_tx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_get_gpio_state("\\_SB.PCI0.GTXS", gpio_num); -} - -int acpigen_soc_set_tx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_gpio_op("\\_SB.PCI0.STXS", gpio_num); -} - -int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_gpio_op("\\_SB.PCI0.CTXS", gpio_num); -} diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index dd7d699..187aed5 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -87,6 +87,7 @@ select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC + select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 03bf3c8..0bc4e63 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -206,43 +206,6 @@ return MP_IRQ_POLARITY_HIGH; } -static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num) -{ - /* op (gpio_num) */ - acpigen_emit_namestring(op); - acpigen_write_integer(gpio_num); - return 0; -} - -static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num) -{ - /* Store (op (gpio_num), Local0) */ - acpigen_write_store(); - acpigen_soc_gpio_op(op, gpio_num); - acpigen_emit_byte(LOCAL0_OP); - return 0; -} - -int acpigen_soc_read_rx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_get_gpio_state("\\_SB.PCI0.GRXS", gpio_num); -} - -int acpigen_soc_get_tx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_get_gpio_state("\\_SB.PCI0.GTXS", gpio_num); -} - -int acpigen_soc_set_tx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_gpio_op("\\_SB.PCI0.STXS", gpio_num); -} - -int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_gpio_op("\\_SB.PCI0.CTXS", gpio_num); -} - static unsigned long soc_fill_dmar(unsigned long current) { struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); diff --git a/src/soc/intel/common/block/acpi/Kconfig b/src/soc/intel/common/block/acpi/Kconfig index 8912ff3..6aa3abc 100644 --- a/src/soc/intel/common/block/acpi/Kconfig +++ b/src/soc/intel/common/block/acpi/Kconfig @@ -5,6 +5,9 @@ help Intel Processor common code for ACPI +config SOC_INTEL_COMMON_BLOCK_ACPI_GPIO + bool + config SOC_INTEL_COMMON_BLOCK_ACPI_LPIT bool depends on HAVE_ACPI_TABLES diff --git a/src/soc/intel/common/block/acpi/Makefile.inc b/src/soc/intel/common/block/acpi/Makefile.inc index 89565a6..c78dbc0 100644 --- a/src/soc/intel/common/block/acpi/Makefile.inc +++ b/src/soc/intel/common/block/acpi/Makefile.inc @@ -1,4 +1,5 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI) += acpi.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPIO) += gpio.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_LPIT) += lpit.c ramstage-$(CONFIG_ACPI_BERT) += acpi_bert.c ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c diff --git a/src/soc/intel/common/block/acpi/gpio.c b/src/soc/intel/common/block/acpi/gpio.c new file mode 100644 index 0000000..99847c5 --- /dev/null +++ b/src/soc/intel/common/block/acpi/gpio.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpigen.h> + +static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num) +{ + /* op (gpio_num) */ + acpigen_emit_namestring(op); + acpigen_write_integer(gpio_num); + return 0; +} + +static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num) +{ + /* Store (op (gpio_num), Local0) */ + acpigen_write_store(); + acpigen_soc_gpio_op(op, gpio_num); + acpigen_emit_byte(LOCAL0_OP); + return 0; +} + +int acpigen_soc_read_rx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_get_gpio_state("\\_SB.PCI0.GRXS", gpio_num); +} + +int acpigen_soc_get_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_get_gpio_state("\\_SB.PCI0.GTXS", gpio_num); +} + +int acpigen_soc_set_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_gpio_op("\\_SB.PCI0.STXS", gpio_num); +} + +int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_gpio_op("\\_SB.PCI0.CTXS", gpio_num); +} diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 3b17a0ed..b227ec2 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -39,6 +39,7 @@ select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG diff --git a/src/soc/intel/elkhartlake/acpi.c b/src/soc/intel/elkhartlake/acpi.c index 12706c9..0006b5f 100644 --- a/src/soc/intel/elkhartlake/acpi.c +++ b/src/soc/intel/elkhartlake/acpi.c @@ -269,40 +269,3 @@ { return MP_IRQ_POLARITY_HIGH; } - -static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num) -{ - /* op (gpio_num) */ - acpigen_emit_namestring(op); - acpigen_write_integer(gpio_num); - return 0; -} - -static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num) -{ - /* Store (op (gpio_num), Local0) */ - acpigen_write_store(); - acpigen_soc_gpio_op(op, gpio_num); - acpigen_emit_byte(LOCAL0_OP); - return 0; -} - -int acpigen_soc_read_rx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_get_gpio_state("\\_SB.PCI0.GRXS", gpio_num); -} - -int acpigen_soc_get_tx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_get_gpio_state("\\_SB.PCI0.GTXS", gpio_num); -} - -int acpigen_soc_set_tx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_gpio_op("\\_SB.PCI0.STXS", gpio_num); -} - -int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_gpio_op("\\_SB.PCI0.CTXS", gpio_num); -} diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 72912f7..d6281ec 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -40,6 +40,7 @@ select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index f33bebd..ebfa668 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -296,40 +296,3 @@ { return MP_IRQ_POLARITY_HIGH; } - -static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num) -{ - /* op (gpio_num) */ - acpigen_emit_namestring(op); - acpigen_write_integer(gpio_num); - return 0; -} - -static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num) -{ - /* Store (op (gpio_num), Local0) */ - acpigen_write_store(); - acpigen_soc_gpio_op(op, gpio_num); - acpigen_emit_byte(LOCAL0_OP); - return 0; -} - -int acpigen_soc_read_rx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_get_gpio_state("\\_SB.PCI0.GRXS", gpio_num); -} - -int acpigen_soc_get_tx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_get_gpio_state("\\_SB.PCI0.GTXS", gpio_num); -} - -int acpigen_soc_set_tx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_gpio_op("\\_SB.PCI0.STXS", gpio_num); -} - -int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_gpio_op("\\_SB.PCI0.CTXS", gpio_num); -} diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index a7e25b1..781cdbf 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -48,6 +48,7 @@ select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 100f16f..c2eb9a8 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -657,40 +657,3 @@ return NULL; } - -static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num) -{ - /* op (gpio_num) */ - acpigen_emit_namestring(op); - acpigen_write_integer(gpio_num); - return 0; -} - -static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num) -{ - /* Store (op (gpio_num), Local0) */ - acpigen_write_store(); - acpigen_soc_gpio_op(op, gpio_num); - acpigen_emit_byte(LOCAL0_OP); - return 0; -} - -int acpigen_soc_read_rx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_get_gpio_state("\\_SB.PCI0.GRXS", gpio_num); -} - -int acpigen_soc_get_tx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_get_gpio_state("\\_SB.PCI0.GTXS", gpio_num); -} - -int acpigen_soc_set_tx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_gpio_op("\\_SB.PCI0.STXS", gpio_num); -} - -int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_gpio_op("\\_SB.PCI0.CTXS", gpio_num); -} diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 92c2955..bf204f5 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -43,6 +43,7 @@ select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index 17d8a34..c60bcaa 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -296,40 +296,3 @@ { return MP_IRQ_POLARITY_HIGH; } - -static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num) -{ - /* op (gpio_num) */ - acpigen_emit_namestring(op); - acpigen_write_integer(gpio_num); - return 0; -} - -static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num) -{ - /* Store (op (gpio_num), Local0) */ - acpigen_write_store(); - acpigen_soc_gpio_op(op, gpio_num); - acpigen_emit_byte(LOCAL0_OP); - return 0; -} - -int acpigen_soc_read_rx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_get_gpio_state("\\_SB.PCI0.GRXS", gpio_num); -} - -int acpigen_soc_get_tx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_get_gpio_state("\\_SB.PCI0.GTXS", gpio_num); -} - -int acpigen_soc_set_tx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_gpio_op("\\_SB.PCI0.STXS", gpio_num); -} - -int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_gpio_op("\\_SB.PCI0.CTXS", gpio_num); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/50938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27f198d403f6ba05ba72ae0652da224d4cbf323a Gerrit-Change-Number: 50938 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/skylake: Clean up SD GPIO handling
by Angel Pons (Code Review) 01 Mar '21

01 Mar '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50963 ) Change subject: soc/intel/skylake: Clean up SD GPIO handling ...................................................................... soc/intel/skylake: Clean up SD GPIO handling This is to align with newer platforms. Change-Id: If33ea3a7835ec071be3fd060f9712c47678bd6bf Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50963 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/fizz/variants/fizz/overridetree.cb M src/mainboard/google/glados/variants/cave/overridetree.cb M src/mainboard/google/glados/variants/sentry/overridetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/sd.c 13 files changed, 24 insertions(+), 31 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Michael Niewöhner: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/fizz/variants/fizz/overridetree.cb b/src/mainboard/google/fizz/variants/fizz/overridetree.cb index 2b30905..3394bdf 100644 --- a/src/mainboard/google/fizz/variants/fizz/overridetree.cb +++ b/src/mainboard/google/fizz/variants/fizz/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/skylake # Use default SD card detect GPIO configuration - register "sdcard_cd_gpio_default" = "GPP_A7" + register "sdcard_cd_gpio" = "GPP_A7" device domain 0 on device pci 14.0 on diff --git a/src/mainboard/google/glados/variants/cave/overridetree.cb b/src/mainboard/google/glados/variants/cave/overridetree.cb index e77a2b4..bd3c139 100644 --- a/src/mainboard/google/glados/variants/cave/overridetree.cb +++ b/src/mainboard/google/glados/variants/cave/overridetree.cb @@ -23,7 +23,7 @@ register "tcc_offset" = "10" # Use default SD card detect GPIO configuration - register "sdcard_cd_gpio_default" = "GPP_A7" + register "sdcard_cd_gpio" = "GPP_A7" device domain 0 on device pci 15.0 on diff --git a/src/mainboard/google/glados/variants/sentry/overridetree.cb b/src/mainboard/google/glados/variants/sentry/overridetree.cb index 36575f8..28bc2fb 100644 --- a/src/mainboard/google/glados/variants/sentry/overridetree.cb +++ b/src/mainboard/google/glados/variants/sentry/overridetree.cb @@ -16,7 +16,7 @@ register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # Use default SD card detect GPIO configuration - register "sdcard_cd_gpio_default" = "GPP_A7" + register "sdcard_cd_gpio" = "GPP_A7" device domain 0 on device pci 15.0 on diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 4bfac6d..09bdac4 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -251,7 +251,7 @@ register "tcc_offset" = "10" # TCC of 90C # Use default SD card detect GPIO configuration - register "sdcard_cd_gpio_default" = "GPP_E15" + register "sdcard_cd_gpio" = "GPP_E15" device cpu_cluster 0 on device lapic 0 on end diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 9563298..6eb83ac 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -273,7 +273,7 @@ register "tcc_offset" = "10" # TCC of 90C # Use default SD card detect GPIO configuration - register "sdcard_cd_gpio_default" = "GPP_E15" + register "sdcard_cd_gpio" = "GPP_E15" device cpu_cluster 0 on device lapic 0 on end diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 162b437..05f62e7 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -232,7 +232,7 @@ register "tcc_offset" = "10" # TCC of 90C # Use default SD card detect GPIO configuration - register "sdcard_cd_gpio_default" = "GPP_E15" + register "sdcard_cd_gpio" = "GPP_E15" device cpu_cluster 0 on device lapic 0 on end diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 6a37b8a..ac8fbc9 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -252,7 +252,7 @@ register "tcc_offset" = "10" # TCC of 90C # Use default SD card detect GPIO configuration - register "sdcard_cd_gpio_default" = "GPP_E15" + register "sdcard_cd_gpio" = "GPP_E15" device cpu_cluster 0 on device lapic 0 on end diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index e649ed7..20c147c 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -150,7 +150,7 @@ # Use default SD card detect GPIO configuration - register "sdcard_cd_gpio_default" = "GPP_G5" + register "sdcard_cd_gpio" = "GPP_G5" # Lock Down register "common_soc_config" = "{ diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 115e338..a76159b 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -156,7 +156,7 @@ }" # Use default SD card detect GPIO configuration - #register "sdcard_cd_gpio_default" = "GPP_D10" + #register "sdcard_cd_gpio" = "GPP_D10" device domain 0 on device pci 17.0 on end # SATA diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 85586cb..505a598 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -156,7 +156,7 @@ register "SendVrMbxCmd" = "2" # Use default SD card detect GPIO configuration - register "sdcard_cd_gpio_default" = "GPP_A7" + register "sdcard_cd_gpio" = "GPP_A7" # Lock Down register "common_soc_config" = "{ diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 0da097f..d049db1 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -197,7 +197,7 @@ register "SendVrMbxCmd" = "2" # Use default SD card detect GPIO configuration - #register "sdcard_cd_gpio_default" = "GPP_A7" + #register "sdcard_cd_gpio" = "GPP_A7" device cpu_cluster 0 on device lapic 0 on end diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index bef0f12..99eb8e6 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -427,12 +427,9 @@ * * GpioInt (Edge, ActiveBoth, SharedAndWake, PullNone, 10000, * "\\_SB.PCI0.GPIO", 0, ResourceConsumer) - * { sdcard_cd_gpio_default } + * { sdcard_cd_gpio } */ - unsigned int sdcard_cd_gpio_default; - - /* Use custom SD card detect GPIO configuration */ - struct acpi_gpio sdcard_cd_gpio; + unsigned int sdcard_cd_gpio; /* Wake Enable Bitmap for USB2 ports */ u16 usb2_wake_enable_bitmap; diff --git a/src/soc/intel/skylake/sd.c b/src/soc/intel/skylake/sd.c index ba56182..46d3852 100644 --- a/src/soc/intel/skylake/sd.c +++ b/src/soc/intel/skylake/sd.c @@ -3,26 +3,22 @@ #include <intelblocks/sd.h> #include "chip.h" -int sd_fill_soc_gpio_info(struct acpi_gpio* gpio, const struct device *dev) +int sd_fill_soc_gpio_info(struct acpi_gpio *gpio, const struct device *dev) { config_t *config = config_of(dev); - /* Nothing to write if GPIO is not set in devicetree */ - if (!config->sdcard_cd_gpio_default && !config->sdcard_cd_gpio.pins[0]) + if (!config->sdcard_cd_gpio) return -1; - if (config->sdcard_cd_gpio_default) { - gpio->type = ACPI_GPIO_TYPE_INTERRUPT; - gpio->pull = ACPI_GPIO_PULL_NONE; - gpio->irq.mode = ACPI_IRQ_EDGE_TRIGGERED; - gpio->irq.polarity = ACPI_IRQ_ACTIVE_BOTH; - gpio->irq.shared = ACPI_IRQ_SHARED; - gpio->irq.wake = ACPI_IRQ_WAKE; - gpio->interrupt_debounce_timeout = 10000; /* 100ms */ - gpio->pin_count = 1; - gpio->pins[0] = config->sdcard_cd_gpio_default; - } else - *gpio = config->sdcard_cd_gpio; + gpio->type = ACPI_GPIO_TYPE_INTERRUPT; + gpio->pull = ACPI_GPIO_PULL_NONE; + gpio->irq.mode = ACPI_IRQ_EDGE_TRIGGERED; + gpio->irq.polarity = ACPI_IRQ_ACTIVE_BOTH; + gpio->irq.shared = ACPI_IRQ_SHARED; + gpio->irq.wake = ACPI_IRQ_WAKE; + gpio->interrupt_debounce_timeout = 10000; /* 100ms */ + gpio->pin_count = 1; + gpio->pins[0] = config->sdcard_cd_gpio; return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/50963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If33ea3a7835ec071be3fd060f9712c47678bd6bf Gerrit-Change-Number: 50963 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/skylake: Remove unused macro in cpu.h
by Angel Pons (Code Review) 01 Mar '21

01 Mar '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50962 ) Change subject: soc/intel/skylake: Remove unused macro in cpu.h ...................................................................... soc/intel/skylake: Remove unused macro in cpu.h Change-Id: I92c9c06c606215a4bd9b44b3b4b1f0acced8a252 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50962 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/skylake/include/soc/cpu.h 1 file changed, 0 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h index 473068c..29f7f32 100644 --- a/src/soc/intel/skylake/include/soc/cpu.h +++ b/src/soc/intel/skylake/include/soc/cpu.h @@ -5,9 +5,6 @@ #include <device/device.h> -/* CPU types */ -#define SKYLAKE_FAMILY_ULT 0x406e0 - /* Latency times in units of 1024ns. */ #define C_STATE_LATENCY_CONTROL_0_LIMIT 0x4e #define C_STATE_LATENCY_CONTROL_1_LIMIT 0x76 -- To view, visit https://review.coreboot.org/c/coreboot/+/50962 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92c9c06c606215a4bd9b44b3b4b1f0acced8a252 Gerrit-Change-Number: 50962 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush: Add SPDs into build
by Martin Roth (Code Review) 01 Mar '21

01 Mar '21

Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Paul Menzel, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51022 to look at the new patch set (#4). Change subject: mb/google/guybrush: Add SPDs into build ...................................................................... mb/google/guybrush: Add SPDs into build This enables the standard library method of adding SPDs to CBFS. BUG=b:178715165 TEST=Build Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I2ec94fd866409e1dfa5cb65f6960ea07cbe22f2a --- M src/mainboard/google/guybrush/Kconfig M src/mainboard/google/guybrush/Makefile.inc 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/51022/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/51022 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ec94fd866409e1dfa5cb65f6960ea07cbe22f2a Gerrit-Change-Number: 51022 Gerrit-PatchSet: 4 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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