coreboot-gerrit March 2021

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Change in coreboot[master]: mb/google/dedede/var/drawcia: Re-tune override GPIO table
by Karthik Ramasubramanian (Code Review) 01 Mar '21

01 Mar '21

Karthik Ramasubramanian has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/51153 ) Change subject: mb/google/dedede/var/drawcia: Re-tune override GPIO table ...................................................................... mb/google/dedede/var/drawcia: Re-tune override GPIO table There is going to be an upcoming board version for Drawlat/man and Drawcia. Hence update the pen detect GPIO configuration to apply for board versions 6 or 8 alone. BUG=None BRANCH=dedede TEST=Build and boot to OS in Drawcia. Change-Id: I320de9a0c37ac033f3efda74eeb8f36e34667fd4 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/drawcia/gpio.c 1 file changed, 10 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/51153/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I320de9a0c37ac033f3efda74eeb8f36e34667fd4 Gerrit-Change-Number: 51153 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skylake: Move `gspi_early_bar_init()` call
by Angel Pons (Code Review) 01 Mar '21

01 Mar '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50954 ) Change subject: soc/intel/skylake: Move `gspi_early_bar_init()` call ...................................................................... soc/intel/skylake: Move `gspi_early_bar_init()` call For consistency with newer platforms, do this in pch.c instead. Change-Id: Ie7a1d3e106553388df55044be91c7837061c42da Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50954 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/skylake/bootblock/bootblock.c M src/soc/intel/skylake/bootblock/pch.c 2 files changed, 3 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index 7b8b147..276bb48 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -2,7 +2,6 @@ #include <bootblock_common.h> #include <intelblocks/fast_spi.h> -#include <intelblocks/gspi.h> #include <intelblocks/systemagent.h> #include <intelblocks/tco.h> #include <intelblocks/uart.h> @@ -34,7 +33,6 @@ */ report_platform_info(); bootblock_pch_init(); - gspi_early_bar_init(); /* Program TCO_BASE_ADDRESS and TCO Timer Halt */ tco_configure(); diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index b15bf98..1685e43 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -5,6 +5,7 @@ #include <intelblocks/cse.h> #include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> +#include <intelblocks/gspi.h> #include <intelblocks/itss.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/p2sb.h> @@ -142,4 +143,6 @@ /* initialize Heci interface */ heci_init(HECI1_BASE_ADDRESS); + + gspi_early_bar_init(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/50954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7a1d3e106553388df55044be91c7837061c42da Gerrit-Change-Number: 50954 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel: Drop `bootblock_cpu_init()` function
by Angel Pons (Code Review) 01 Mar '21

01 Mar '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50952 ) Change subject: soc/intel: Drop `bootblock_cpu_init()` function ...................................................................... soc/intel: Drop `bootblock_cpu_init()` function Just call `fast_spi_cache_bios_region()` directly instead. Change-Id: I99f6ed4cf1a5c49b078cfd05e357c2d4c26ade45 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50952 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/bootblock/bootblock.c D src/soc/intel/alderlake/bootblock/cpu.c M src/soc/intel/alderlake/include/soc/bootblock.h M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/bootblock/bootblock.c D src/soc/intel/cannonlake/bootblock/cpu.c M src/soc/intel/cannonlake/include/soc/bootblock.h M src/soc/intel/elkhartlake/Makefile.inc M src/soc/intel/elkhartlake/bootblock/bootblock.c D src/soc/intel/elkhartlake/bootblock/cpu.c M src/soc/intel/elkhartlake/include/soc/bootblock.h M src/soc/intel/icelake/Makefile.inc M src/soc/intel/icelake/bootblock/bootblock.c D src/soc/intel/icelake/bootblock/cpu.c M src/soc/intel/icelake/include/soc/bootblock.h M src/soc/intel/jasperlake/Makefile.inc M src/soc/intel/jasperlake/bootblock/bootblock.c D src/soc/intel/jasperlake/bootblock/cpu.c M src/soc/intel/jasperlake/include/soc/bootblock.h M src/soc/intel/skylake/Makefile.inc M src/soc/intel/skylake/bootblock/bootblock.c D src/soc/intel/skylake/bootblock/cpu.c M src/soc/intel/skylake/include/soc/bootblock.h M src/soc/intel/tigerlake/Makefile.inc M src/soc/intel/tigerlake/bootblock/bootblock.c D src/soc/intel/tigerlake/bootblock/cpu.c M src/soc/intel/tigerlake/include/soc/bootblock.h 28 files changed, 14 insertions(+), 135 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index fc3d63e..bb731a1 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -15,7 +15,6 @@ all-y += uart.c bootblock-y += bootblock/bootblock.c -bootblock-y += bootblock/cpu.c bootblock-y += bootblock/pch.c bootblock-y += bootblock/report_platform.c bootblock-y += espi.c diff --git a/src/soc/intel/alderlake/bootblock/bootblock.c b/src/soc/intel/alderlake/bootblock/bootblock.c index 96e6268..b8086a4 100644 --- a/src/soc/intel/alderlake/bootblock/bootblock.c +++ b/src/soc/intel/alderlake/bootblock/bootblock.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> +#include <intelblocks/fast_spi.h> #include <intelblocks/systemagent.h> #include <intelblocks/tco.h> #include <intelblocks/uart.h> @@ -16,7 +17,7 @@ { bootblock_systemagent_early_init(); bootblock_pch_early_init(); - bootblock_cpu_init(); + fast_spi_cache_bios_region(); pch_early_iorange_init(); if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) uart_bootblock_init(); diff --git a/src/soc/intel/alderlake/bootblock/cpu.c b/src/soc/intel/alderlake/bootblock/cpu.c deleted file mode 100644 index 4225358..0000000 --- a/src/soc/intel/alderlake/bootblock/cpu.c +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * This file is created based on Intel Alder Lake Processor PCH Datasheet - * Document number: 621483 - * Chapter number: 7 - */ - -#include <intelblocks/fast_spi.h> -#include <soc/bootblock.h> - -void bootblock_cpu_init(void) -{ - /* - * Alderlake platform doesn't support booting from any other media - * than SPI flash and on IA platform SPI is memory mapped hence - * enabling temporary caching of memory-mapped spi boot media. - */ - fast_spi_cache_bios_region(); -} diff --git a/src/soc/intel/alderlake/include/soc/bootblock.h b/src/soc/intel/alderlake/include/soc/bootblock.h index 087d29f..0cf334f 100644 --- a/src/soc/intel/alderlake/include/soc/bootblock.h +++ b/src/soc/intel/alderlake/include/soc/bootblock.h @@ -4,7 +4,6 @@ #define _SOC_ALDERLAKE_BOOTBLOCK_H_ /* Bootblock pre console init programming */ -void bootblock_cpu_init(void); void bootblock_pch_early_init(void); /* Bootblock post console init programming */ diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 28b5ad0..d212d94 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -10,7 +10,6 @@ subdirs-y += ../../../cpu/intel/common bootblock-y += bootblock/bootblock.c -bootblock-y += bootblock/cpu.c bootblock-y += bootblock/pch.c bootblock-y += pmutil.c bootblock-y += bootblock/report_platform.c diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c index 255bac8..dfa0bd0 100644 --- a/src/soc/intel/cannonlake/bootblock/bootblock.c +++ b/src/soc/intel/cannonlake/bootblock/bootblock.c @@ -2,6 +2,7 @@ #include <bootblock_common.h> #include <cpu/x86/mtrr.h> +#include <intelblocks/fast_spi.h> #include <intelblocks/gspi.h> #include <intelblocks/systemagent.h> #include <intelblocks/tco.h> @@ -52,7 +53,7 @@ { bootblock_systemagent_early_init(); bootblock_pch_early_init(); - bootblock_cpu_init(); + fast_spi_cache_bios_region(); pch_early_iorange_init(); if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) uart_bootblock_init(); diff --git a/src/soc/intel/cannonlake/bootblock/cpu.c b/src/soc/intel/cannonlake/bootblock/cpu.c deleted file mode 100644 index 30c1a41..0000000 --- a/src/soc/intel/cannonlake/bootblock/cpu.c +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <intelblocks/fast_spi.h> -#include <soc/bootblock.h> - -void bootblock_cpu_init(void) -{ - /* Temporarily cache the memory-mapped boot media. */ - fast_spi_cache_bios_region(); -} diff --git a/src/soc/intel/cannonlake/include/soc/bootblock.h b/src/soc/intel/cannonlake/include/soc/bootblock.h index 6ac2bc2..dea7d47 100644 --- a/src/soc/intel/cannonlake/include/soc/bootblock.h +++ b/src/soc/intel/cannonlake/include/soc/bootblock.h @@ -4,7 +4,6 @@ #define _SOC_CANNONLAKE_BOOTBLOCK_H_ /* Bootblock pre console init programming */ -void bootblock_cpu_init(void); void bootblock_pch_early_init(void); /* Bootblock post console init programming */ diff --git a/src/soc/intel/elkhartlake/Makefile.inc b/src/soc/intel/elkhartlake/Makefile.inc index 5c46f86..371f952 100644 --- a/src/soc/intel/elkhartlake/Makefile.inc +++ b/src/soc/intel/elkhartlake/Makefile.inc @@ -16,7 +16,6 @@ all-y += uart.c bootblock-y += bootblock/bootblock.c -bootblock-y += bootblock/cpu.c bootblock-y += bootblock/pch.c bootblock-y += bootblock/report_platform.c bootblock-y += espi.c diff --git a/src/soc/intel/elkhartlake/bootblock/bootblock.c b/src/soc/intel/elkhartlake/bootblock/bootblock.c index 96e6268..b8086a4 100644 --- a/src/soc/intel/elkhartlake/bootblock/bootblock.c +++ b/src/soc/intel/elkhartlake/bootblock/bootblock.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> +#include <intelblocks/fast_spi.h> #include <intelblocks/systemagent.h> #include <intelblocks/tco.h> #include <intelblocks/uart.h> @@ -16,7 +17,7 @@ { bootblock_systemagent_early_init(); bootblock_pch_early_init(); - bootblock_cpu_init(); + fast_spi_cache_bios_region(); pch_early_iorange_init(); if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) uart_bootblock_init(); diff --git a/src/soc/intel/elkhartlake/bootblock/cpu.c b/src/soc/intel/elkhartlake/bootblock/cpu.c deleted file mode 100644 index bbce44c..0000000 --- a/src/soc/intel/elkhartlake/bootblock/cpu.c +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <intelblocks/fast_spi.h> -#include <soc/bootblock.h> - -void bootblock_cpu_init(void) -{ - /* - * Elkhartlake platform doesn't support booting from any other media - * (like eMMC on APL/GLK platform) than only booting from SPI device - * and on IA platform SPI is memory mapped hence enabling temporarily - * caching on memory-mapped spi boot media. - */ - fast_spi_cache_bios_region(); -} diff --git a/src/soc/intel/elkhartlake/include/soc/bootblock.h b/src/soc/intel/elkhartlake/include/soc/bootblock.h index 2dc50c1..1173bbe 100644 --- a/src/soc/intel/elkhartlake/include/soc/bootblock.h +++ b/src/soc/intel/elkhartlake/include/soc/bootblock.h @@ -4,7 +4,6 @@ #define _SOC_ELKHARTLAKE_BOOTBLOCK_H_ /* Bootblock pre console init programming */ -void bootblock_cpu_init(void); void bootblock_pch_early_init(void); /* Bootblock post console init programming */ diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index 05f4846..05e11f2 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -16,7 +16,6 @@ all-y += uart.c bootblock-y += bootblock/bootblock.c -bootblock-y += bootblock/cpu.c bootblock-y += bootblock/pch.c bootblock-y += bootblock/report_platform.c bootblock-y += espi.c diff --git a/src/soc/intel/icelake/bootblock/bootblock.c b/src/soc/intel/icelake/bootblock/bootblock.c index df1fb56..ef5ada6 100644 --- a/src/soc/intel/icelake/bootblock/bootblock.c +++ b/src/soc/intel/icelake/bootblock/bootblock.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> +#include <intelblocks/fast_spi.h> #include <intelblocks/systemagent.h> #include <intelblocks/tco.h> #include <intelblocks/uart.h> @@ -16,7 +17,7 @@ { bootblock_systemagent_early_init(); bootblock_pch_early_init(); - bootblock_cpu_init(); + fast_spi_cache_bios_region(); pch_early_iorange_init(); if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) uart_bootblock_init(); diff --git a/src/soc/intel/icelake/bootblock/cpu.c b/src/soc/intel/icelake/bootblock/cpu.c deleted file mode 100644 index bf5fc1b..0000000 --- a/src/soc/intel/icelake/bootblock/cpu.c +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <intelblocks/fast_spi.h> -#include <soc/bootblock.h> - -void bootblock_cpu_init(void) -{ - /* - * Icelake platform doesn't support booting from any other media - * (like eMMC on APL/GLK platform) than only booting from SPI device - * and on IA platform SPI is memory mapped hence enabling temporarily - * cacheing on memory-mapped spi boot media. - * - * This assumption will not hold good for APL/GLK platform where boot - * from eMMC is also possible options. - */ - fast_spi_cache_bios_region(); -} diff --git a/src/soc/intel/icelake/include/soc/bootblock.h b/src/soc/intel/icelake/include/soc/bootblock.h index f22b266..cdc350f 100644 --- a/src/soc/intel/icelake/include/soc/bootblock.h +++ b/src/soc/intel/icelake/include/soc/bootblock.h @@ -4,7 +4,6 @@ #define _SOC_ICELAKE_BOOTBLOCK_H_ /* Bootblock pre console init programming */ -void bootblock_cpu_init(void); void bootblock_pch_early_init(void); /* Bootblock post console init programming */ diff --git a/src/soc/intel/jasperlake/Makefile.inc b/src/soc/intel/jasperlake/Makefile.inc index 677b5f3..ccff1e0 100644 --- a/src/soc/intel/jasperlake/Makefile.inc +++ b/src/soc/intel/jasperlake/Makefile.inc @@ -16,7 +16,6 @@ all-y += uart.c bootblock-y += bootblock/bootblock.c -bootblock-y += bootblock/cpu.c bootblock-y += bootblock/pch.c bootblock-y += bootblock/report_platform.c bootblock-y += espi.c diff --git a/src/soc/intel/jasperlake/bootblock/bootblock.c b/src/soc/intel/jasperlake/bootblock/bootblock.c index 96e6268..b8086a4 100644 --- a/src/soc/intel/jasperlake/bootblock/bootblock.c +++ b/src/soc/intel/jasperlake/bootblock/bootblock.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> +#include <intelblocks/fast_spi.h> #include <intelblocks/systemagent.h> #include <intelblocks/tco.h> #include <intelblocks/uart.h> @@ -16,7 +17,7 @@ { bootblock_systemagent_early_init(); bootblock_pch_early_init(); - bootblock_cpu_init(); + fast_spi_cache_bios_region(); pch_early_iorange_init(); if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) uart_bootblock_init(); diff --git a/src/soc/intel/jasperlake/bootblock/cpu.c b/src/soc/intel/jasperlake/bootblock/cpu.c deleted file mode 100644 index 292733a..0000000 --- a/src/soc/intel/jasperlake/bootblock/cpu.c +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <intelblocks/fast_spi.h> -#include <soc/bootblock.h> - -void bootblock_cpu_init(void) -{ - /* - * Jasperlake platform doesn't support booting from any other media - * (like eMMC on APL/GLK platform) than only booting from SPI device - * and on IA platform SPI is memory mapped hence enabling temporarily - * cacheing on memory-mapped spi boot media. - * - * This assumption will not hold good for APL/GLK platform where boot - * from eMMC is also possible options. - */ - fast_spi_cache_bios_region(); -} diff --git a/src/soc/intel/jasperlake/include/soc/bootblock.h b/src/soc/intel/jasperlake/include/soc/bootblock.h index 413ae4f..678a2c4 100644 --- a/src/soc/intel/jasperlake/include/soc/bootblock.h +++ b/src/soc/intel/jasperlake/include/soc/bootblock.h @@ -4,7 +4,6 @@ #define _SOC_JASPERLAKE_BOOTBLOCK_H_ /* Bootblock pre console init programming */ -void bootblock_cpu_init(void); void bootblock_pch_early_init(void); /* Bootblock post console init programming */ diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index de516c1..1d36feb 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -11,7 +11,6 @@ subdirs-y += ../../../cpu/x86/tsc bootblock-y += bootblock/bootblock.c -bootblock-y += bootblock/cpu.c bootblock-y += i2c.c bootblock-y += bootblock/pch.c bootblock-y += bootblock/report_platform.c diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index 65c631a..7b8b147 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> +#include <intelblocks/fast_spi.h> #include <intelblocks/gspi.h> #include <intelblocks/systemagent.h> #include <intelblocks/tco.h> @@ -17,7 +18,7 @@ { bootblock_systemagent_early_init(); bootblock_pch_early_init(); - bootblock_cpu_init(); + fast_spi_cache_bios_region(); pch_early_iorange_init(); if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c deleted file mode 100644 index bf487c3..0000000 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <intelblocks/fast_spi.h> -#include <soc/bootblock.h> - -void bootblock_cpu_init(void) -{ - fast_spi_cache_bios_region(); -} diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h index 5e67735..90c4a40 100644 --- a/src/soc/intel/skylake/include/soc/bootblock.h +++ b/src/soc/intel/skylake/include/soc/bootblock.h @@ -4,7 +4,6 @@ #define _SOC_SKYLAKE_BOOTBLOCK_H_ /* Bootblock pre console init programming */ -void bootblock_cpu_init(void); void bootblock_pch_early_init(void); /* Bootblock post console init programming */ diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index f206406..baa9261 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -16,7 +16,6 @@ all-y += uart.c bootblock-y += bootblock/bootblock.c -bootblock-y += bootblock/cpu.c bootblock-y += bootblock/pch.c bootblock-y += bootblock/report_platform.c bootblock-y += espi.c diff --git a/src/soc/intel/tigerlake/bootblock/bootblock.c b/src/soc/intel/tigerlake/bootblock/bootblock.c index 96e6268..b8086a4 100644 --- a/src/soc/intel/tigerlake/bootblock/bootblock.c +++ b/src/soc/intel/tigerlake/bootblock/bootblock.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> +#include <intelblocks/fast_spi.h> #include <intelblocks/systemagent.h> #include <intelblocks/tco.h> #include <intelblocks/uart.h> @@ -16,7 +17,7 @@ { bootblock_systemagent_early_init(); bootblock_pch_early_init(); - bootblock_cpu_init(); + fast_spi_cache_bios_region(); pch_early_iorange_init(); if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) uart_bootblock_init(); diff --git a/src/soc/intel/tigerlake/bootblock/cpu.c b/src/soc/intel/tigerlake/bootblock/cpu.c deleted file mode 100644 index ed9381c..0000000 --- a/src/soc/intel/tigerlake/bootblock/cpu.c +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * This file is created based on Intel Tiger Lake Processor PCH Datasheet - * Document number: 575857 - * Chapter number: 6 - */ - -#include <intelblocks/fast_spi.h> -#include <soc/bootblock.h> - -void bootblock_cpu_init(void) -{ - /* - * Tigerlake platform doesn't support booting from any other media - * (like eMMC on APL/GLK platform) than only booting from SPI device - * and on IA platform SPI is memory mapped hence enabling temporarily - * cacheing on memory-mapped spi boot media. - * - * This assumption will not hold good for APL/GLK platform where boot - * from eMMC is also possible options. - */ - fast_spi_cache_bios_region(); -} diff --git a/src/soc/intel/tigerlake/include/soc/bootblock.h b/src/soc/intel/tigerlake/include/soc/bootblock.h index 87be0e0..71a16a5 100644 --- a/src/soc/intel/tigerlake/include/soc/bootblock.h +++ b/src/soc/intel/tigerlake/include/soc/bootblock.h @@ -4,7 +4,6 @@ #define _SOC_TIGERLAKE_BOOTBLOCK_H_ /* Bootblock pre console init programming */ -void bootblock_cpu_init(void); void bootblock_pch_early_init(void); /* Bootblock post console init programming */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99f6ed4cf1a5c49b078cfd05e357c2d4c26ade45 Gerrit-Change-Number: 50952 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/cannonlake: Drop unnecessary guard
by Angel Pons (Code Review) 01 Mar '21

01 Mar '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50951 ) Change subject: soc/intel/cannonlake: Drop unnecessary guard ...................................................................... soc/intel/cannonlake: Drop unnecessary guard The MRC cache driver assumes BOOT_DEVICE_MEMORY_MAPPED=y already. This is to ease factoring out common code across seven Intel platforms. Change-Id: I0598cb18b456e10789b2a42792fbfa2639cdd2c4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50951 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/cannonlake/bootblock/cpu.c 1 file changed, 1 insertion(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/bootblock/cpu.c b/src/soc/intel/cannonlake/bootblock/cpu.c index 5a56d29..30c1a41 100644 --- a/src/soc/intel/cannonlake/bootblock/cpu.c +++ b/src/soc/intel/cannonlake/bootblock/cpu.c @@ -6,7 +6,5 @@ void bootblock_cpu_init(void) { /* Temporarily cache the memory-mapped boot media. */ - if (CONFIG(BOOT_DEVICE_MEMORY_MAPPED) && - CONFIG(BOOT_DEVICE_SPI_FLASH)) - fast_spi_cache_bios_region(); + fast_spi_cache_bios_region(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/50951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0598cb18b456e10789b2a42792fbfa2639cdd2c4 Gerrit-Change-Number: 50951 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/{skl,cnl}: Do not chain-include systemagent.h
by Angel Pons (Code Review) 01 Mar '21

01 Mar '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50950 ) Change subject: soc/intel/{skl,cnl}: Do not chain-include systemagent.h ...................................................................... soc/intel/{skl,cnl}: Do not chain-include systemagent.h Change-Id: I8f48765ad99dad49f9d94c45aa4af6aff2ed702c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50950 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/cannonlake/bootblock/bootblock.c M src/soc/intel/cannonlake/include/soc/bootblock.h M src/soc/intel/skylake/bootblock/bootblock.c M src/soc/intel/skylake/include/soc/bootblock.h 4 files changed, 2 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c index a72b66e..255bac8 100644 --- a/src/soc/intel/cannonlake/bootblock/bootblock.c +++ b/src/soc/intel/cannonlake/bootblock/bootblock.c @@ -3,6 +3,7 @@ #include <bootblock_common.h> #include <cpu/x86/mtrr.h> #include <intelblocks/gspi.h> +#include <intelblocks/systemagent.h> #include <intelblocks/tco.h> #include <intelblocks/uart.h> #include <soc/bootblock.h> diff --git a/src/soc/intel/cannonlake/include/soc/bootblock.h b/src/soc/intel/cannonlake/include/soc/bootblock.h index b82e557..6ac2bc2 100644 --- a/src/soc/intel/cannonlake/include/soc/bootblock.h +++ b/src/soc/intel/cannonlake/include/soc/bootblock.h @@ -3,8 +3,6 @@ #ifndef _SOC_CANNONLAKE_BOOTBLOCK_H_ #define _SOC_CANNONLAKE_BOOTBLOCK_H_ -#include <intelblocks/systemagent.h> - /* Bootblock pre console init programming */ void bootblock_cpu_init(void); void bootblock_pch_early_init(void); diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index 1e5f105..65c631a 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> -#include <intelblocks/systemagent.h> #include <intelblocks/gspi.h> +#include <intelblocks/systemagent.h> #include <intelblocks/tco.h> #include <intelblocks/uart.h> #include <soc/bootblock.h> diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h index 62544de..5e67735 100644 --- a/src/soc/intel/skylake/include/soc/bootblock.h +++ b/src/soc/intel/skylake/include/soc/bootblock.h @@ -3,8 +3,6 @@ #ifndef _SOC_SKYLAKE_BOOTBLOCK_H_ #define _SOC_SKYLAKE_BOOTBLOCK_H_ -#include <intelblocks/systemagent.h> - /* Bootblock pre console init programming */ void bootblock_cpu_init(void); void bootblock_pch_early_init(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/50950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f48765ad99dad49f9d94c45aa4af6aff2ed702c Gerrit-Change-Number: 50950 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: skylake,fsp1_1: Delete dead `report_memory_config()` function
by Angel Pons (Code Review) 01 Mar '21

01 Mar '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50949 ) Change subject: skylake,fsp1_1: Delete dead `report_memory_config()` function ...................................................................... skylake,fsp1_1: Delete dead `report_memory_config()` function RAM is not yet configured in bootblock. This function was copy-pasted from Broadwell. Also, Skylake no longer uses FSP 1.1 and the stubs in there can be removed as nothing else uses them. Change-Id: I22cb7e63ed1e9565934296fd40771130ba91d227 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50949 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/intel/fsp1_1/include/fsp/romstage.h M src/drivers/intel/fsp1_1/raminit.c M src/drivers/intel/fsp1_1/romstage.c M src/soc/intel/skylake/bootblock/report_platform.c M src/soc/intel/skylake/include/soc/bootblock.h 5 files changed, 0 insertions(+), 51 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index 23eadfa..db4b352 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -34,7 +34,6 @@ struct memory_info *mem_info, int channel, int dimm, int index); void raminit(struct romstage_params *params); -void report_memory_config(void); /* Initialize memory margin analysis settings. */ void setup_mma(MEMORY_INIT_UPD *memory_upd); void soc_after_ram_init(struct romstage_params *params); diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 4c468e5..44e7693 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -237,9 +237,6 @@ die_with_post_code(POST_INVALID_VENDOR_BINARY, "ERROR - coreboot's requirements not met by FSP binary!\n"); - /* Display the memory configuration */ - report_memory_config(); - /* Locate the memory configuration data to speed up the next reboot */ mrc_hob = get_next_guid_hob(&mrc_guid, hob_list_ptr); if (mrc_hob == NULL) { diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 5129dc6..1befc47 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -291,11 +291,6 @@ return -1; } -/* Display the memory configuration */ -__weak void report_memory_config(void) -{ -} - /* SOC initialization after RAM is enabled */ __weak void soc_after_ram_init(struct romstage_params *params) { diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index 957b4c2..99b5ba1 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -241,44 +241,3 @@ report_pch_info(); report_igd_info(); } - -/* - * Dump in the log memory controller configuration as read from the memory - * controller registers. - */ -void report_memory_config(void) -{ - u32 addr_decoder_common, addr_decode_ch[2]; - int i; - - addr_decoder_common = MCHBAR32(0x5000); - addr_decode_ch[0] = MCHBAR32(0x5004); - addr_decode_ch[1] = MCHBAR32(0x5008); - - printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", - (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); - printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", - addr_decoder_common & 3, - (addr_decoder_common >> 2) & 3, - (addr_decoder_common >> 4) & 3); - - for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { - u32 ch_conf = addr_decode_ch[i]; - printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", - i, ch_conf); - printk(BIOS_DEBUG, " enhanced interleave mode %s\n", - ((ch_conf >> 22) & 1) ? "on" : "off"); - printk(BIOS_DEBUG, " rank interleave %s\n", - ((ch_conf >> 21) & 1) ? "on" : "off"); - printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n", - ((ch_conf >> 0) & 0xff) * 256, - ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", - ((ch_conf >> 17) & 1) ? "dual" : "single", - ((ch_conf >> 16) & 1) ? "" : ", selected"); - printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n", - ((ch_conf >> 8) & 0xff) * 256, - ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", - ((ch_conf >> 18) & 1) ? "dual" : "single", - ((ch_conf >> 16) & 1) ? ", selected" : ""); - } -} diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h index 6b6af36..62544de 100644 --- a/src/soc/intel/skylake/include/soc/bootblock.h +++ b/src/soc/intel/skylake/include/soc/bootblock.h @@ -13,6 +13,5 @@ void bootblock_pch_init(void); void pch_early_iorange_init(void); void report_platform_info(void); -void report_memory_config(void); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/50949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22cb7e63ed1e9565934296fd40771130ba91d227 Gerrit-Change-Number: 50949 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/drawcia: Update Pen Detect GPIO config
by Karthik Ramasubramanian (Code Review) 01 Mar '21

01 Mar '21

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51153 ) Change subject: mb/google/dedede/var/drawcia: Update Pen Detect GPIO config ...................................................................... mb/google/dedede/var/drawcia: Update Pen Detect GPIO config There is going to be an upcoming board version for Drawlat/man and Drawcia. Hence update the pen detect GPIO configuration to apply for board versions 6 or 8 alone. BUG=None BRANCH=dedede TEST=Build and boot to OS in Drawcia. Change-Id: I320de9a0c37ac033f3efda74eeb8f36e34667fd4 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/drawcia/gpio.c 1 file changed, 10 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/51153/1 diff --git a/src/mainboard/google/dedede/variants/drawcia/gpio.c b/src/mainboard/google/dedede/variants/drawcia/gpio.c index 863d289..d553949 100644 --- a/src/mainboard/google/dedede/variants/drawcia/gpio.c +++ b/src/mainboard/google/dedede/variants/drawcia/gpio.c @@ -2,18 +2,19 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> +#include <boardid.h> #include <fw_config.h> #include <ec/google/chromeec/ec.h> /* Pad configuration in ramstage*/ -static const struct pad_config pre_board6_gpio_table[] = { +static const struct pad_config not_board6or8_gpio_table[] = { /* C12 : AP_PEN_DET_ODL */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, UP_20K, DEEP), }; -/* bid6: Pad configuration for board version 6 afterward in ramstage*/ -static const struct pad_config board6_gpio_table[] = { +/* bid6: Pad configuration for board version 6 or 8 in ramstage*/ +static const struct pad_config board6or8_gpio_table[] = { /* C12 : AP_PEN_DET_ODL has an external pull-up and hence no pad termination.*/ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), @@ -21,15 +22,13 @@ const struct pad_config *variant_override_gpio_table(size_t *num) { - uint32_t board_version; - *num = ARRAY_SIZE(pre_board6_gpio_table); + uint32_t board_version = board_id(); + *num = ARRAY_SIZE(not_board6or8_gpio_table); - if (!google_chromeec_cbi_get_board_version(&board_version)) { - if (board_version >= 6) { - *num = ARRAY_SIZE(board6_gpio_table); - return board6_gpio_table; - } + if (board_version == 6 || board_version == 8) { + *num = ARRAY_SIZE(board6or8_gpio_table); + return board6or8_gpio_table; } - return pre_board6_gpio_table; + return not_board6or8_gpio_table; } -- To view, visit https://review.coreboot.org/c/coreboot/+/51153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I320de9a0c37ac033f3efda74eeb8f36e34667fd4 Gerrit-Change-Number: 51153 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: Extract fsp_params.c out of romstage.c
by Angel Pons (Code Review) 01 Mar '21

01 Mar '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50948 ) Change subject: soc/intel/skylake: Extract fsp_params.c out of romstage.c ...................................................................... soc/intel/skylake: Extract fsp_params.c out of romstage.c Done for consistency with newer platforms. Also clean up includes. Change-Id: Ib78717c6fbd49a5bd79bd564add8849ad21fa9e2 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50948 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/skylake/romstage/Makefile.inc A src/soc/intel/skylake/romstage/fsp_params.c M src/soc/intel/skylake/romstage/romstage.c 3 files changed, 192 insertions(+), 187 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc index dff89ce..cac7065 100644 --- a/src/soc/intel/skylake/romstage/Makefile.inc +++ b/src/soc/intel/skylake/romstage/Makefile.inc @@ -1,3 +1,4 @@ +romstage-y += fsp_params.c romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c romstage-y += systemagent.c diff --git a/src/soc/intel/skylake/romstage/fsp_params.c b/src/soc/intel/skylake/romstage/fsp_params.c new file mode 100644 index 0000000..2793c2d --- /dev/null +++ b/src/soc/intel/skylake/romstage/fsp_params.c @@ -0,0 +1,189 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <fsp/util.h> +#include <intelblocks/cpulib.h> +#include <soc/iomap.h> +#include <soc/msr.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> +#include <soc/soc_chip.h> + +static void cpu_flex_override(FSP_M_CONFIG *m_cfg) +{ + msr_t flex_ratio; + m_cfg->CpuRatioOverride = 1; + /* + * Set cpuratio to that value set in bootblock, This will ensure FSPM + * knows the intended flex ratio. + */ + flex_ratio = rdmsr(MSR_FLEX_RATIO); + m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; +} + +static void soc_peg_init_params(FSP_M_CONFIG *m_cfg, + FSP_M_TEST_CONFIG *m_t_cfg, + const struct soc_intel_skylake_config *config) +{ + const struct device *dev; + /* + * To enable or disable the corresponding PEG root port you need to + * add to the devicetree.cb: + * + * device pci 01.0 on end # enable PEG0 root port + * device pci 01.1 off end # do not configure PEG1 + * + * If PEG port is not defined in the device tree, it will be disabled + * in FSP + */ + dev = pcidev_path_on_root(SA_DEVFN_PEG0); /* PEG 0:1:0 */ + m_cfg->Peg0Enable = dev && dev->enabled; + if (m_cfg->Peg0Enable) { + m_cfg->Peg0Enable = 2; + m_cfg->Peg0MaxLinkWidth = config->Peg0MaxLinkWidth; + /* Use maximum possible link speed */ + m_cfg->Peg0MaxLinkSpeed = 0; + /* Power down unused lanes based on the max possible width */ + m_cfg->Peg0PowerDownUnusedLanes = 1; + /* Set [Auto] for options to enable equalization methods */ + m_t_cfg->Peg0Gen3EqPh2Enable = 2; + m_t_cfg->Peg0Gen3EqPh3Method = 0; + } + + dev = pcidev_path_on_root(SA_DEVFN_PEG1); /* PEG 0:1:1 */ + m_cfg->Peg1Enable = dev && dev->enabled; + if (m_cfg->Peg1Enable) { + m_cfg->Peg1Enable = 2; + m_cfg->Peg1MaxLinkWidth = config->Peg1MaxLinkWidth; + m_cfg->Peg1MaxLinkSpeed = 0; + m_cfg->Peg1PowerDownUnusedLanes = 1; + m_t_cfg->Peg1Gen3EqPh2Enable = 2; + m_t_cfg->Peg1Gen3EqPh3Method = 0; + } + + dev = pcidev_path_on_root(SA_DEVFN_PEG2); /* PEG 0:1:2 */ + m_cfg->Peg2Enable = dev && dev->enabled; + if (m_cfg->Peg2Enable) { + m_cfg->Peg2Enable = 2; + m_cfg->Peg2MaxLinkWidth = config->Peg2MaxLinkWidth; + m_cfg->Peg2MaxLinkSpeed = 0; + m_cfg->Peg2PowerDownUnusedLanes = 1; + m_t_cfg->Peg2Gen3EqPh2Enable = 2; + m_t_cfg->Peg2Gen3EqPh3Method = 0; + } +} + +static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_skylake_config *config) +{ + int i; + uint32_t mask = 0; + + m_cfg->MmioSize = 0x800; /* 2GB in MB */ + m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; + m_cfg->IedSize = CONFIG_IED_REGION_SIZE; + m_cfg->ProbelessTrace = 0; + m_cfg->SaGv = config->SaGv; + m_cfg->UserBd = BOARD_TYPE_ULT_ULX; + m_cfg->RMT = config->Rmt; + m_cfg->CmdTriStateDis = config->CmdTriStateDis; + m_cfg->DdrFreqLimit = 0; + m_cfg->VmxEnable = CONFIG(ENABLE_VMX); + m_cfg->PrmrrSize = get_valid_prmrr_size(); + for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { + if (config->PcieRpEnable[i]) + mask |= (1<<i); + } + m_cfg->PcieRpEnableMask = mask; + + cpu_flex_override(m_cfg); + + /* HPET BDF already handled in coreboot code, so tell FSP to ignore UPDs */ + m_cfg->PchHpetBdfValid = 0; + + m_cfg->HyperThreading = CONFIG(FSP_HYPERTHREADING); +} + +static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_skylake_config *config) +{ + const struct device *dev; + + dev = pcidev_path_on_root(SA_DEVFN_IGD); + m_cfg->InternalGfx = dev && dev->enabled; + + /* + * If iGPU is enabled, set IGD stolen size to 64MB. The FBC + * hardware for skylake does not have access to the bios + * reserved range so it always assumes 8MB is used and so the + * kernel will avoid the last 8MB of the stolen window. With + * the default stolen size of 32MB(-8MB) there is not enough + * space for FBC to work with a high resolution panel. + * + * If disabled, don't reserve memory for it. + */ + m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? 2 : 0; + + m_cfg->PrimaryDisplay = config->PrimaryDisplay; +} + +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ + const struct soc_intel_skylake_config *config; + const struct device *dev; + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig; + + config = config_of_soc(); + + soc_memory_init_params(m_cfg, config); + soc_peg_init_params(m_cfg, m_t_cfg, config); + + /* Skip creating Management Engine MBP HOB */ + m_t_cfg->SkipMbpHob = 0x01; + + /* Enable DMI Virtual Channel for ME */ + m_t_cfg->DmiVcm = 0x01; + + /* Enable Sending DID to ME */ + m_t_cfg->SendDidMsg = 0x01; + m_t_cfg->DidInitStat = 0x01; + + /* DCI and TraceHub configs */ + m_t_cfg->PchDciEn = config->PchDciEn; + + dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB); + m_cfg->EnableTraceHub = dev && dev->enabled; + m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size; + m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size; + + /* Enable SMBus controller */ + dev = pcidev_path_on_root(PCH_DEVFN_SMBUS); + m_cfg->SmbusEnable = dev && dev->enabled; + + /* Set primary graphic device */ + soc_primary_gfx_config_params(m_cfg, config); + m_t_cfg->SkipExtGfxScan = config->SkipExtGfxScan; + + mainboard_memory_init_params(mupd); +} + +void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg, + struct mma_config_param *mma_cfg) +{ + /* Boot media is memory mapped for Skylake and Kabylake (SPI). */ + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); + + memory_cfg->MmaTestContentPtr = + (uintptr_t) rdev_mmap_full(&mma_cfg->test_content); + memory_cfg->MmaTestContentSize = + region_device_sz(&mma_cfg->test_content); + memory_cfg->MmaTestConfigPtr = + (uintptr_t) rdev_mmap_full(&mma_cfg->test_param); + memory_cfg->MmaTestConfigSize = + region_device_sz(&mma_cfg->test_param); + memory_cfg->MrcFastBoot = 0x00; + memory_cfg->SaGv = 0x02; +} diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 97d21b2..30f65ea 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -1,28 +1,20 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/romstage.h> -#include <arch/symbols.h> -#include <assert.h> -#include <cpu/x86/msr.h> #include <cbmem.h> #include <console/console.h> -#include <device/pci_def.h> #include <fsp/util.h> -#include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> #include <intelblocks/smbus.h> #include <memory_info.h> #include <smbios.h> #include <soc/intel/common/smbios.h> -#include <soc/msr.h> +#include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/romstage.h> -#include <soc/systemagent.h> +#include <soc/soc_chip.h> #include <string.h> -#include <security/vboot/vboot_common.h> - -#include "../chip.h" #define FSP_SMBIOS_MEMORY_INFO_GUID \ { \ @@ -142,180 +134,3 @@ if (!s3wake) save_dimm_info(); } - -static void cpu_flex_override(FSP_M_CONFIG *m_cfg) -{ - msr_t flex_ratio; - m_cfg->CpuRatioOverride = 1; - /* - * Set cpuratio to that value set in bootblock, This will ensure FSPM - * knows the intended flex ratio. - */ - flex_ratio = rdmsr(MSR_FLEX_RATIO); - m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; -} - -static void soc_peg_init_params(FSP_M_CONFIG *m_cfg, - FSP_M_TEST_CONFIG *m_t_cfg, - const struct soc_intel_skylake_config *config) -{ - const struct device *dev; - /* - * To enable or disable the corresponding PEG root port you need to - * add to the devicetree.cb: - * - * device pci 01.0 on end # enable PEG0 root port - * device pci 01.1 off end # do not configure PEG1 - * - * If PEG port is not defined in the device tree, it will be disabled - * in FSP - */ - dev = pcidev_path_on_root(SA_DEVFN_PEG0); /* PEG 0:1:0 */ - m_cfg->Peg0Enable = dev && dev->enabled; - if (m_cfg->Peg0Enable) { - m_cfg->Peg0Enable = 2; - m_cfg->Peg0MaxLinkWidth = config->Peg0MaxLinkWidth; - /* Use maximum possible link speed */ - m_cfg->Peg0MaxLinkSpeed = 0; - /* Power down unused lanes based on the max possible width */ - m_cfg->Peg0PowerDownUnusedLanes = 1; - /* Set [Auto] for options to enable equalization methods */ - m_t_cfg->Peg0Gen3EqPh2Enable = 2; - m_t_cfg->Peg0Gen3EqPh3Method = 0; - } - - dev = pcidev_path_on_root(SA_DEVFN_PEG1); /* PEG 0:1:1 */ - m_cfg->Peg1Enable = dev && dev->enabled; - if (m_cfg->Peg1Enable) { - m_cfg->Peg1Enable = 2; - m_cfg->Peg1MaxLinkWidth = config->Peg1MaxLinkWidth; - m_cfg->Peg1MaxLinkSpeed = 0; - m_cfg->Peg1PowerDownUnusedLanes = 1; - m_t_cfg->Peg1Gen3EqPh2Enable = 2; - m_t_cfg->Peg1Gen3EqPh3Method = 0; - } - - dev = pcidev_path_on_root(SA_DEVFN_PEG2); /* PEG 0:1:2 */ - m_cfg->Peg2Enable = dev && dev->enabled; - if (m_cfg->Peg2Enable) { - m_cfg->Peg2Enable = 2; - m_cfg->Peg2MaxLinkWidth = config->Peg2MaxLinkWidth; - m_cfg->Peg2MaxLinkSpeed = 0; - m_cfg->Peg2PowerDownUnusedLanes = 1; - m_t_cfg->Peg2Gen3EqPh2Enable = 2; - m_t_cfg->Peg2Gen3EqPh3Method = 0; - } -} - -static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, - const struct soc_intel_skylake_config *config) -{ - int i; - uint32_t mask = 0; - - m_cfg->MmioSize = 0x800; /* 2GB in MB */ - m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; - m_cfg->IedSize = CONFIG_IED_REGION_SIZE; - m_cfg->ProbelessTrace = 0; - m_cfg->SaGv = config->SaGv; - m_cfg->UserBd = BOARD_TYPE_ULT_ULX; - m_cfg->RMT = config->Rmt; - m_cfg->CmdTriStateDis = config->CmdTriStateDis; - m_cfg->DdrFreqLimit = 0; - m_cfg->VmxEnable = CONFIG(ENABLE_VMX); - m_cfg->PrmrrSize = get_valid_prmrr_size(); - for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { - if (config->PcieRpEnable[i]) - mask |= (1<<i); - } - m_cfg->PcieRpEnableMask = mask; - - cpu_flex_override(m_cfg); - - /* HPET BDF already handled in coreboot code, so tell FSP to ignore UPDs */ - m_cfg->PchHpetBdfValid = 0; - - m_cfg->HyperThreading = CONFIG(FSP_HYPERTHREADING); -} - -static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg, - const struct soc_intel_skylake_config *config) -{ - const struct device *dev; - - dev = pcidev_path_on_root(SA_DEVFN_IGD); - m_cfg->InternalGfx = dev && dev->enabled; - - /* - * If iGPU is enabled, set IGD stolen size to 64MB. The FBC - * hardware for skylake does not have access to the bios - * reserved range so it always assumes 8MB is used and so the - * kernel will avoid the last 8MB of the stolen window. With - * the default stolen size of 32MB(-8MB) there is not enough - * space for FBC to work with a high resolution panel. - * - * If disabled, don't reserve memory for it. - */ - m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? 2 : 0; - - m_cfg->PrimaryDisplay = config->PrimaryDisplay; -} - -void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -{ - const struct soc_intel_skylake_config *config; - const struct device *dev; - FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig; - - config = config_of_soc(); - - soc_memory_init_params(m_cfg, config); - soc_peg_init_params(m_cfg, m_t_cfg, config); - - /* Skip creating Management Engine MBP HOB */ - m_t_cfg->SkipMbpHob = 0x01; - - /* Enable DMI Virtual Channel for ME */ - m_t_cfg->DmiVcm = 0x01; - - /* Enable Sending DID to ME */ - m_t_cfg->SendDidMsg = 0x01; - m_t_cfg->DidInitStat = 0x01; - - /* DCI and TraceHub configs */ - m_t_cfg->PchDciEn = config->PchDciEn; - - dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB); - m_cfg->EnableTraceHub = dev && dev->enabled; - m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size; - m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size; - - /* Enable SMBus controller */ - dev = pcidev_path_on_root(PCH_DEVFN_SMBUS); - m_cfg->SmbusEnable = dev && dev->enabled; - - /* Set primary graphic device */ - soc_primary_gfx_config_params(m_cfg, config); - m_t_cfg->SkipExtGfxScan = config->SkipExtGfxScan; - - mainboard_memory_init_params(mupd); -} - -void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg, - struct mma_config_param *mma_cfg) -{ - /* Boot media is memory mapped for Skylake and Kabylake (SPI). */ - assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); - - memory_cfg->MmaTestContentPtr = - (uintptr_t) rdev_mmap_full(&mma_cfg->test_content); - memory_cfg->MmaTestContentSize = - region_device_sz(&mma_cfg->test_content); - memory_cfg->MmaTestConfigPtr = - (uintptr_t) rdev_mmap_full(&mma_cfg->test_param); - memory_cfg->MmaTestConfigSize = - region_device_sz(&mma_cfg->test_param); - memory_cfg->MrcFastBoot = 0x00; - memory_cfg->SaGv = 0x02; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/50948 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib78717c6fbd49a5bd79bd564add8849ad21fa9e2 Gerrit-Change-Number: 50948 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel: Drop `romstage_pch_init()` function
by Angel Pons (Code Review) 01 Mar '21

01 Mar '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50947 ) Change subject: soc/intel: Drop `romstage_pch_init()` function ...................................................................... soc/intel: Drop `romstage_pch_init()` function It only calls `smbus_common_init()`, so just call that directly. Change-Id: I0237f52bb9b0503e83f5dbf31c4064bd0f5bae28 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50947 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/include/soc/romstage.h M src/soc/intel/alderlake/romstage/Makefile.inc D src/soc/intel/alderlake/romstage/pch.c M src/soc/intel/alderlake/romstage/romstage.c M src/soc/intel/cannonlake/include/soc/romstage.h M src/soc/intel/cannonlake/romstage/Makefile.inc D src/soc/intel/cannonlake/romstage/pch.c M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/elkhartlake/include/soc/romstage.h M src/soc/intel/elkhartlake/romstage/Makefile.inc D src/soc/intel/elkhartlake/romstage/pch.c M src/soc/intel/elkhartlake/romstage/romstage.c M src/soc/intel/icelake/include/soc/romstage.h M src/soc/intel/icelake/romstage/Makefile.inc D src/soc/intel/icelake/romstage/pch.c M src/soc/intel/icelake/romstage/romstage.c M src/soc/intel/jasperlake/include/soc/romstage.h M src/soc/intel/jasperlake/romstage/Makefile.inc D src/soc/intel/jasperlake/romstage/pch.c M src/soc/intel/jasperlake/romstage/romstage.c M src/soc/intel/skylake/include/soc/romstage.h M src/soc/intel/skylake/romstage/Makefile.inc D src/soc/intel/skylake/romstage/pch.c M src/soc/intel/skylake/romstage/romstage.c M src/soc/intel/tigerlake/include/soc/romstage.h M src/soc/intel/tigerlake/romstage/Makefile.inc D src/soc/intel/tigerlake/romstage/pch.c M src/soc/intel/tigerlake/romstage/romstage.c 28 files changed, 21 insertions(+), 98 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/alderlake/include/soc/romstage.h b/src/soc/intel/alderlake/include/soc/romstage.h index c72c8aa..13a5b5f 100644 --- a/src/soc/intel/alderlake/include/soc/romstage.h +++ b/src/soc/intel/alderlake/include/soc/romstage.h @@ -8,7 +8,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); -void romstage_pch_init(void); /* Board type */ enum board_type { diff --git a/src/soc/intel/alderlake/romstage/Makefile.inc b/src/soc/intel/alderlake/romstage/Makefile.inc index a1a6c66..99c1d2c 100644 --- a/src/soc/intel/alderlake/romstage/Makefile.inc +++ b/src/soc/intel/alderlake/romstage/Makefile.inc @@ -3,5 +3,4 @@ romstage-y += fsp_params.c romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c -romstage-y += pch.c romstage-y += systemagent.c diff --git a/src/soc/intel/alderlake/romstage/pch.c b/src/soc/intel/alderlake/romstage/pch.c deleted file mode 100644 index bec6150..0000000 --- a/src/soc/intel/alderlake/romstage/pch.c +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <intelblocks/smbus.h> -#include <soc/romstage.h> - -void romstage_pch_init(void) -{ - /* Program SMBus base address and enable it */ - smbus_common_init(); -} diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index 6cd22d0..cc3126b 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -7,6 +7,7 @@ #include <intelblocks/cfg.h> #include <intelblocks/cse.h> #include <intelblocks/pmclib.h> +#include <intelblocks/smbus.h> #include <memory_info.h> #include <soc/intel/common/smbios.h> #include <soc/iomap.h> @@ -120,8 +121,8 @@ /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); - /* Perform PCH init */ - romstage_pch_init(); + /* Program SMBus base address and enable it */ + smbus_common_init(); /* Initialize HECI interface */ heci_init(HECI1_BASE_ADDRESS); diff --git a/src/soc/intel/cannonlake/include/soc/romstage.h b/src/soc/intel/cannonlake/include/soc/romstage.h index 3772db4..ba44f2d 100644 --- a/src/soc/intel/cannonlake/include/soc/romstage.h +++ b/src/soc/intel/cannonlake/include/soc/romstage.h @@ -7,7 +7,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); -void romstage_pch_init(void); /* Board type */ enum board_type { diff --git a/src/soc/intel/cannonlake/romstage/Makefile.inc b/src/soc/intel/cannonlake/romstage/Makefile.inc index 261e5b3..3db9190 100644 --- a/src/soc/intel/cannonlake/romstage/Makefile.inc +++ b/src/soc/intel/cannonlake/romstage/Makefile.inc @@ -4,4 +4,3 @@ romstage-y += romstage.c romstage-y += fsp_params.c romstage-y += systemagent.c -romstage-y += pch.c diff --git a/src/soc/intel/cannonlake/romstage/pch.c b/src/soc/intel/cannonlake/romstage/pch.c deleted file mode 100644 index f94d611a..0000000 --- a/src/soc/intel/cannonlake/romstage/pch.c +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <intelblocks/smbus.h> -#include <soc/romstage.h> - -void romstage_pch_init(void) -{ - /* Program SMBUS_BASE_ADDRESS and enable it */ - smbus_common_init(); -} diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 0bf0404..a83cf61 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -7,6 +7,7 @@ #include <intelblocks/cfg.h> #include <intelblocks/cse.h> #include <intelblocks/pmclib.h> +#include <intelblocks/smbus.h> #include <memory_info.h> #include <soc/intel/common/smbios.h> #include <soc/iomap.h> @@ -121,8 +122,8 @@ /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); - /* Program PCH init */ - romstage_pch_init(); + /* Program SMBus base address and enable it */ + smbus_common_init(); /* initialize Heci interface */ heci_init(HECI1_BASE_ADDRESS); diff --git a/src/soc/intel/elkhartlake/include/soc/romstage.h b/src/soc/intel/elkhartlake/include/soc/romstage.h index 3772db4..ba44f2d 100644 --- a/src/soc/intel/elkhartlake/include/soc/romstage.h +++ b/src/soc/intel/elkhartlake/include/soc/romstage.h @@ -7,7 +7,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); -void romstage_pch_init(void); /* Board type */ enum board_type { diff --git a/src/soc/intel/elkhartlake/romstage/Makefile.inc b/src/soc/intel/elkhartlake/romstage/Makefile.inc index a1a6c66..99c1d2c 100644 --- a/src/soc/intel/elkhartlake/romstage/Makefile.inc +++ b/src/soc/intel/elkhartlake/romstage/Makefile.inc @@ -3,5 +3,4 @@ romstage-y += fsp_params.c romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c -romstage-y += pch.c romstage-y += systemagent.c diff --git a/src/soc/intel/elkhartlake/romstage/pch.c b/src/soc/intel/elkhartlake/romstage/pch.c deleted file mode 100644 index d3c2554..0000000 --- a/src/soc/intel/elkhartlake/romstage/pch.c +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <intelblocks/smbus.h> -#include <soc/romstage.h> - -void romstage_pch_init(void) -{ - /* Program SMBUS_BASE_ADDRESS and Enable it */ - smbus_common_init(); -} diff --git a/src/soc/intel/elkhartlake/romstage/romstage.c b/src/soc/intel/elkhartlake/romstage/romstage.c index 7ca0318..ecbdd97 100644 --- a/src/soc/intel/elkhartlake/romstage/romstage.c +++ b/src/soc/intel/elkhartlake/romstage/romstage.c @@ -7,6 +7,7 @@ #include <intelblocks/cfg.h> #include <intelblocks/cse.h> #include <intelblocks/pmclib.h> +#include <intelblocks/smbus.h> #include <memory_info.h> #include <soc/intel/common/smbios.h> #include <soc/iomap.h> @@ -127,8 +128,8 @@ /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); - /* Program PCH init */ - romstage_pch_init(); + /* Program SMBus base address and enable it */ + smbus_common_init(); /* initialize Heci interface */ heci_init(HECI1_BASE_ADDRESS); diff --git a/src/soc/intel/icelake/include/soc/romstage.h b/src/soc/intel/icelake/include/soc/romstage.h index 3772db4..ba44f2d 100644 --- a/src/soc/intel/icelake/include/soc/romstage.h +++ b/src/soc/intel/icelake/include/soc/romstage.h @@ -7,7 +7,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); -void romstage_pch_init(void); /* Board type */ enum board_type { diff --git a/src/soc/intel/icelake/romstage/Makefile.inc b/src/soc/intel/icelake/romstage/Makefile.inc index a1a6c66..99c1d2c 100644 --- a/src/soc/intel/icelake/romstage/Makefile.inc +++ b/src/soc/intel/icelake/romstage/Makefile.inc @@ -3,5 +3,4 @@ romstage-y += fsp_params.c romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c -romstage-y += pch.c romstage-y += systemagent.c diff --git a/src/soc/intel/icelake/romstage/pch.c b/src/soc/intel/icelake/romstage/pch.c deleted file mode 100644 index d3c2554..0000000 --- a/src/soc/intel/icelake/romstage/pch.c +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <intelblocks/smbus.h> -#include <soc/romstage.h> - -void romstage_pch_init(void) -{ - /* Program SMBUS_BASE_ADDRESS and Enable it */ - smbus_common_init(); -} diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 1517974..1dc618c 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -7,6 +7,7 @@ #include <intelblocks/cfg.h> #include <intelblocks/cse.h> #include <intelblocks/pmclib.h> +#include <intelblocks/smbus.h> #include <memory_info.h> #include <soc/intel/common/smbios.h> #include <soc/iomap.h> @@ -110,8 +111,8 @@ /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); - /* Program PCH init */ - romstage_pch_init(); + /* Program SMBus base address and enable it */ + smbus_common_init(); /* initialize Heci interface */ heci_init(HECI1_BASE_ADDRESS); diff --git a/src/soc/intel/jasperlake/include/soc/romstage.h b/src/soc/intel/jasperlake/include/soc/romstage.h index 3772db4..ba44f2d 100644 --- a/src/soc/intel/jasperlake/include/soc/romstage.h +++ b/src/soc/intel/jasperlake/include/soc/romstage.h @@ -7,7 +7,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); -void romstage_pch_init(void); /* Board type */ enum board_type { diff --git a/src/soc/intel/jasperlake/romstage/Makefile.inc b/src/soc/intel/jasperlake/romstage/Makefile.inc index a1a6c66..99c1d2c 100644 --- a/src/soc/intel/jasperlake/romstage/Makefile.inc +++ b/src/soc/intel/jasperlake/romstage/Makefile.inc @@ -3,5 +3,4 @@ romstage-y += fsp_params.c romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c -romstage-y += pch.c romstage-y += systemagent.c diff --git a/src/soc/intel/jasperlake/romstage/pch.c b/src/soc/intel/jasperlake/romstage/pch.c deleted file mode 100644 index d3c2554..0000000 --- a/src/soc/intel/jasperlake/romstage/pch.c +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <intelblocks/smbus.h> -#include <soc/romstage.h> - -void romstage_pch_init(void) -{ - /* Program SMBUS_BASE_ADDRESS and Enable it */ - smbus_common_init(); -} diff --git a/src/soc/intel/jasperlake/romstage/romstage.c b/src/soc/intel/jasperlake/romstage/romstage.c index 6d34b43..f7e6a91 100644 --- a/src/soc/intel/jasperlake/romstage/romstage.c +++ b/src/soc/intel/jasperlake/romstage/romstage.c @@ -7,6 +7,7 @@ #include <intelblocks/cfg.h> #include <intelblocks/cse.h> #include <intelblocks/pmclib.h> +#include <intelblocks/smbus.h> #include <memory_info.h> #include <soc/intel/common/smbios.h> #include <soc/iomap.h> @@ -127,8 +128,8 @@ /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); - /* Program PCH init */ - romstage_pch_init(); + /* Program SMBus base address and enable it */ + smbus_common_init(); /* initialize Heci interface */ heci_init(HECI1_BASE_ADDRESS); diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h index 3772db4..ba44f2d 100644 --- a/src/soc/intel/skylake/include/soc/romstage.h +++ b/src/soc/intel/skylake/include/soc/romstage.h @@ -7,7 +7,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); -void romstage_pch_init(void); /* Board type */ enum board_type { diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc index 1b069b6..dff89ce 100644 --- a/src/soc/intel/skylake/romstage/Makefile.inc +++ b/src/soc/intel/skylake/romstage/Makefile.inc @@ -1,4 +1,3 @@ romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c romstage-y += systemagent.c -romstage-y += pch.c diff --git a/src/soc/intel/skylake/romstage/pch.c b/src/soc/intel/skylake/romstage/pch.c deleted file mode 100644 index f94d611a..0000000 --- a/src/soc/intel/skylake/romstage/pch.c +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <intelblocks/smbus.h> -#include <soc/romstage.h> - -void romstage_pch_init(void) -{ - /* Program SMBUS_BASE_ADDRESS and enable it */ - smbus_common_init(); -} diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index a20f279..97d21b2 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -10,6 +10,7 @@ #include <fsp/util.h> #include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> +#include <intelblocks/smbus.h> #include <memory_info.h> #include <smbios.h> #include <soc/intel/common/smbios.h> @@ -132,8 +133,8 @@ /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); - /* Program PCH init */ - romstage_pch_init(); + /* Program SMBus base address and enable it */ + smbus_common_init(); ps = pmc_get_power_state(); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); diff --git a/src/soc/intel/tigerlake/include/soc/romstage.h b/src/soc/intel/tigerlake/include/soc/romstage.h index 3772db4..ba44f2d 100644 --- a/src/soc/intel/tigerlake/include/soc/romstage.h +++ b/src/soc/intel/tigerlake/include/soc/romstage.h @@ -7,7 +7,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); -void romstage_pch_init(void); /* Board type */ enum board_type { diff --git a/src/soc/intel/tigerlake/romstage/Makefile.inc b/src/soc/intel/tigerlake/romstage/Makefile.inc index a1a6c66..99c1d2c 100644 --- a/src/soc/intel/tigerlake/romstage/Makefile.inc +++ b/src/soc/intel/tigerlake/romstage/Makefile.inc @@ -3,5 +3,4 @@ romstage-y += fsp_params.c romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c -romstage-y += pch.c romstage-y += systemagent.c diff --git a/src/soc/intel/tigerlake/romstage/pch.c b/src/soc/intel/tigerlake/romstage/pch.c deleted file mode 100644 index d3c2554..0000000 --- a/src/soc/intel/tigerlake/romstage/pch.c +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <intelblocks/smbus.h> -#include <soc/romstage.h> - -void romstage_pch_init(void) -{ - /* Program SMBUS_BASE_ADDRESS and Enable it */ - smbus_common_init(); -} diff --git a/src/soc/intel/tigerlake/romstage/romstage.c b/src/soc/intel/tigerlake/romstage/romstage.c index 8b7dc23..872cca5 100644 --- a/src/soc/intel/tigerlake/romstage/romstage.c +++ b/src/soc/intel/tigerlake/romstage/romstage.c @@ -7,6 +7,7 @@ #include <intelblocks/cfg.h> #include <intelblocks/cse.h> #include <intelblocks/pmclib.h> +#include <intelblocks/smbus.h> #include <memory_info.h> #include <soc/intel/common/smbios.h> #include <soc/iomap.h> @@ -127,8 +128,8 @@ /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); - /* Program PCH init */ - romstage_pch_init(); + /* Program SMBus base address and enable it */ + smbus_common_init(); /* initialize Heci interface */ heci_init(HECI1_BASE_ADDRESS); -- To view, visit https://review.coreboot.org/c/coreboot/+/50947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0237f52bb9b0503e83f5dbf31c4064bd0f5bae28 Gerrit-Change-Number: 50947 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/{skl,icl}: Move tco_configure() to bootblock
by Angel Pons (Code Review) 01 Mar '21

01 Mar '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50946 ) Change subject: soc/intel/{skl,icl}: Move tco_configure() to bootblock ...................................................................... soc/intel/{skl,icl}: Move tco_configure() to bootblock Backport commit 03ed5bff5c (soc/intel/cannonlake: Move tco_configure to bootblock), commit bb50c67227 (soc/intel/tigerlake: Move tco_configure to bootblock) and commit 60c619f6a3 (soc/intel/jasperlake: Move tco_configure to bootblock) to other platforms. This is for consistency. Change-Id: I31fd0ceb67eacf30aefa457d757bf0d7f4cd7e87 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50946 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/icelake/bootblock/bootblock.c M src/soc/intel/icelake/romstage/pch.c M src/soc/intel/skylake/bootblock/bootblock.c M src/soc/intel/skylake/romstage/pch.c 4 files changed, 8 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/icelake/bootblock/bootblock.c b/src/soc/intel/icelake/bootblock/bootblock.c index 9f360da..df1fb56 100644 --- a/src/soc/intel/icelake/bootblock/bootblock.c +++ b/src/soc/intel/icelake/bootblock/bootblock.c @@ -2,6 +2,7 @@ #include <bootblock_common.h> #include <intelblocks/systemagent.h> +#include <intelblocks/tco.h> #include <intelblocks/uart.h> #include <soc/bootblock.h> @@ -25,4 +26,7 @@ { report_platform_info(); bootblock_pch_init(); + + /* Program TCO_BASE_ADDRESS and TCO Timer Halt */ + tco_configure(); } diff --git a/src/soc/intel/icelake/romstage/pch.c b/src/soc/intel/icelake/romstage/pch.c index 6b134c0..d3c2554 100644 --- a/src/soc/intel/icelake/romstage/pch.c +++ b/src/soc/intel/icelake/romstage/pch.c @@ -1,14 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <intelblocks/smbus.h> -#include <intelblocks/tco.h> #include <soc/romstage.h> void romstage_pch_init(void) { - /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ - tco_configure(); - /* Program SMBUS_BASE_ADDRESS and Enable it */ smbus_common_init(); } diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index 6380db2..1e5f105 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -3,6 +3,7 @@ #include <bootblock_common.h> #include <intelblocks/systemagent.h> #include <intelblocks/gspi.h> +#include <intelblocks/tco.h> #include <intelblocks/uart.h> #include <soc/bootblock.h> @@ -33,4 +34,7 @@ report_platform_info(); bootblock_pch_init(); gspi_early_bar_init(); + + /* Program TCO_BASE_ADDRESS and TCO Timer Halt */ + tco_configure(); } diff --git a/src/soc/intel/skylake/romstage/pch.c b/src/soc/intel/skylake/romstage/pch.c index c85bdd6..f94d611a 100644 --- a/src/soc/intel/skylake/romstage/pch.c +++ b/src/soc/intel/skylake/romstage/pch.c @@ -1,14 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <intelblocks/smbus.h> -#include <intelblocks/tco.h> #include <soc/romstage.h> void romstage_pch_init(void) { - /* Program TCO_BASE_ADDRESS and TCO Timer Halt */ - tco_configure(); - /* Program SMBUS_BASE_ADDRESS and enable it */ smbus_common_init(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/50946 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31fd0ceb67eacf30aefa457d757bf0d7f4cd7e87 Gerrit-Change-Number: 50946 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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