Attention is currently required from: Damien Zammit.
Hello Damien Zammit, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/51150
to look at the new patch set (#3).
Change subject: mb/{intel/d510mo,foxconn/d14s}/devicetree.cb: Remove PEG device
......................................................................
mb/{intel/d510mo,foxconn/d14s}/devicetree.cb: Remove PEG device
Pineview does not support PEG.
Change-Id: Ib0006dbd54e6f2031b97ed11ce61407ffcfa6244
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/foxconn/d41s/devicetree.cb
M src/mainboard/intel/d510mo/devicetree.cb
2 files changed, 0 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/51150/3
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Gerrit-Change-Id: Ib0006dbd54e6f2031b97ed11ce61407ffcfa6244
Gerrit-Change-Number: 51150
Gerrit-PatchSet: 3
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
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Attention is currently required from: Damien Zammit, Arthur Heymans.
Hello Damien Zammit, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/51149
to look at the new patch set (#3).
Change subject: mb/intel/d510/devicetree.cb: Indent with tabs
......................................................................
mb/intel/d510/devicetree.cb: Indent with tabs
This is a cosmetic change.
Make the formatting consistent with the rest of the tree.
Change-Id: Ic90e5584938592f1c2ab41edfcc773702822070d
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/intel/d510mo/devicetree.cb
1 file changed, 94 insertions(+), 94 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/51149/3
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/51133 )
Change subject: Add support to switch LSPCON modes
......................................................................
Set Ready For Review
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51045 )
Change subject: soc/amd/cezanne: Fill out pci devices in chipset.cb
......................................................................
Patch Set 9: Code-Review+2
(1 comment)
Patchset:
PS9:
> The PPR shows […]
from chapter 1 (processor overview) of the ppr: "Two SATA controllers supporting x2 lanes of SATA Gen1/Gen2/Gen3". i'm ok with doing that in a separate patch, since it's not used at the moment anyway
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