coreboot-gerrit February 2021

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Change in coreboot[master]: soc/intel/broadwell: Convert some CONFIG(CHROMEOS) preprocessor
by Kyösti Mälkki (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Patrick Rudolph. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50252 ) Change subject: soc/intel/broadwell: Convert some CONFIG(CHROMEOS) preprocessor ...................................................................... soc/intel/broadwell: Convert some CONFIG(CHROMEOS) preprocessor Change-Id: Ie3feee0448175db2b6ed4e8e37d92de3af9be371 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/broadwell/gma.c 1 file changed, 1 insertion(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/50252/1 diff --git a/src/soc/intel/broadwell/gma.c b/src/soc/intel/broadwell/gma.c index 45d1833..b6ce426 100644 --- a/src/soc/intel/broadwell/gma.c +++ b/src/soc/intel/broadwell/gma.c @@ -515,12 +515,8 @@ /* Wait for any configured pre-graphics delay */ if (!acpi_is_wakeup_s3()) { -#if CONFIG(CHROMEOS) - if (display_init_required()) + if (!CONFIG(CHROMEOS) || display_init_required()) mdelay(CONFIG_PRE_GRAPHICS_DELAY); -#else - mdelay(CONFIG_PRE_GRAPHICS_DELAY); -#endif } /* Early init steps */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3feee0448175db2b6ed4e8e37d92de3af9be371 Gerrit-Change-Number: 50252 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: pci_ids/intel: Correct 0x3e96, it's a CFL-S part
by Patrick Georgi (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Nico Huber, Christian Walter, Patrick Rudolph. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50088 ) Change subject: pci_ids/intel: Correct 0x3e96, it's a CFL-S part ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdddb3309f862f52c578e91ba3dc310dff8f70bc Gerrit-Change-Number: 50088 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Timofey Komarov <happycorsair(a)yandex.ru> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 03 Feb 2021 08:57:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src: Remove unused <boardid.h>
by Patrick Georgi (Code Review) 03 Feb '21

03 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50183 ) Change subject: src: Remove unused <boardid.h> ...................................................................... src: Remove unused <boardid.h> Change-Id: I960870fabde1dacfe52a8a35c253b0bd097d3e10 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50183 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/mainboard/google/drallion/ramstage.c M src/mainboard/google/foster/pmic.c M src/mainboard/google/gale/cdp.c M src/mainboard/google/gale/mainboard.c M src/mainboard/google/hatch/variants/palkia/memory.c M src/mainboard/google/kahlee/OemCustomize.c M src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c M src/mainboard/google/kahlee/variants/baseboard/gpio.c M src/mainboard/google/nyan_big/pmic.c M src/mainboard/google/nyan_blaze/pmic.c M src/mainboard/google/octopus/variants/casta/gpio.c M src/mainboard/google/octopus/variants/dood/variant.c M src/mainboard/google/octopus/variants/fleex/gpio.c M src/mainboard/google/octopus/variants/lick/gpio.c M src/mainboard/google/smaug/pmic.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c M src/mainboard/google/zork/variants/berknip/gpio.c M src/mainboard/google/zork/variants/dalboz/gpio.c M src/mainboard/google/zork/variants/dirinboz/gpio.c M src/mainboard/google/zork/variants/ezkinil/gpio.c M src/mainboard/google/zork/variants/gumboz/gpio.c M src/mainboard/google/zork/variants/morphius/gpio.c M src/mainboard/google/zork/variants/shuboz/gpio.c M src/mainboard/google/zork/variants/trembyle/gpio.c M src/mainboard/google/zork/variants/vilboz/gpio.c M src/mainboard/intel/glkrvp/romstage.c M src/mainboard/intel/strago/acpi_tables.c M src/mainboard/intel/strago/gpio.c M src/mainboard/intel/strago/ramstage.c M src/mainboard/intel/strago/romstage.c M src/soc/mediatek/mt8173/emi.c M src/soc/qualcomm/common/qclib.c 34 files changed, 0 insertions(+), 34 deletions(-) Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved diff --git a/src/mainboard/google/drallion/ramstage.c b/src/mainboard/google/drallion/ramstage.c index 384e44b..ceba219 100644 --- a/src/mainboard/google/drallion/ramstage.c +++ b/src/mainboard/google/drallion/ramstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <boardid.h> #include <smbios.h> #include <soc/gpio.h> #include <soc/ramstage.h> diff --git a/src/mainboard/google/foster/pmic.c b/src/mainboard/google/foster/pmic.c index b9f2830..5ea0485 100644 --- a/src/mainboard/google/foster/pmic.c +++ b/src/mainboard/google/foster/pmic.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <boardid.h> #include <console/console.h> #include <delay.h> #include <device/i2c_simple.h> diff --git a/src/mainboard/google/gale/cdp.c b/src/mainboard/google/gale/cdp.c index ab7bc8c..7d29df8 100644 --- a/src/mainboard/google/gale/cdp.c +++ b/src/mainboard/google/gale/cdp.c @@ -4,7 +4,6 @@ #include <soc/cdp.h> #include <soc/ebi2.h> #include <soc/clock.h> -#include <boardid.h> void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned int count) { diff --git a/src/mainboard/google/gale/mainboard.c b/src/mainboard/google/gale/mainboard.c index cd55c93..39a3428 100644 --- a/src/mainboard/google/gale/mainboard.c +++ b/src/mainboard/google/gale/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <boardid.h> #include <boot/coreboot_tables.h> #include <device/device.h> #include <gpio.h> diff --git a/src/mainboard/google/hatch/variants/palkia/memory.c b/src/mainboard/google/hatch/variants/palkia/memory.c index 5b80203..f2a3a78 100644 --- a/src/mainboard/google/hatch/variants/palkia/memory.c +++ b/src/mainboard/google/hatch/variants/palkia/memory.c @@ -2,7 +2,6 @@ #include <baseboard/variants.h> #include <baseboard/gpio.h> -#include <boardid.h> #include <gpio.h> #include <soc/cnl_memcfg_init.h> #include <string.h> diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c index ec9ae3a..349fe34 100644 --- a/src/mainboard/google/kahlee/OemCustomize.c +++ b/src/mainboard/google/kahlee/OemCustomize.c @@ -2,7 +2,6 @@ #include <chip.h> #include <amdblocks/agesawrapper.h> -#include <boardid.h> #include <gpio.h> #include <console/console.h> #include <soc/pci_devs.h> diff --git a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c index 4b50d49..79fd478 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c +++ b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c @@ -2,7 +2,6 @@ #include <amdblocks/agesawrapper.h> #include <variant/gpio.h> -#include <boardid.h> #include <chip.h> #include <soc/pci_devs.h> diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index 8628074..22d8bb8 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -3,7 +3,6 @@ #include <baseboard/variants.h> #include <soc/gpio.h> #include <soc/southbridge.h> -#include <boardid.h> #include <variant/gpio.h> /* diff --git a/src/mainboard/google/nyan_big/pmic.c b/src/mainboard/google/nyan_big/pmic.c index d01c513..599907e 100644 --- a/src/mainboard/google/nyan_big/pmic.c +++ b/src/mainboard/google/nyan_big/pmic.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <boardid.h> #include <console/console.h> #include <delay.h> #include <device/i2c_simple.h> diff --git a/src/mainboard/google/nyan_blaze/pmic.c b/src/mainboard/google/nyan_blaze/pmic.c index d01c513..599907e 100644 --- a/src/mainboard/google/nyan_blaze/pmic.c +++ b/src/mainboard/google/nyan_blaze/pmic.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <boardid.h> #include <console/console.h> #include <delay.h> #include <device/i2c_simple.h> diff --git a/src/mainboard/google/octopus/variants/casta/gpio.c b/src/mainboard/google/octopus/variants/casta/gpio.c index 9c8e2a6..ea488ad 100644 --- a/src/mainboard/google/octopus/variants/casta/gpio.c +++ b/src/mainboard/google/octopus/variants/casta/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> diff --git a/src/mainboard/google/octopus/variants/dood/variant.c b/src/mainboard/google/octopus/variants/dood/variant.c index 1a8a371..635d721 100644 --- a/src/mainboard/google/octopus/variants/dood/variant.c +++ b/src/mainboard/google/octopus/variants/dood/variant.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <boardid.h> #include <sar.h> #include <baseboard/variants.h> #include <delay.h> diff --git a/src/mainboard/google/octopus/variants/fleex/gpio.c b/src/mainboard/google/octopus/variants/fleex/gpio.c index 8148dce..6dbc74a 100644 --- a/src/mainboard/google/octopus/variants/fleex/gpio.c +++ b/src/mainboard/google/octopus/variants/fleex/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> diff --git a/src/mainboard/google/octopus/variants/lick/gpio.c b/src/mainboard/google/octopus/variants/lick/gpio.c index e813fb1..089b28a 100644 --- a/src/mainboard/google/octopus/variants/lick/gpio.c +++ b/src/mainboard/google/octopus/variants/lick/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/smaug/pmic.c b/src/mainboard/google/smaug/pmic.c index 6644022..26a7e90 100644 --- a/src/mainboard/google/smaug/pmic.c +++ b/src/mainboard/google/smaug/pmic.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <boardid.h> #include <console/console.h> #include <delay.h> #include <device/i2c_simple.h> diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c index 0b658a4..948ce8f 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c @@ -3,7 +3,6 @@ #include <baseboard/variants.h> #include <soc/gpio.h> #include <stdlib.h> -#include <boardid.h> #include <variant/gpio.h> static const struct soc_amd_gpio early_gpio_table[] = { diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index 12d2890..473ffb1 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -6,7 +6,6 @@ #include <soc/gpio.h> #include <soc/smi.h> #include <stdlib.h> -#include <boardid.h> #include <variant/gpio.h> static const struct soc_amd_gpio gpio_set_stage_ram[] = { diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index a2ad517..341357e 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -8,7 +8,6 @@ #include <soc/gpio.h> #include <soc/smi.h> #include <stdlib.h> -#include <boardid.h> #include <variant/gpio.h> static const struct soc_amd_gpio gpio_set_stage_ram[] = { diff --git a/src/mainboard/google/zork/variants/berknip/gpio.c b/src/mainboard/google/zork/variants/berknip/gpio.c index ae2d02a..2452a1d 100644 --- a/src/mainboard/google/zork/variants/berknip/gpio.c +++ b/src/mainboard/google/zork/variants/berknip/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/zork/variants/dalboz/gpio.c b/src/mainboard/google/zork/variants/dalboz/gpio.c index 2b46938..a71aa78 100644 --- a/src/mainboard/google/zork/variants/dalboz/gpio.c +++ b/src/mainboard/google/zork/variants/dalboz/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/zork/variants/dirinboz/gpio.c b/src/mainboard/google/zork/variants/dirinboz/gpio.c index 7f9582c..aeebd07 100644 --- a/src/mainboard/google/zork/variants/dirinboz/gpio.c +++ b/src/mainboard/google/zork/variants/dirinboz/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/zork/variants/ezkinil/gpio.c b/src/mainboard/google/zork/variants/ezkinil/gpio.c index f86d926..295fb21 100644 --- a/src/mainboard/google/zork/variants/ezkinil/gpio.c +++ b/src/mainboard/google/zork/variants/ezkinil/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/zork/variants/gumboz/gpio.c b/src/mainboard/google/zork/variants/gumboz/gpio.c index aac25bb..501c144 100644 --- a/src/mainboard/google/zork/variants/gumboz/gpio.c +++ b/src/mainboard/google/zork/variants/gumboz/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> diff --git a/src/mainboard/google/zork/variants/morphius/gpio.c b/src/mainboard/google/zork/variants/morphius/gpio.c index 9b36e37..778c6e4 100644 --- a/src/mainboard/google/zork/variants/morphius/gpio.c +++ b/src/mainboard/google/zork/variants/morphius/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/zork/variants/shuboz/gpio.c b/src/mainboard/google/zork/variants/shuboz/gpio.c index 0fd867e..db20e44 100644 --- a/src/mainboard/google/zork/variants/shuboz/gpio.c +++ b/src/mainboard/google/zork/variants/shuboz/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/zork/variants/trembyle/gpio.c b/src/mainboard/google/zork/variants/trembyle/gpio.c index 4d73ea0..0546df4 100644 --- a/src/mainboard/google/zork/variants/trembyle/gpio.c +++ b/src/mainboard/google/zork/variants/trembyle/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/zork/variants/vilboz/gpio.c b/src/mainboard/google/zork/variants/vilboz/gpio.c index c6ef161..5c918fd 100644 --- a/src/mainboard/google/zork/variants/vilboz/gpio.c +++ b/src/mainboard/google/zork/variants/vilboz/gpio.c @@ -2,7 +2,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/intel/glkrvp/romstage.c b/src/mainboard/intel/glkrvp/romstage.c index f1e544c..868a4c6 100644 --- a/src/mainboard/intel/glkrvp/romstage.c +++ b/src/mainboard/intel/glkrvp/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <string.h> #include <baseboard/variants.h> -#include <boardid.h> #include <soc/meminit.h> #include <soc/romstage.h> diff --git a/src/mainboard/intel/strago/acpi_tables.c b/src/mainboard/intel/strago/acpi_tables.c index a600d0a..9f8187f 100644 --- a/src/mainboard/intel/strago/acpi_tables.c +++ b/src/mainboard/intel/strago/acpi_tables.c @@ -8,7 +8,6 @@ #include <soc/iomap.h> #include <soc/nvs.h> #include <soc/device_nvs.h> -#include <boardid.h> #include "onboard.h" void mainboard_fill_gnvs(struct global_nvs *gnvs) diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c index d3d6168..0e7f88c 100644 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -2,7 +2,6 @@ #include "irqroute.h" #include <soc/gpio.h> -#include <boardid.h> #include "onboard.h" #include "gpio.h" diff --git a/src/mainboard/intel/strago/ramstage.c b/src/mainboard/intel/strago/ramstage.c index eac843d..e7ed500 100644 --- a/src/mainboard/intel/strago/ramstage.c +++ b/src/mainboard/intel/strago/ramstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/ramstage.h> -#include <boardid.h> #include "onboard.h" void mainboard_silicon_init_params(SILICON_INIT_UPD *params) diff --git a/src/mainboard/intel/strago/romstage.c b/src/mainboard/intel/strago/romstage.c index 0bb4476..331db04 100644 --- a/src/mainboard/intel/strago/romstage.c +++ b/src/mainboard/intel/strago/romstage.c @@ -2,7 +2,6 @@ #include <soc/romstage.h> #include "onboard.h" -#include <boardid.h> void mainboard_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *memory_params) diff --git a/src/soc/mediatek/mt8173/emi.c b/src/soc/mediatek/mt8173/emi.c index aa8079e..b3a9693 100644 --- a/src/soc/mediatek/mt8173/emi.c +++ b/src/soc/mediatek/mt8173/emi.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/mmio.h> -#include <boardid.h> #include <console/console.h> #include <soc/addressmap.h> #include <soc/dramc_common.h> diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c index 9358890..daea209 100644 --- a/src/soc/qualcomm/common/qclib.c +++ b/src/soc/qualcomm/common/qclib.c @@ -2,7 +2,6 @@ #include <console/cbmem_console.h> #include <cbmem.h> -#include <boardid.h> #include <bootmode.h> #include <string.h> #include <fmap.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/50183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I960870fabde1dacfe52a8a35c253b0bd097d3e10 Gerrit-Change-Number: 50183 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: src: Remove unused <cbmem.h>
by Patrick Georgi (Code Review) 03 Feb '21

03 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50182 ) Change subject: src: Remove unused <cbmem.h> ...................................................................... src: Remove unused <cbmem.h> Change-Id: I2279e2d7e6255a88953b2485c1f1a3b51a72c65e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50182 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/lib/metadata_hash.c M src/security/vboot/vboot_loader.c M src/soc/amd/common/block/lpc/lpc.c M src/soc/amd/common/block/pi/refcode_loader.c M src/soc/intel/alderlake/acpi.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/baytrail/acpi.c M src/soc/intel/baytrail/refcode.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/pch/acpi.c M src/soc/intel/broadwell/refcode.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/icelake/acpi.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/tigerlake/acpi.c M src/soc/intel/xeon_sp/cpx/soc_acpi.c M src/soc/intel/xeon_sp/skx/soc_acpi.c 18 files changed, 0 insertions(+), 18 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/lib/metadata_hash.c b/src/lib/metadata_hash.c index f296cf5..a823c5f 100644 --- a/src/lib/metadata_hash.c +++ b/src/lib/metadata_hash.c @@ -2,7 +2,6 @@ /* This file is part of the coreboot project. */ #include <assert.h> -#include <cbmem.h> #include <metadata_hash.h> #include <symbols.h> diff --git a/src/security/vboot/vboot_loader.c b/src/security/vboot/vboot_loader.c index 56a0664..234ae8f 100644 --- a/src/security/vboot/vboot_loader.c +++ b/src/security/vboot/vboot_loader.c @@ -2,7 +2,6 @@ #include <boot_device.h> #include <cbfs.h> -#include <cbmem.h> #include <commonlib/bsd/cbfs_private.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index e0c0e42..7f3bea0 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <cbmem.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/soc/amd/common/block/pi/refcode_loader.c b/src/soc/amd/common/block/pi/refcode_loader.c index 274291d..9fc73d4 100644 --- a/src/soc/amd/common/block/pi/refcode_loader.c +++ b/src/soc/amd/common/block/pi/refcode_loader.c @@ -2,7 +2,6 @@ #include <acpi/acpi.h> #include <cbfs.h> -#include <cbmem.h> #include <console/console.h> #include <rmodule.h> #include <stage_cache.h> diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index 55ecc00..9800563 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -5,7 +5,6 @@ #include <acpi/acpigen.h> #include <device/mmio.h> #include <arch/smp/mpspec.h> -#include <cbmem.h> #include <console/console.h> #include <device/device.h> #include <device/pci_ops.h> diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 773f56e..2c271d2 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -9,7 +9,6 @@ #include <arch/smp/mpspec.h> #include <assert.h> #include <device/pci_ops.h> -#include <cbmem.h> #include <gpio.h> #include <intelblocks/acpi.h> #include <intelblocks/pmclib.h> diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 5433fdc..153ef04 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -6,7 +6,6 @@ #include <arch/ioapic.h> #include <device/mmio.h> #include <arch/smp/mpspec.h> -#include <cbmem.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <types.h> diff --git a/src/soc/intel/baytrail/refcode.c b/src/soc/intel/baytrail/refcode.c index 8cd7336..d8623ae 100644 --- a/src/soc/intel/baytrail/refcode.c +++ b/src/soc/intel/baytrail/refcode.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <cbmem.h> #include <console/console.h> #include <console/streams.h> #include <cpu/x86/tsc.h> diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index b9b3424..f60ebd8 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -4,7 +4,6 @@ #include <acpi/acpigen.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> -#include <cbmem.h> #include <cpu/intel/haswell/haswell.h> #include <device/pci_ops.h> #include <console/console.h> diff --git a/src/soc/intel/broadwell/pch/acpi.c b/src/soc/intel/broadwell/pch/acpi.c index 38f057e..48a83df 100644 --- a/src/soc/intel/broadwell/pch/acpi.c +++ b/src/soc/intel/broadwell/pch/acpi.c @@ -4,7 +4,6 @@ #include <acpi/acpigen.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> -#include <cbmem.h> #include <device/pci_ops.h> #include <console/console.h> #include <types.h> diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c index 31d6ad8..5d3ccce 100644 --- a/src/soc/intel/broadwell/refcode.c +++ b/src/soc/intel/broadwell/refcode.c @@ -2,7 +2,6 @@ #include <string.h> #include <acpi/acpi.h> -#include <cbmem.h> #include <console/console.h> #include <console/streams.h> #include <program_loading.h> diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 943c15e..37fe216 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -4,7 +4,6 @@ #include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> #include <arch/smp/mpspec.h> -#include <cbmem.h> #include <console/console.h> #include <device/mmio.h> #include <device/pci_ops.h> diff --git a/src/soc/intel/elkhartlake/acpi.c b/src/soc/intel/elkhartlake/acpi.c index ff7457c..ba64c04 100644 --- a/src/soc/intel/elkhartlake/acpi.c +++ b/src/soc/intel/elkhartlake/acpi.c @@ -4,7 +4,6 @@ #include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> #include <arch/smp/mpspec.h> -#include <cbmem.h> #include <console/console.h> #include <device/device.h> #include <device/mmio.h> diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index 6a8e329..67b7ca5 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -5,7 +5,6 @@ #include <acpi/acpigen.h> #include <device/mmio.h> #include <arch/smp/mpspec.h> -#include <cbmem.h> #include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> #include <intelblocks/acpi.h> diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index 7702bf0..a3c2b25 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -6,7 +6,6 @@ #include <device/device.h> #include <device/mmio.h> #include <arch/smp/mpspec.h> -#include <cbmem.h> #include <console/console.h> #include <device/pci_ops.h> #include <intelblocks/cpulib.h> diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index cb1731f..f3e821f 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -5,7 +5,6 @@ #include <acpi/acpigen.h> #include <device/mmio.h> #include <arch/smp/mpspec.h> -#include <cbmem.h> #include <console/console.h> #include <device/device.h> #include <device/pci_ops.h> diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index 99326ee..5e1b412 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -3,7 +3,6 @@ #include <acpi/acpigen.h> #include <arch/smp/mpspec.h> #include <assert.h> -#include <cbmem.h> #include <cpu/intel/turbo.h> #include <device/mmio.h> #include <device/pci.h> diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index 2d28623..79768d4 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -3,7 +3,6 @@ #include <acpi/acpigen.h> #include <arch/smp/mpspec.h> #include <assert.h> -#include <cbmem.h> #include <cpu/intel/turbo.h> #include <device/mmio.h> #include <device/pci.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/50182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2279e2d7e6255a88953b2485c1f1a3b51a72c65e Gerrit-Change-Number: 50182 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: src: Remove unused <cbmem.h>
by Patrick Georgi (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Andrey Petrov, Aaron Durbin, Patrick Rudolph, Felix Held. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50182 ) Change subject: src: Remove unused <cbmem.h> ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2279e2d7e6255a88953b2485c1f1a3b51a72c65e Gerrit-Change-Number: 50182 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 03 Feb 2021 08:56:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/ti/am335x/header.c: Add missing include
by HAOUAS Elyes (Code Review) 03 Feb '21

03 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44738 ) Change subject: soc/ti/am335x/header.c: Add missing include ...................................................................... soc/ti/am335x/header.c: Add missing include Use of 'offsetof' needs stddef. Change-Id: Ie250b20f464909649b2bd038dbb757d5df637486 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/ti/am335x/header.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/44738/1 diff --git a/src/soc/ti/am335x/header.c b/src/soc/ti/am335x/header.c index 9edfdd0..9ed9937 100644 --- a/src/soc/ti/am335x/header.c +++ b/src/soc/ti/am335x/header.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <stddef.h> #include <stdint.h> #include <symbols.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/44738 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie250b20f464909649b2bd038dbb757d5df637486 Gerrit-Change-Number: 44738 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: mb/google/volteer/variants/drobit: Modify touchpad I2C sequence
by Patrick Georgi (Code Review) 03 Feb '21

03 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49958 ) Change subject: mb/google/volteer/variants/drobit: Modify touchpad I2C sequence ...................................................................... mb/google/volteer/variants/drobit: Modify touchpad I2C sequence Modify touchpad I2C sequence to meet requirement. BUG=b:178512111 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot chromeos-bootimage build Pass And check the touchpad I2C5 sequence by EE. Signed-off-by: Wayne3_Wang <Wayne3_Wang(a)pegatron.corp-partner.google.com> Change-Id: Iebbeeec51b802c318ac014dcdd2603b600d931a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49958 Reviewed-by: Zhuohao Lee <zhuohao(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Reviewed-by: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/volteer/variants/drobit/overridetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Zhuohao Lee: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved Hao Chou: Looks good to me, but someone else must approve Wayne3 Wang: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/volteer/variants/drobit/overridetree.cb b/src/mainboard/google/volteer/variants/drobit/overridetree.cb index 8ce98de..17143b8 100644 --- a/src/mainboard/google/volteer/variants/drobit/overridetree.cb +++ b/src/mainboard/google/volteer/variants/drobit/overridetree.cb @@ -56,6 +56,12 @@ }, .i2c[5] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 155, + .scl_hcnt = 80, + .sda_hold = 36, + }, }, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/49958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebbeeec51b802c318ac014dcdd2603b600d931a9 Gerrit-Change-Number: 49958 Gerrit-PatchSet: 7 Gerrit-Owner: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alex1 Kao <alex1_kao(a)pegatron.corp-partner.google.com> Gerrit-CC: Ariel Chang <ariel_chang(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/volteer/variants/drobit: Add TBT PCIE rp setting for drobit
by Patrick Georgi (Code Review) 03 Feb '21

03 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50103 ) Change subject: mb/google/volteer/variants/drobit: Add TBT PCIE rp setting for drobit ...................................................................... mb/google/volteer/variants/drobit: Add TBT PCIE rp setting for drobit Add the TBT PCIE rp setting to on and also fixes system hang in recovery screen after selected "Power off" item problem. BUG=b:177963941 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot chromeos-bootimage build Pass And check the system can power off normally in recovery page Cq-Depend: chrome-internal:3581043 Signed-off-by: Wayne3_Wang <Wayne3_Wang(a)pegatron.corp-partner.google.com> Change-Id: Ic0a4756b4af839ea0a23febb991bd71af7733dcc Reviewed-on: https://review.coreboot.org/c/coreboot/+/50103 Reviewed-by: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Reviewed-by: Ariel Chang <ariel_chang(a)pegatron.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao(a)chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/volteer/variants/drobit/overridetree.cb 1 file changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Zhuohao Lee: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved Wayne3 Wang: Looks good to me, but someone else must approve Ariel Chang: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/volteer/variants/drobit/overridetree.cb b/src/mainboard/google/volteer/variants/drobit/overridetree.cb index 96c109f..8ce98de 100644 --- a/src/mainboard/google/volteer/variants/drobit/overridetree.cb +++ b/src/mainboard/google/volteer/variants/drobit/overridetree.cb @@ -60,6 +60,14 @@ }" device domain 0 on + device ref tbt_pcie_rp0 on + probe DB_USB USB4_GEN3 + end + + device ref tbt_pcie_rp1 on + probe DB_USB USB4_GEN3 + end + device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" -- To view, visit https://review.coreboot.org/c/coreboot/+/50103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0a4756b4af839ea0a23febb991bd71af7733dcc Gerrit-Change-Number: 50103 Gerrit-PatchSet: 4 Gerrit-Owner: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Ariel Chang <ariel_chang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alex1 Kao <alex1_kao(a)pegatron.corp-partner.google.com> Gerrit-CC: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-CC: Kirk Wang <kirk_wang(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: intel/xeon_sp: Select TPM_STARTUP_IGNORE_POSTINIT if INTEL_TXT is sel...
by Patrick Georgi (Code Review) 03 Feb '21

03 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50102 ) Change subject: intel/xeon_sp: Select TPM_STARTUP_IGNORE_POSTINIT if INTEL_TXT is selected ...................................................................... intel/xeon_sp: Select TPM_STARTUP_IGNORE_POSTINIT if INTEL_TXT is selected Because ACM already does TPM initialization. Change-Id: I49cc3b0077b220b0ca0bfa048be1e3d3d7023b05 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50102 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 7f7135e..49af384 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -57,6 +57,7 @@ select SOC_INTEL_COMMON_BLOCK_TCO select SOC_INTEL_COMMON_BLOCK_ACPI select TSC_MONOTONIC_TIMER + select TPM_STARTUP_IGNORE_POSTINIT if INTEL_TXT select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE -- To view, visit https://review.coreboot.org/c/coreboot/+/50102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49cc3b0077b220b0ca0bfa048be1e3d3d7023b05 Gerrit-Change-Number: 50102 Gerrit-PatchSet: 4 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: hatch: Update fan and thermal settings for ambassador
by Patrick Georgi (Code Review) 03 Feb '21

03 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50100 ) Change subject: hatch: Update fan and thermal settings for ambassador ...................................................................... hatch: Update fan and thermal settings for ambassador Update fan and thermal settings for ambassador, per recommendations from Quanta. BUG=b:177765580 TEST=Built AP firmware Change-Id: I080859f872caf696f0c085defb8372de658da58a Signed-off-by: Neill Corlett <corlett(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50100 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Joe Tessler <jrt(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/hatch/variants/ambassador/overridetree.cb 1 file changed, 8 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Joe Tessler: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/hatch/variants/ambassador/overridetree.cb b/src/mainboard/google/hatch/variants/ambassador/overridetree.cb index 7cc920d..b4f3609 100644 --- a/src/mainboard/google/hatch/variants/ambassador/overridetree.cb +++ b/src/mainboard/google/hatch/variants/ambassador/overridetree.cb @@ -213,15 +213,14 @@ ## Active Policy register "policies.active[0]" = "{.target=DPTF_CPU, .thresholds={TEMP_PCT(94, 0),}}" - register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_1, - .thresholds={TEMP_PCT(70, 100), - TEMP_PCT(66, 90), - TEMP_PCT(62, 80), - TEMP_PCT(58, 70), - TEMP_PCT(53, 60), - TEMP_PCT(48, 50), - TEMP_PCT(43, 40), - TEMP_PCT(38, 30),}}" + register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, + .thresholds={TEMP_PCT(72, 90), + TEMP_PCT(68, 80), + TEMP_PCT(64, 70), + TEMP_PCT(58, 60), + TEMP_PCT(51, 50), + TEMP_PCT(42, 40), + TEMP_PCT(35, 30),}}" ## Passive Policy register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" -- To view, visit https://review.coreboot.org/c/coreboot/+/50100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I080859f872caf696f0c085defb8372de658da58a Gerrit-Change-Number: 50100 Gerrit-PatchSet: 4 Gerrit-Owner: Neill Corlett <corlett(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Joe Tessler <jrt(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matthew Ziegelbaum <ziegs(a)google.com> Gerrit-MessageType: merged

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coreboot-gerrit February 2021