coreboot-gerrit February 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/biostar/th61-itx/early_init.c: Clean includes
by Patrick Georgi (Code Review) 03 Feb '21

03 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50200 ) Change subject: mb/biostar/th61-itx/early_init.c: Clean includes ...................................................................... mb/biostar/th61-itx/early_init.c: Clean includes Change-Id: I0619e567527812bd0e7088d23d91f114c8fec9ec Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50200 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/biostar/th61-itx/early_init.c 1 file changed, 1 insertion(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/biostar/th61-itx/early_init.c b/src/mainboard/biostar/th61-itx/early_init.c index b1a99e0..9d537e6 100644 --- a/src/mainboard/biostar/th61-itx/early_init.c +++ b/src/mainboard/biostar/th61-itx/early_init.c @@ -1,9 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <bootblock_common.h> #include <northbridge/intel/sandybridge/raminit_native.h> -#include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/pch.h> +#include <stdbool.h> const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, -- To view, visit https://review.coreboot.org/c/coreboot/+/50200 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0619e567527812bd0e7088d23d91f114c8fec9ec Gerrit-Change-Number: 50200 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/aspeed: Fix some issues
by Patrick Georgi (Code Review) 03 Feb '21

03 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50195 ) Change subject: drivers/aspeed: Fix some issues ...................................................................... drivers/aspeed: Fix some issues * Use probe_resource instead of find_resource. This prevents a call to die and instead returns NULL. * Handle the case where BAR2 isn't present * Don't hardcode legacy VGA when BAR2 is present. This fixes graphic initialisation when the Aspeed isn't the primary GPU and thus doesn't decode VGA cycles. This makes the coreboot code more similar to the Linux kernel code. Change-Id: I2a99712a562a57c65f1cd0df7b1d7606681afe9b Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50195 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/aspeed/common/ast_main.c 1 file changed, 4 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/drivers/aspeed/common/ast_main.c b/src/drivers/aspeed/common/ast_main.c index 89194ad..30d1131 100644 --- a/src/drivers/aspeed/common/ast_main.c +++ b/src/drivers/aspeed/common/ast_main.c @@ -393,7 +393,7 @@ ast->dev = dev; /* PCI BAR 1 */ - res = find_resource(dev->pdev, PCI_BASE_ADDRESS_1); + res = probe_resource(dev->pdev, PCI_BASE_ADDRESS_1); if (!res) { dev_err(dev->pdev, "BAR1 resource not found.\n"); ret = -EIO; @@ -407,19 +407,16 @@ /* PCI BAR 2 */ ast->io_space_uses_mmap = false; - res = find_resource(dev->pdev, PCI_BASE_ADDRESS_2); - if (!res) { + res = probe_resource(dev->pdev, PCI_BASE_ADDRESS_2); + if (!res) dev_err(dev->pdev, "BAR2 resource not found.\n"); - ret = -EIO; - goto out_free; - } /* * If we don't have IO space at all, use MMIO now and * assume the chip has MMIO enabled by default (rev 0x20 * and higher). */ - if (!(res->flags & IORESOURCE_IO)) { + if (!res || !(res->flags & IORESOURCE_IO)) { DRM_INFO("platform has no IO space, trying MMIO\n"); ast->ioregs = ast->regs + AST_IO_MM_OFFSET; ast->io_space_uses_mmap = true; @@ -432,8 +429,6 @@ ret = -EIO; goto out_free; } - /* Adjust the I/O space location to match expectations (the code expects offset 0x0 to be I/O location 0x380) */ - ast->ioregs = (void *)AST_IO_MM_OFFSET; } ast_detect_chip(dev, &need_post); -- To view, visit https://review.coreboot.org/c/coreboot/+/50195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a99712a562a57c65f1cd0df7b1d7606681afe9b Gerrit-Change-Number: 50195 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne: Replace the PSP Bootloader with AB version
by Bao Zheng (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Felix Held. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50251 ) Change subject: soc/amd/cezanne: Replace the PSP Bootloader with AB version ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: This need to wait for PSP updating. -- To view, visit https://review.coreboot.org/c/coreboot/+/50251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdcee65e7dcc30d7ee7a58338f439eaee5cd942e Gerrit-Change-Number: 50251 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 03 Feb 2021 08:53:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/sarien: Turn `hda_verb.h` into `hda_verb.c`
by Patrick Georgi (Code Review) 03 Feb '21

03 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50175 ) Change subject: mb/google/sarien: Turn `hda_verb.h` into `hda_verb.c` ...................................................................... mb/google/sarien: Turn `hda_verb.h` into `hda_verb.c` Change-Id: I40c8145fdddf9605bc3cc66ae8075e52dca4e539 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50175 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/sarien/Makefile.inc D src/mainboard/google/sarien/hda_verb.c R src/mainboard/google/sarien/variants/arcada/hda_verb.c R src/mainboard/google/sarien/variants/sarien/hda_verb.c 4 files changed, 1 insertion(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/sarien/Makefile.inc b/src/mainboard/google/sarien/Makefile.inc index 12e08be..6bc69ef 100644 --- a/src/mainboard/google/sarien/Makefile.inc +++ b/src/mainboard/google/sarien/Makefile.inc @@ -12,7 +12,7 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += variants/$(VARIANT_DIR)/hda_verb.c bootblock-$(CONFIG_EC_GOOGLE_WILCO) += ec.c ramstage-$(CONFIG_EC_GOOGLE_WILCO) += ec.c diff --git a/src/mainboard/google/sarien/hda_verb.c b/src/mainboard/google/sarien/hda_verb.c deleted file mode 100644 index c260297..0000000 --- a/src/mainboard/google/sarien/hda_verb.c +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include "variant/hda_verb.h" diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/hda_verb.h b/src/mainboard/google/sarien/variants/arcada/hda_verb.c similarity index 97% rename from src/mainboard/google/sarien/variants/arcada/include/variant/hda_verb.h rename to src/mainboard/google/sarien/variants/arcada/hda_verb.c index 83acbc2..b447e9f 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/hda_verb.h +++ b/src/mainboard/google/sarien/variants/arcada/hda_verb.c @@ -1,8 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef MAINBOARD_HDA_VERB_H -#define MAINBOARD_HDA_VERB_H - #include <device/azalia_device.h> const u32 cim_verb_data[] = { @@ -192,5 +189,3 @@ }; AZALIA_ARRAY_SIZES; - -#endif diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/hda_verb.h b/src/mainboard/google/sarien/variants/sarien/hda_verb.c similarity index 96% rename from src/mainboard/google/sarien/variants/sarien/include/variant/hda_verb.h rename to src/mainboard/google/sarien/variants/sarien/hda_verb.c index 5ec53ed..316b110 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/hda_verb.h +++ b/src/mainboard/google/sarien/variants/sarien/hda_verb.c @@ -1,8 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef MAINBOARD_HDA_VERB_H -#define MAINBOARD_HDA_VERB_H - #include <device/azalia_device.h> const u32 cim_verb_data[] = { @@ -135,5 +132,3 @@ }; AZALIA_ARRAY_SIZES; - -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/50175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40c8145fdddf9605bc3cc66ae8075e52dca4e539 Gerrit-Change-Number: 50175 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel: Fix compilation on x86_64
by Patrick Rudolph (Code Review) 03 Feb '21

03 Feb '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49080 ) Change subject: soc/intel: Fix compilation on x86_64 ...................................................................... soc/intel: Fix compilation on x86_64 Change-Id: I18a0c18fe1c64611f95bc423916447c89585db9f Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/common/block/include/intelblocks/systemagent.h 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/49080/1 diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h index cf56138..d707062 100644 --- a/src/soc/intel/common/block/include/intelblocks/systemagent.h +++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h @@ -18,10 +18,10 @@ #define TOLUD 0xbc /* Top of Low Used Memory */ /* MCHBAR */ -#define MCHBAR8(x) (*(volatile u8 *)(MCH_BASE_ADDRESS + x)) -#define MCHBAR16(x) (*(volatile u16 *)(MCH_BASE_ADDRESS + x)) -#define MCHBAR32(x) (*(volatile u32 *)(MCH_BASE_ADDRESS + x)) -#define MCHBAR64(x) (*(volatile u64 *)(MCH_BASE_ADDRESS + x)) +#define MCHBAR8(x) (*(volatile u8 *)(uintptr_t)(MCH_BASE_ADDRESS + x)) +#define MCHBAR16(x) (*(volatile u16 *)(uintptr_t)(MCH_BASE_ADDRESS + x)) +#define MCHBAR32(x) (*(volatile u32 *)(uintptr_t)(MCH_BASE_ADDRESS + x)) +#define MCHBAR64(x) (*(volatile u64 *)(uintptr_t)(MCH_BASE_ADDRESS + x)) /* Perform System Agent Initialization during Bootblock phase */ void bootblock_systemagent_early_init(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/49080 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18a0c18fe1c64611f95bc423916447c89585db9f Gerrit-Change-Number: 49080 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne: Replace the PSP Bootloader with AB version
by Bao Zheng (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/50251 to review the following change. Change subject: soc/amd/cezanne: Replace the PSP Bootloader with AB version ...................................................................... soc/amd/cezanne: Replace the PSP Bootloader with AB version Change-Id: Ibdcee65e7dcc30d7ee7a58338f439eaee5cd942e Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/cezanne/fw.cfg 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/50251/1 diff --git a/src/soc/amd/cezanne/fw.cfg b/src/soc/amd/cezanne/fw.cfg index 277707d..34245de 100644 --- a/src/soc/amd/cezanne/fw.cfg +++ b/src/soc/amd/cezanne/fw.cfg @@ -5,7 +5,7 @@ # type file # PSP AMD_PUBKEY_FILE TypeId0x00_CezannePublicKey.tkn -PSPBTLDR_FILE TypeId0x01_PspBootLoader_CZN.sbin +PSPBTLDR_FILE TypeId0x01_PspBootLoader_AB_Stage1_CZN.sbin PSPSECUREOS_FILE TypeId0x02_PspOS_CZN.sbin PSPRCVR_FILE TypeId0x03_PspRecoveryBootLoader_CZN.sbin PSP_SMUFW1_SUB0_FILE TypeId0x08_SmuFirmware_CZN.csbin -- To view, visit https://review.coreboot.org/c/coreboot/+/50251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdcee65e7dcc30d7ee7a58338f439eaee5cd942e Gerrit-Change-Number: 50251 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/ocp/deltalake: Fill ECC type in romstage
by Patrick Rudolph (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Christian Walter, Angel Pons, Arthur Heymans, Morgan Jang, Patrick Rudolph. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50179 ) Change subject: mb/ocp/deltalake: Fill ECC type in romstage ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: How was it tested? -- To view, visit https://review.coreboot.org/c/coreboot/+/50179 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8370b3ee7d75914b895946b53923598adf87b522 Gerrit-Change-Number: 50179 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 03 Feb 2021 08:30:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: memory_info.h: Store SMBIOS error correction type
by Patrick Rudolph (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Christian Walter, Angel Pons, Arthur Heymans, Patrick Rudolph. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50178 ) Change subject: memory_info.h: Store SMBIOS error correction type ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File src/include/memory_info.h: https://review.coreboot.org/c/coreboot/+/50178/comment/d05029c4_2c0710f7 PS1, Line 103: uint8_t ecc_type; This struct is a mess already as some types from SMBIOS are used while other fields have a custom encoding. Please use enum smbios_memory_array_ecc instead. -- To view, visit https://review.coreboot.org/c/coreboot/+/50178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I863f8e34c84841d931dfb8d7067af0f12a437e36 Gerrit-Change-Number: 50178 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 03 Feb 2021 08:30:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/variant/copano: support regular/numpad touchpad
by Zhuohao Lee (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Nick Vaccaro, Zhuohao Lee. Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50129 ) Change subject: mb/google/volteer/variant/copano: support regular/numpad touchpad ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/50129/comment/a6df3118_36009e1f PS1, Line 13: BRANCH=firmware-volteer-13672.B-mai > BRANCH=firmware-volteer-13672. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/50129 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5d61f19fd385600cfdcdd045dab1e61b06e4663 Gerrit-Change-Number: 50129 Gerrit-PatchSet: 2 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Wed, 03 Feb 2021 08:23:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add support for external clock buffer
by Furquan Shaikh (Code Review) 03 Feb '21

03 Feb '21

Attention is currently required from: Tim Wawrzynczak, Subrata Banik, Angel Pons, Patrick Rudolph, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50162 ) Change subject: soc/intel/alderlake: Add support for external clock buffer ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/50162/comment/17fdde1d_825d0a6e PS1, Line 9: 3 CLKSRC using external clock buffer. : CLKSRC 6 provides feed clock to discrete buffer for further : distribution to platform. > Could you share the schematic to me, just for the external clock part. […] Thanks for the details, Angel! That makes sense to me. Before we add any Kconfigs, I think we need to understand how the internal v/s external clock sources need to be described. * Are these clocks associated with different root ports? --> My understanding is yes. * How does FSP treat the internal v/s external clock sources? What we know so far: * One of the internal clock sources needs to be configured as free running because it is used as input to external clock chip. * The external clock chip generates upto 4 external clock sources. * These external clock sources can be requested by CLKREQ# signals 7-10 which result in PCH driving the OE# signals going to the external clock chip. Subrata - do you have any documentation that talks more about how the external clock chip configuration really works i.e. usage of OE# pins and CLKSRC/CLKREQ configuration, etc. -- To view, visit https://review.coreboot.org/c/coreboot/+/50162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If49d756ed47d577fd839516d4e707563700453d2 Gerrit-Change-Number: 50162 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 03 Feb 2021 08:15:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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coreboot-gerrit February 2021